Packaging structure of semiconductor power device
By designing the package structure of three MOS tubes, the source and gate of the MOS tube are distributed on both sides of the package structure and the drain is located in the middle, solving the dilemma of packaging in the prior art between solving large currents and reducing patch costs, achieving a more uniform current distribution and a larger heat dissipation area, simplifying the PCB trace design, and improving the stability and reliability of the device.
Patent Information
- Application Number
- CN202421351390.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-14
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-06-14
AI Technical Summary
The packaging of existing semiconductor power devices has difficulties in solving large currents and reducing patch costs, and the PCB trace design is complex.
A package structure including three MOS tubes is designed. The source and gate of the MOS tube are distributed on both sides of the package structure. The drain is located in the middle. The pad area of the drain is larger than the pad area of the source and gate, forming six pins to achieve a more uniform current distribution and a larger heat dissipation area.
This package structure can effectively solve the demand for large currents, while reducing patch costs, simplifying PCB trace design, and improving device stability and reliability.
Smart Images
Figure CN222690677U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, in particular to a packaging structure of a semiconductor power device. Background Art
[0002] The existing semiconductor power device packaging mainly includes single package and double package, such as Figure 1 and Figure 2 As shown in the figure, G is the gate of the MOS tube, D is the drain of the MOS tube, and S is the source of the MOS tube. Only one MOS tube is encapsulated, and the current of a single MOS tube can be very large, but the volume and space are large, the cost is high, the back-end patch processing fee is expensive, and the PCB design and routing are complicated; Figure 3 and Figure 4 As shown, G1 and G2 are the gates of the first MOS tube and the second MOS tube respectively, D1 and D2 are the drains of the first MOS tube and the second MOS tube respectively, S1 and S2 are the sources of the first MOS tube and the second MOS tube respectively, and the two MOS tubes are sealed together, the volume is small, the pad area of the pin is smaller, the current is smaller, the back-end patch addition is better than a single one, and the PCB design and routing are complicated.
[0003] In the field of motor commutation applications, such as Figure 5 As shown, six MOS tubes are usually required for phase switching. Currently, semiconductor packaging mainly includes single chip and two-chip package. If a single chip package is used, six chips are required. Although the current of a single chip package can be very large, there are problems such as large volume and space, high cost, expensive back-end patch processing fee, and complex PCB routing. If a double chip package is used, three chips are required. The double chip package reduces the volume, but the current also decreases accordingly. At the same time, the back-end patch processing fee has certain advantages over the single chip package, but the PCB routing is still complex.
[0004] In the fields of motor commutation applications, there is an urgent need for a semiconductor package that can not only solve the high current problem, but also reduce the post-processing cost of the chip, while simplifying the PCB routing design. Utility Model Content
[0005] In order to solve the technical problem that the existing semiconductor power devices cannot take into account both high current and chip cost, the utility model provides a packaging structure of a semiconductor power device.
[0006] In order to achieve the above object, the technical solution of the utility model is implemented as follows:
[0007] As a first aspect of the utility model, a packaging structure of a semiconductor power device includes three MOS tubes, wherein the source and gate of the MOS tubes are distributed on both sides of the packaging structure, the drain of the MOS tube is located in the middle of the packaging structure, the pad area of the drain is larger than the pad area of the source, and the pad area of the source is larger than the pad area of the gate.
[0008] By distributing the source and gate of the three MOS tubes on both sides of the package structure to form six pins, and placing the drain in the middle, a more uniform current distribution can be achieved. The pad area of the drain is the largest, which is conducive to heat dissipation and improves the stability and reliability of the device.
[0009] Designing the pad area of the drain electrode to be larger than the pad area of the source electrode, and the pad area of the source electrode to be larger than the pad area of the gate electrode, can effectively reduce the resistance of the pad, reduce the on-state voltage drop and power consumption of the device, and improve the efficiency of the circuit. The gate is a weak current, and the pad area is the smallest.
[0010] The space utilization rate is high. By rationally arranging the packaging structure of the MOS tube, the entire packaging structure is made more compact in space, which is beneficial to reducing the size of the device, improving the integration of the equipment, and reducing the manufacturing cost.
[0011] Compared with single or double MOS tube packaging, this packaging structure can reduce welding interfaces, simplify manufacturing processes, reduce production costs, and improve production efficiency.
[0012] The PCB layout is simple. Due to the reasonable design of the pad area and the compactness of the packaging structure, the PCB layout is relatively simple, which reduces the complexity of routing, reduces the design difficulty, and improves the reliability and stability of the circuit.
[0013] Furthermore, the source pad is square in shape; the drain pad is L-shaped, consisting of a square area and a strip area; the gate pad is strip-shaped; the gate pad is parallel to the strip area, and the left side of the gate pad is aligned with the left side of the square area.
[0014] The source pad is square in shape, and the drain pad is L-shaped, including a square area and a strip area, so that the drain pad area is larger, which can improve the thermal conductivity of the device, effectively reduce the temperature, and increase the working stability and life of the device.
[0015] The gate pad is strip-shaped and parallel to the strip area of the drain pad. The left side of the gate pad is aligned with the left side of the square area. This design makes the entire packaging structure more compact, which is conducive to improving the integration of the device and reducing the overall size.
[0016] Simplify PCB layout. Reasonable design of pad shape makes PCB layout simpler, reduces routing complexity, reduces design difficulty, and improves circuit reliability and stability.
[0017] The design of the pad can optimize the thermal conductivity of the package structure, increase integration, simplify PCB layout and improve manufacturing processability, thereby comprehensively improving the performance and reliability of semiconductor devices.
[0018] As a second aspect of the utility model, a semiconductor power device packaging structure includes three MOS tubes, the gate, source and gate of the MOS tubes are distributed on both sides of the packaging structure, and three drain pads are formed in the middle of the bottom of the packaging structure. The three drain pads are connected in parallel and integrated;
[0019] On one side of the packaging structure, six small pads are distributed in sequence, including a small drain pad and / or a small gate pad; on the other side of the packaging structure, six small pads are distributed in sequence, including a small source pad and / or a small gate pad, or the source pads are connected in parallel and integrated.
[0020] Large pads provide a larger heat dissipation area, effectively reducing the operating temperature of the device and improving the heat dissipation performance of the power device. Large pads can carry larger currents, improve the current handling capacity of power devices, and reduce conduction losses. The reasonable distribution of small pads makes the connection of gate, source and drain more flexible.
[0021] As the third aspect of the utility model, a packaging structure of a semiconductor power device includes three MOS tubes, three large drain pads are formed in the middle of the bottom of the packaging structure, at most two gate pads are formed on the right side of the bottom of the packaging structure, at most two small drain pads connected to the large drain pads are formed on the right side of the bottom of the packaging structure, and the source pad and at least one gate pad of the MOS tube are formed on the left side of the packaging structure.
[0022] The large drain pad at the bottom of the package can dissipate heat more effectively, helping to reduce the device operating temperature and improve the device's stability and reliability.
[0023] The beneficial effects brought by implementing the utility model are:
[0024] The utility model provides a semiconductor power device packaging structure with six pins on both sides and the drain in the middle, which can handle large currents, reduce the cost of post-processing chips, and simplify the PCB routing design; when used in motor commutation circuits, only two are needed, which reduces the number of chips, simplifies PCB design and layout, and reduces subsequent patch costs compared to single MOS and dual MOS packaging structures. It can be seen that the semiconductor power device packaging structure provided by the utility model can solve the problems of large currents, simple routing, and optimal post-processing chips in motor commutation applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 It is a symbol diagram of a single MOS tube element in the prior art;
[0026] Figure 2 This is a diagram of a single MOS tube packaging structure in the prior art;
[0027] Figure 3 It is a symbol diagram of a dual MOS tube component in the prior art;
[0028] Figure 4 It is a double MOS tube packaging structure diagram in the prior art;
[0029] Figure 5 It is a three-phase full-bridge circuit diagram in the prior art;
[0030] Figure 6 The three MOS tube packaging structure provided in the utility model Figure 1 ;
[0031] Figure 7 The three MOS tube packaging structure provided in the utility model Figure 2 ;
[0032] Figure 8 The three MOS tube packaging structure provided in the utility model Figure 3 ;
[0033] Fig. 9 The three MOS tube packaging structure provided in the utility model Figure 4 ;
[0034] Fig.10 The three MOS tube packaging structure provided in the utility model Figure 5 ;
[0035] Fig.11 The three MOS tube packaging structure provided in the utility model Figure 6 ;
[0036] Fig.12 The three MOS tube packaging structure provided in the utility model Figure 7 . DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.
[0038] Embodiment 1
[0039] See also Figure 6 The utility model provides a semiconductor power device packaging structure, which includes three MOS tubes inside, the source and gate of the MOS tubes are distributed on both sides of the packaging structure, and three source pads, drain pads and gate pads are formed at the bottom of the packaging structure, that is, the source pad is divided into a first source pad S1, a second source pad S2, and a third source pad S3, which are spaced and distributed in parallel; the gate pad is divided into a first gate pad G1, a second gate pad G2, and a third gate pad G3, which are spaced and distributed in parallel. The main part of the drain pad is located in the middle, including a first drain pad D1, a second drain pad D2, and a third drain pad D3, and can also extend to the right.
[0040] The source of the MOS tube is located on the left side of the drain, and the gate of the MOS tube is located on the right side of the drain. The pad area of the drain is larger than the pad area of the source, and the pad area of the source is larger than the pad area of the gate.
[0041] In one embodiment, the gate pad area is approximately one-half of the source pad area, and the source pad area is approximately one-third of the drain pad area.
[0042] By distributing the source and gate of the three MOS tubes on both sides of the package structure to form six pins, and placing the drain in the middle, a more uniform current distribution can be achieved. The pad area of the drain is the largest, which is conducive to heat dissipation and improves the stability and reliability of the device.
[0043] Designing the pad area of the drain electrode to be larger than the pad area of the source electrode, and the pad area of the source electrode to be larger than the pad area of the gate electrode, can effectively reduce the resistance of the pad, reduce the on-state voltage drop and power consumption of the device, and improve the efficiency of the circuit. The gate is the control terminal and the gate is a weak current, so the pad area is the smallest.
[0044] The space utilization rate is high. By rationally arranging the packaging structure of the MOS tube, the entire packaging structure is made more compact in space, which is beneficial to reducing the size of the device, improving the integration of the equipment, and reducing the manufacturing cost.
[0045] Compared with single or double MOS tube packaging, this packaging structure can reduce welding interfaces, simplify manufacturing processes, reduce production costs, and improve production efficiency.
[0046] The PCB layout is simple. Due to the reasonable design of the pad area and the compactness of the packaging structure, the PCB layout is relatively simple, which reduces the complexity of routing, reduces the design difficulty, and improves the reliability and stability of the circuit.
[0047] Furthermore, the source pad is square in shape; the drain pad is L-shaped, consisting of a square area and a strip area; the gate pad is strip-shaped; the gate pad is parallel to the strip area, and the left side of the gate pad is aligned with the left side of the square area.
[0048] The source pad is square in shape, and the drain pad is L-shaped, including a square area and a strip area, so that the drain pad area is larger, which can improve the thermal conductivity of the device, effectively reduce the temperature, and increase the working stability and life of the device.
[0049] The gate pad is strip-shaped and parallel to the strip area of the drain pad. The left side of the gate pad is aligned with the left side of the square area. This design makes the entire packaging structure more compact, which is conducive to improving the integration of the device and reducing the overall size.
[0050] Simplify PCB layout. Reasonable design of pad shape makes PCB layout simpler, reduces routing complexity, reduces design difficulty, and improves circuit reliability and stability.
[0051] The design of the pad can optimize the thermal conductivity of the package structure, increase integration, simplify PCB layout and improve manufacturing processability, thereby comprehensively improving the performance and reliability of semiconductor devices.
[0052] Embodiment 2
[0053] See also Figure 7 The utility model provides a semiconductor power device packaging structure, including three MOS tubes, the drain pads of the MOS tubes are distributed in the middle and right sides, and the source and gate of the MOS tubes are distributed on the left side of the packaging structure.
[0054] Embodiment 3
[0055] See also Figure 8 The utility model provides a packaging structure of a semiconductor power device, including three MOS tubes, including a first drain pad D1, a second drain pad D2, a third drain pad D3, a first source pad S1, a second source pad S2, a third source pad S3, a first gate pad G1, a second gate pad G2, and a third gate pad G3.
[0056] The first drain pad D1, the second drain pad D2, and the third drain pad D3 are distributed in the middle and right sides of the packaging structure, the second gate pad G2 is distributed on the right side of the packaging structure, and the first source pad S1, the second source pad S2, the third source pad S3, the first gate pad G1, and the third gate pad G3 are distributed on the left side of the packaging structure.
[0057] Embodiment 4
[0058] See also Fig. 9 The utility model provides a packaging structure of a semiconductor power device, including three MOS tubes, a first drain pad D1, a second drain pad D2, and a third drain pad D3 are distributed in the middle and right sides of the packaging structure, a first gate pad G1 and a third gate pad G3 are distributed on the right side of the packaging structure, and a first source pad S1, a second source pad S2, a third source pad S3, and a second gate pad G2 are distributed on the left side of the packaging structure.
[0059] Embodiment 5
[0060] See also Fig.10 The utility model provides a packaging structure of a semiconductor power device, including three MOS tubes, a first drain pad D1, a second drain pad D2, and a third drain pad D3 are distributed in the middle and right sides of the packaging structure, a first gate pad G1 and a third gate pad G3 are distributed on the right side of the packaging structure, a first source pad S1, a second source pad S2, a third source pad S3, and a second gate pad G2 are distributed on the left side of the packaging structure, wherein the first source pad G1 and the second source pad G2 are connected in parallel.
[0061] See also Fig.11 The utility model provides a packaging structure of a semiconductor power device, including three MOS tubes, wherein the gate, source and gate level of the MOS tubes are distributed on both sides of the packaging structure, and three drain pads are formed in the middle of the bottom of the packaging structure, that is, the drain pads are divided into a first drain pad, a second drain pad and a third drain pad.
[0062] On the right side of the packaging structure, there are six pins distributed in sequence, namely the first drain pin, the first drain pin, the second drain pin, the second drain pin, the third drain pin, and the third drain pin; on the left side of the packaging structure, there are six pins distributed in sequence, namely the first gate pin, the first source pin, the second gate pin, the second source pin, the third gate pin, and the third source pin.
[0063] Embodiment 7
[0064] See also Fig.12The utility model provides a packaging structure of a semiconductor power device, including three MOS tubes, wherein the gate, source and gate level of the MOS tubes are distributed on both sides of the packaging structure, and three drain pads are formed in the middle of the bottom of the packaging structure, that is, the drain pads are divided into a first drain pad, a second drain pad and a third drain pad.
[0065] On the right side of the packaging structure, there are six pins distributed in sequence, namely the first gate pin, the first drain pin, the second gate pin, the second drain pin, the third gate pin, and the third drain pin; on the left side of the packaging structure, there are six pins distributed in sequence, namely the first source pin, the first source pin, the second source pin, the second source pin, the third source pin, and the third source pin.
[0066] By integrating three MOS tubes into one package structure, the overall size is made more compact, which is suitable for application scenarios with limited space.
[0067] The heat dissipation performance is excellent, and the three drain pads design at the bottom effectively increases the heat dissipation area and improves the heat dissipation performance of the device, thereby improving the working stability and reliability of the device.
[0068] Six pins are set on both sides of the package structure. Multiple pin distribution helps to achieve better current distribution, reduce current density and improve power handling capability.
[0069] In the above scheme, two different types can be set, one is that three drain pads are directly connected in parallel as the upper tube, and the other is that three source pads are directly connected in parallel as the lower tube. When the drain is connected in parallel to the power supply, the source is separated and outputs three-phase AC power respectively; when the source is connected in parallel to the ground, the drain is separated and outputs three-phase AC power respectively. This further increases the convenience of post-welding.
[0070] The beneficial effects of implementing the semiconductor power device packaging structure provided by the utility model are as follows:
[0071] The utility model provides a packaging structure for a semiconductor power device, with six pins on both sides and the drain in the middle, which can handle large currents, reduce the processing costs of the subsequent patch, and simplify the PCB routing design; when used in a motor commutation circuit, only two are needed. Compared with the packaging structure of a single MOS and a double MOS, the number of chips is reduced, the PCB design and layout are simplified, the routing is simple, and the subsequent patch costs are reduced. It can be seen that the packaging structure of the semiconductor power device provided by the utility model can solve the problem of meeting large current requirements in motor commutation applications, improve the application performance of motor commutation, and balance the comprehensive volume and space to achieve balanced thermal efficiency.
[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A packaging structure of a semiconductor power device, characterized in that: It includes three MOS tubes, the source and gate of the MOS tubes are distributed on both sides of the packaging structure, and three source pads, drain pads and gate pads are formed at the bottom of the packaging structure respectively. The drain pad is located in the middle of the packaging structure, the area of the drain pad is larger than the area of the source pad, and the area of the source pad is larger than the area of the gate pad.
2. The packaging structure of a semiconductor power device according to claim 1, characterized in that: The source pad is square in shape; the drain pad is L-shaped, consisting of a square area and a strip area; the gate pad is strip-shaped; the gate pad is parallel to the strip area, and the left side of the gate pad is aligned with the left side of the square area.
3. A packaging structure of a semiconductor power device, characterized in that: It includes three MOS tubes, three large drain pads are formed in the middle of the bottom of the packaging structure, at most two gate pads are formed on the right side of the bottom of the packaging structure, at most two small drain pads connected to the large drain pads are formed on the right side of the bottom of the packaging structure, and the source pad and at least one gate pad of the MOS tube are formed on the left side of the packaging structure.
4. The semiconductor power device packaging structure according to claim 3, characterized in that: The three drain electrode pads are integrally formed in parallel, or the three source electrode pads are integrally formed in parallel.
5. A packaging structure of a semiconductor power device, characterized in that: It includes three MOS tubes, the gate, source and gate of the MOS tubes are distributed on both sides of the package structure, and three drain pads are formed in the middle of the bottom of the package structure; On one side of the package structure, six small pads are distributed in sequence, including a drain pad and / or a gate pad; on the other side of the package structure, six small pads are distributed in sequence, including a source pad and / or a gate pad.