Semiconductor power device packaging structure

Abstract

The utility model discloses a semiconductor power device packaging structure, which comprises a packaging body, a chip, a substrate and a plurality of pins, the chip, the substrate and the pins are packaged in the packaging body, the bottom of the substrate is exposed out of the packaging body, and at least one end of each pin extends out of the packaging body; the pins comprise a plurality of interconnection pins, the interconnection pins are electrically connected with a common electrode of the chip, an interconnection structure is arranged between the interconnection pins, and the bottom of the interconnection structure is exposed out of the packaging body. Due to the arrangement of the interconnection structure, the welding area of a pin welding area is increased, when large current passes through, the current density of the welding area is greatly reduced, the lower current density has more stable welding reliability, the packaging power density is improved, and the current capacity is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor power device packaging structure. Background Art

[0002] The packaging structure of electronic components mainly includes chips and pins arranged in the package body. The pins are used to lead out the internal circuit lead ends of the chip so as to connect the chip to external circuits or external devices through the pins.

[0003] With the development of computer, communication, automotive electronics, aerospace industry and other consumer system fields, the PCB area of ​​the application end is becoming more and more compact. The low integration of traditional packaging can no longer meet the current needs, so a more highly integrated packaging form is needed.

[0004] In the existing packaging structure, the area exposed at the bottom of the pin for welding is relatively small. When a large current passes through, the welding area has a high current density due to its small area. Long-term operation can easily reduce welding reliability and lead to instability. Utility Model Content

[0005] The purpose of the utility model is to provide a semiconductor power device packaging structure to solve the above-mentioned problems.

[0006] To achieve the above-mentioned object, the utility model provides a semiconductor power device packaging structure, comprising a packaging body, a chip, a substrate and a plurality of pins, wherein the chip, the substrate and the pins are packaged in the packaging body, the bottom of the substrate is exposed outside the packaging body, and at least one end of the pin extends outside the packaging body;

[0007] The pins include a plurality of interconnection pins, the interconnection pins are electrically connected to a common electrode of the chip, an interconnection structure is arranged between the interconnection pins, and the bottom of the interconnection structure is exposed outside the package body.

[0008] Preferably, the interconnect pin includes a lead-out portion and a chip connecting portion, the outer end of the lead-out portion extends outside the package body, the inner ends of the lead-out portion are electrically connected to each other through an interconnect structure, and the bottom of the lead-out portion is exposed outside the package body; the chip connecting portion is used to electrically connect to the chip.

[0009] Preferably, the chip connecting portion is formed by bending toward the inside of the package body to form a bent portion.

[0010] Preferably, the chip connecting portion is formed by etching a portion of the bottom of the interconnect pin.

[0011] Preferably, the chip connecting portion is electrically connected to the chip via a copper sheet.

[0012] Preferably, the chip connecting portion is integrally formed with the copper sheet.

[0013] Preferably, the copper sheet has a heat dissipation portion, one side of the heat dissipation portion is exposed outside the package body, and the other side of the heat dissipation portion is in contact with the chip surface.

[0014] Preferably, the chip connection portion is electrically connected to the chip by wire bonding.

[0015] Preferably, a tin creeping recessed area is formed at the exposed end of the pin.

[0016] Compared with the prior art, the utility model has the following beneficial effects:

[0017] (1) The setting of the interconnection structure increases the welding area of ​​the pin welding area. When a large current passes through, the current density of the welding area is greatly reduced. The lower current density has a more stable welding reliability, and also improves the power density of the package and the current capacity.

[0018] (2) A tin creeping depression area is opened on the outside of the pin, which has a higher side tin creeping effect and can also improve the AOI inspection of the device after soldering, thereby improving the board-level reliability of the device.

[0019] (3) The heat dissipation part of the copper sheet can be exposed outside the package body, which can achieve better heat dissipation capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 and Figure 2 A schematic structural diagram of a semiconductor power device packaging structure according to an embodiment of the utility model;

[0021] Figures 3 to 6 It is a side cross-sectional view of the semiconductor power device packaging structure according to an embodiment of the utility model.

[0022] In the figure: a package body 100 , a chip 200 , a substrate 300 , pins 400 , interconnection pins 410 , a lead-out portion 420 , a chip connection portion 430 , a solder creeping recessed area 440 , an interconnection structure 500 , a copper sheet 600 , and a heat dissipation portion 610 . DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0024] Figure 1 and Figure 2The schematic diagram of the structure of the semiconductor power device package structure of the present embodiment is shown, which includes a package body 100, a chip 200, a substrate 300 and a plurality of pins 400. The chip 200, the substrate 300 and the pins 400 are packaged in the package body 100, the bottom of the substrate 300 is exposed outside the package body 100, and at least one end of the pin 400 extends outside the package body 100;

[0025] The pins 400 include a plurality of interconnect pins 410, which are electrically connected to a common electrode of the chip 200. For example, the interconnect pins 410 are all electrically connected to the source of the chip 200. An interconnect structure 500 is provided between the interconnect pins 410, and the bottom of the interconnect structure 500 is exposed outside the package body 100. The provision of the interconnect structure 500 increases the welding area of ​​the welding region of the pins 400. When a large current passes through, the current density of the welding region is greatly reduced. A lower current density has a more stable welding reliability, and also improves the power density of the package and the current capacity.

[0026] like Figure 3 As shown, the interconnect pin 410 includes a lead-out portion 420 and a chip connection portion 430. The outer end of the lead-out portion 420 extends to the outside of the package body 100, the inner end of the lead-out portion 420 is electrically connected to each other through the interconnect structure 500, and the bottom of the lead-out portion 420 is exposed outside the package body 100; the chip connection portion 430 is used to electrically connect to the chip 200.

[0027] In a preferred embodiment, if Figure 3 As shown, the chip connection portion 430 is formed by bending toward the inside of the package body 100 to form a bent portion. In other embodiments, the chip connection portion 430 can also be formed by etching the bottom of a portion of the interconnect pin 410. The method of forming the chip connection portion 430 is a common technical means for those skilled in the art and will not be repeated here.

[0028] like Figure 3 As shown, the chip connection portion 430 is electrically connected to the chip 200 through the copper sheet 600. In other embodiments, the chip connection portion 430 can also be electrically connected to the chip 200 by wire bonding. Figure 4 As shown, the chip connection portion 430 and the copper sheet 600 are integrally formed, which can effectively improve the packaging performance.

[0029] In order to further improve the heat dissipation capacity, such as Figure 5 As shown, the thickness of the copper sheet 600 is increased so that the copper sheet 600 has a heat dissipation portion 610, one side of the heat dissipation portion 610 is exposed outside the package body 100, and the other side of the heat dissipation portion 610 is in contact with the surface of the chip 200. Figure 6As shown, when the chip connecting portion 430 and the copper sheet 600 are integrally formed, the copper sheet 600 may also have a heat dissipation portion 610 by increasing the thickness of the copper sheet 600 .

[0030] like Figure 1 and Figure 2 As shown, a tin creeping recessed area 440 is provided at the exposed end of the pin 400. The tin creeping recessed area 440 can make the pin 400 have a higher side tin creeping effect, and can also improve the AOI inspection of the device after welding, thereby improving the board-level reliability of the device.

[0031] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0032] In addition, it should be understood that although this specification is described based on implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A semiconductor power device packaging structure, characterized in that: The invention comprises a package body, a chip, a substrate and a plurality of pins, wherein the chip, the substrate and the pins are packaged in the package body, the bottom of the substrate is exposed outside the package body, and at least one end of the pins extends outside the package body; The pins include a plurality of interconnect pins, the interconnect pins are electrically connected to a common electrode of the chip, an interconnect structure is arranged between the interconnect pins, and the bottom of the interconnect structure is exposed outside the package body; The interconnect pin comprises a lead-out portion and a chip connection portion, the outer end of the lead-out portion extends outside the package body, the inner ends of the lead-out portion are electrically connected to each other through an interconnection structure, and the bottom of the lead-out portion is exposed outside the package body; the chip connection portion is used to electrically connect to the chip; The chip connection portion is electrically connected to the chip via a copper sheet; The copper sheet has a heat dissipation portion, one side of the heat dissipation portion is exposed outside the package body, and the other side of the heat dissipation portion is in contact with the chip surface.

2. The semiconductor power device packaging structure according to claim 1, characterized in that: The chip connection portion is formed by bending toward the inside of the package body to form a bent portion.

3. The semiconductor power device packaging structure according to claim 1, characterized in that: The chip connection portion is formed by etching a portion of the bottom of the interconnection pin.

4. The semiconductor power device packaging structure according to claim 1, characterized in that: The chip connecting portion is integrally formed with the copper sheet.

5. The semiconductor power device packaging structure according to claim 1, characterized in that: The chip connection portion is electrically connected to the chip by wire bonding.

6. The semiconductor power device packaging structure according to claim 1, characterized in that: A tin creeping recessed area is provided at the exposed end of the pin.

Images