Low-on-resistance planar gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

Abstract

The utility model provides a low-on-resistance planar gate silicon carbide VDMOS. The low-on-resistance planar gate silicon carbide VDMOS is characterized in that at least one metal filling structure layer is arranged in a silicon carbide substrate; the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate; the lower side of the current-sharing layer is connected to the upper side of the first drift layer; the lower side of the well region is connected to the upper side of the current-sharing layer; the lower side of the N-type source region is connected to the upper side of the well region, and the inner side of the N-type source region is connected to the well region; the lower side surface of the P-type source region is connected to the upper side surface of the well region; the inner side surface of the P-type source region is connected to the outer side surface of the N-type source region; the side surface of the second drift layer is connected to the inner side surface of the well region; the lower side surface of the gate dielectric layer is connected to the N-type source region, the well region and the second drift layer; the source metal layer is connected to the P-type source region and the N-type source region; the gate metal layer is connected to the gate dielectric layer; the drain electrode metal layer is connected with the silicon carbide substrate and each metal filling structure layer, high voltage resistance is achieved, and meanwhile the on-resistance of the device is reduced.

Description

Technical Field

[0001] The utility model relates to a low-on-resistance planar gate silicon carbide VDMOS. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, which is widely used in electric vehicles, aerospace, power conversion and other fields. The device has achieved good characteristics within 1200V, and has replaced silicon MOSFET and IGBT within 1200V. With the improvement of device withstand voltage and the reduction of on-resistance, achieving high reliability and low on-resistance under high withstand voltage conditions has become a new requirement for the development of device technology. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a low on-resistance planar gate silicon carbide VDMOS, which can achieve high withstand voltage and reduce the on-resistance of the device.

[0004] The utility model is implemented as follows: a low on-resistance planar gate silicon carbide VDMOS, comprising:

[0005] A silicon carbide substrate, wherein at least one metal filling structure layer is provided in the silicon carbide substrate;

[0006] A first drift layer, wherein a lower side of the first drift layer is connected to an upper side of the silicon carbide substrate;

[0007] A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the first drift layer;

[0008] A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer;

[0009] An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region, and the inner side of the N-type source region is connected to the well region;

[0010] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region, and the inner side of the P-type source region is connected to the outer side of the N-type source region;

[0011] A second drift layer, wherein a lower side of the second drift layer is connected to an upper side of the current balancing layer, and a side of the second drift layer is connected to an inner side of the well region;

[0012] A gate dielectric layer, the lower side of which is connected to the N-type source region, the well region and the second drift layer;

[0013] A source metal layer, the source metal layer connected to the P-type source region and the N-type source region;

[0014] a gate metal layer, the gate metal layer being connected to the gate dielectric layer;

[0015] and a drain metal layer, wherein the drain metal layer is respectively connected to the silicon carbide substrate and each metal filling structure layer.

[0016] Furthermore, the silicon carbide substrate, drift layer, and current balancing layer are all N-type; and the well region is P-type.

[0017] Furthermore, the thickness of the metal filling structure layer is four fifths of the thickness of the silicon carbide substrate.

[0018] Furthermore, the thickness of the flow balancing layer is 300 nm.

[0019] The advantages of the utility model are:

[0020] 1. The device adopts a longitudinal planar gate structure, and the device gate reliability is high;

[0021] Second, a current-balancing layer is constructed under the well region of the device, which can realize the lateral distribution of the current under the gate structure, thereby reducing the overall on-resistance of the device, while suppressing the internal heat concentration of the device caused by current concentration, making the heat distribution uniform;

[0022] 3. Construct a metal filling structure in the silicon carbide substrate layer of the device to reduce the contact resistance of the device substrate and thereby reduce the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0024] Figure 1 The utility model is a schematic diagram of a low on-resistance planar gate silicon carbide VDMOS.

[0025] Figure 2 The utility model is a flow chart of a method for preparing a low on-resistance planar gate silicon carbide VDMOS.

[0026] Figure 3 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 1 .

[0027] Figure 4 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 2 .

[0028] Figure 5 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 3 .

[0029] Figure 6This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 4 .

[0030] Figure 7 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 5 .

[0031] Figure 8 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 6 .

[0032] Fig. 9 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 7 .

[0033] Fig.10 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 8 .

[0034] Fig.11 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 9 .

[0035] Fig.12 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 10 .

[0036] Fig.13 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 10 one.

[0037] Fig.14 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 10 two. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] like Figure 1 As shown, the embodiment of the present application provides a low on-resistance planar gate silicon carbide VDMOS, including:

[0044] A silicon carbide substrate 101, wherein at least one metal filling structure layer 1011 is provided in the silicon carbide substrate 101;

[0045] A first drift layer 102, wherein a lower side of the first drift layer 102 is connected to an upper side of the silicon carbide substrate 101;

[0046] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the first drift layer 102;

[0047] A well region 104, wherein the lower side of the well region 104 is connected to the upper side of the current balancing layer 103;

[0048] An N-type source region 105 , wherein the lower side of the N-type source region 105 is connected to the upper side of the well region 104 , and the inner side of the N-type source region 105 is connected to the well region 104 ;

[0049] A P-type source region 106, wherein the lower side of the P-type source region 106 is connected to the upper side of the well region 104, and the inner side of the P-type source region 106 is connected to the outer side of the N-type source region 105;

[0050] A second drift layer 107, wherein the lower side of the second drift layer 107 is connected to the upper side of the current balancing layer 103, and the side of the second drift layer 107 is connected to the inner side of the well region 104;

[0051] A gate dielectric layer 108 , wherein the lower side of the gate dielectric layer 108 is connected to the N-type source region 105 , the well region 104 and the second drift layer 107 ;

[0052] A source metal layer 109 , the source metal layer 109 is connected to the P-type source region 106 and the N-type source region 105 ;

[0053] A gate metal layer 110 , wherein the gate metal layer 110 is connected to the gate dielectric layer 108 ;

[0054] And, a drain metal layer 111 , wherein the drain metal layer 111 is respectively connected to the silicon carbide substrate 101 and each metal filling structure layer 1011 .

[0055] like Figures 2 to 14 As shown, the method for preparing the above-mentioned silicon carbide VDMOS comprises the following steps:

[0056] Step 1: epitaxially growing a first drift layer 102 on a silicon carbide substrate 101;

[0057] Step 2, ion implantation is performed on the first drift layer 102 to form a current balancing layer 103 and a second drift layer 107, and the ion implantation energy is 330-430kev;

[0058] Step 3, forming a barrier layer a on the upper part of the second drift layer 107, etching the barrier layer a to form a through hole, and performing ion implantation on the second drift layer 107 to form a well region 104, wherein the ion implantation energy is 10-330kev;

[0059] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the well region 104 to form an N-type source region 105 with a thickness of 500 nm and an ion implantation energy of 10-170 keV;

[0060] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the well region 104 to form a P-type source region 106 with a thickness of 500 nm and an ion implantation energy of 10-170 keV;

[0061] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and deposit to form a gate dielectric layer 108, wherein the thickness of the gate dielectric layer 108 is 300 nm; the gate dielectric layer 108 may be silicon dioxide or other high-K dielectrics such as hafnium dioxide;

[0062] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 110;

[0063] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a source metal layer 109;

[0064] Step 9, remove the original barrier layer a, reform the barrier layer a, flip the device, reform the barrier region b on the silicon carbide substrate 101, etch the barrier region b to form a through hole, and etch the silicon carbide substrate 101 to a depth of 800 nm, deposit metal, and form a metal filling structure layer 1011; the thickness of the metal filling structure layer 1011 is four fifths of the thickness of the silicon carbide substrate 101;

[0065] Step 10: remove the barrier region b, deposit metal on the silicon carbide substrate 101 to form a drain metal layer 111, remove the barrier layer a, and complete the preparation.

[0066] The silicon carbide substrate 101, the drift layer 102, and the current balancing layer 103 are all N-type; the well region 104 is P-type, and the doping concentration of the silicon carbide substrate 101 is 5e18 cm -3 The doping concentration of the drift layer 102 is 2e17cm -3 The doping concentration of the current balancing layer 103 is 1e18 cm -3 The doping concentration of the P-type source region 106 is 4e19cm -3The doping concentration of the well region 104 is 5e17 cm -3 The doping concentration of the N-type source region 105 is 8e18cm -3 The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the metal filling structure layer 1011 is 800 nm, the thickness of the N-type drift layer 102 is 20-30 μm, the thickness of the P-type well region 104 is 1 μm, the thickness of the N-type source region 105 and the P-type source region 106 is 500 nm, the thickness of the gate dielectric layer 108 is 300 nm, the thickness of the N-type current balancing layer 103 is 300 nm, the thickness of the source metal layer 109 is 300 nm, and the device withstand voltage is 1200-3000 V; the concentration of the N-type silicon carbide substrate 101 is for A low-resistance ohmic contact is formed with the drain metal layer 111 to reduce the on-resistance of the device. The thickness is to ensure support during device epitaxy and improve process stability. The thickness of the metal filling structure layer 1011 is to reduce the contact resistance of the device N-type silicon carbide substrate 101 while ensuring that the contact characteristics with the device remain ohmic contact. Therefore, a 200nm N-type silicon carbide substrate 101 is separated from the N-type drift layer 102. The thickness and concentration of the N-type current balancing layer 103 are to ensure the realization of the internal current balancing effect while reducing the voltage resistance of the device. The doping concentration and thickness of the P-type well region 104 are designed to ensure the device's gate control capability for the P-type well region 104. The doping concentration of the N-type drift layer 102 is a compromise between the device's withstand voltage and on-resistance. The P-type source region 106 and the N-type source region 105 are designed to achieve ohmic contact with the source metal layer 109. The thickness of the gate dielectric layer 108 is a compromise between the device's gate control capability and gate reliability. An N-type current balancing layer 103 is constructed below the device's P-type well region 104. When the device is turned on, electrons flow from the N-type source region 105 through the gate below. The inverted p-well region 104 flows to the N-type drift layer 102 region directly below the gate, and flows toward the drain under the action of the positive voltage of the drain. When flowing through the N-type current balancing layer 103, due to the high doping concentration of the N-type current balancing layer 103, there is a low-resistance path in the horizontal direction compared to the vertical direction, and the electrons begin to flow horizontally to other regions inside the device, and then continue to flow downward, so that the electrons are redistributed laterally inside the device structure, and the current is more evenly distributed inside the device, thereby reducing the overall on-resistance of the device and suppressing the concentrated heat inside the device caused by current concentration.

[0067] During the device preparation process, the N-type silicon carbide substrate 101 needs to have a certain thickness to support various processes such as epitaxy on the top thereof. However, a large thickness of the N-type silicon carbide substrate 101 will increase the on-resistance of the device. The utility model constructs a metal filling structure layer 1011 in the N-type silicon carbide substrate 101 of the device to reduce the contact resistance of the silicon carbide substrate 101 of the device, thereby reducing the on-resistance of the device. If the thickness of the metal filling structure layer 1011 is controlled to be the same as that of the N-type silicon carbide substrate 101, the metal filling structure layer 1011 will form a Schottky contact with the N-type drift layer 102, thereby increasing the on-resistance of the device. Therefore, a 200nm thick N-type silicon carbide substrate 101 is maintained between the metal filling structure layer 1011 and the N-type drift layer 102 structure to achieve ohmic contact.

[0068] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A low on-resistance planar gate silicon carbide VDMOS, characterized in that: include: A silicon carbide substrate, wherein at least one metal filling structure layer is provided in the silicon carbide substrate; A first drift layer, wherein a lower side of the first drift layer is connected to an upper side of the silicon carbide substrate; A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the first drift layer; A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer; An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region, and the inner side of the N-type source region is connected to the well region; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region, and the inner side of the P-type source region is connected to the outer side of the N-type source region; A second drift layer, wherein a lower side of the second drift layer is connected to an upper side of the current balancing layer, and a side of the second drift layer is connected to an inner side of the well region; A gate dielectric layer, the lower side of which is connected to the N-type source region, the well region and the second drift layer; A source metal layer, the source metal layer connected to the P-type source region and the N-type source region; a gate metal layer, the gate metal layer being connected to the gate dielectric layer; and a drain metal layer, wherein the drain metal layer is respectively connected to the silicon carbide substrate and each metal filling structure layer.

2. A low on-resistance planar gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer and current balancing layer are all N-type; the well region is P-type.

3. A low on-resistance planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the metal filling structure layer is four fifths of the thickness of the silicon carbide substrate.

4. A low on-resistance planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the flow balancing layer is 300 nm.

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