Low-on-resistance trench gate super-junction silicon carbide VDMOS
By adopting a longitudinal trench gate superjunction structure and insulating layer design in silicon carbide VDMOS devices, the problem of difficulty in taking into account both voltage and on-resistance in the prior art is solved, and the effects of high voltage and low on-resistance are achieved.
Patent Information
- Application Number
- CN202421357918.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-14
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-06-14
AI Technical Summary
The existing silicon carbide VDMOS devices are difficult to effectively reduce the on-resistance while improving the voltage withstandability.
A longitudinal trench gate superjunction structure is adopted, including a silicon carbide substrate, a drift layer, a superjunction structure layer, an N-type source region, a P-type source region, a source metal layer, a gate dielectric layer, a gate metal layer and a drain metal layer, and the lateral voltage withstandness of the device is improved through the design of the insulating layer.
The combination of high voltage with low on-resistance is achieved. The gate corner of the device is protected by the design of the well region, the drift layer concentration is increased to reduce the on-resistance, and the voltage withstand structure of the device is enhanced by the design of the P-type source region.
Smart Images
Figure CN222692194U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a low on-resistance trench gate super-junction silicon carbide VDMOS. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The device has achieved good characteristics within 1200V, and has replaced Si MOSFET and IGBT within 1200V. With the improvement of device withstand voltage and the reduction of on-resistance, achieving both high withstand voltage and low on-resistance has become a new requirement for the development of device technology. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a low on-resistance trench gate super-junction silicon carbide VDMOS, which improves the withstand voltage capability and reduces the on-resistance.
[0004] The utility model is implemented as follows: a low on-resistance trench gate super-junction silicon carbide VDMOS, comprising:
[0005] Silicon carbide substrate,
[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a well region is provided on the drift layer;
[0007] A super junction structure layer, wherein the lower side of the super junction structure layer is connected to the upper side of the silicon carbide substrate, and the inner side of the super junction structure layer is connected to the outer side of the drift layer and the outer side of the well region;
[0008] An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region;
[0009] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the super junction structure layer, and the inner side of the P-type source region is connected to the N-type source region;
[0010] A source metal layer, the source metal layer is connected to the N-type source region and the P-type source region respectively;
[0011] A gate dielectric layer, wherein the bottom of the gate dielectric layer is connected to the upper side of the drift layer, and the outer side of the gate dielectric layer is connected to the inner side of the well region and the inner side of the N-type source region; a groove is provided on the gate dielectric layer;
[0012] A gate metal layer, wherein the gate metal layer is disposed in the groove;
[0013] and a drain metal layer connected to the lower side of the silicon carbide substrate.
[0014] Furthermore, it also includes an insulating layer, the lower side of the insulating layer is connected to the upper side of the silicon carbide substrate, and the inner side of the insulating layer is respectively connected to the outer side of the super junction structure layer and the outer side of the P-type source region.
[0015] Furthermore, the bottom thickness of the gate dielectric layer is 300 nm, and the side wall thickness is 100 nm.
[0016] Furthermore, the thickness of the N-type source region is equal to that of the P-type source region.
[0017] Furthermore, the drift layer has a thickness of 20-30 microns.
[0018] Furthermore, the super junction structure layer and the well region are both P-type, and the silicon carbide substrate and the drift layer are both N-type.
[0019] The advantages of the utility model are:
[0020] 1. The device adopts a vertical trench gate super junction structure, which has the characteristics of high withstand voltage and low on-resistance;
[0021] Second, the well region of the device not only realizes the function of controlling the conduction and shutdown of the device, but also realizes the protection of the dielectric layer at the corner of the device gate. This is because the bottom of the well region is flush with the bottom of the gate dielectric, which can realize the protection of the corner of the device gate;
[0022] 3. The insulating layer of the device can withstand lateral withstand voltage. The withstand voltage requirement of the super junction structure layer caused by increasing the concentration of the device drift layer is transferred to the insulating layer area, thereby increasing the concentration of the drift layer and reducing the on-resistance of the device;
[0023] Fourth, the P-type source region of the device completes the contact with the super junction structure layer while realizing the ohmic contact of the source region of the device, thereby realizing the voltage conduction of the super junction structure layer and forming the voltage-resistant structure of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0025] Figure 1 The utility model is a schematic diagram of a low on-resistance trench gate super-junction silicon carbide VDMOS.
[0026] Figure 2 The utility model is a flow chart of a method for preparing a low on-resistance trench gate super-junction silicon carbide VDMOS.
[0027] Figure 3 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 1 .
[0028] Figure 4This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 2 .
[0029] Figure 5 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 3 .
[0030] Figure 6 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 4 .
[0031] Figure 7 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 5 .
[0032] Figure 8 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 6 .
[0033] Fig. 9 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 7 .
[0034] Fig.10 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 8 .
[0035] Fig.11 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 9 .
[0036] Fig.12 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 10 .
[0037] Fig.13 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 10 one.
[0038] Fig.14 This is a cross-sectional view of the process of a low on-resistance trench gate superjunction silicon carbide VDMOS of the utility model. Figure 10 two. DETAILED DESCRIPTION
[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0044] like Figure 1 As shown, the embodiment of the present application provides a low on-resistance trench gate super junction silicon carbide VDMOS, including:
[0045] Silicon carbide substrate 101,
[0046] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a well region 1021 is provided on the drift layer 102;
[0047] A super junction structure layer 103, wherein the lower side of the super junction structure layer 103 is connected to the upper side of the silicon carbide substrate 101, and the inner side of the super junction structure layer 103 is connected to the outer side of the drift layer 102 and the outer side of the well region 1021;
[0048] An N-type source region 104, wherein the lower side of the N-type source region 104 is connected to the upper side of the well region 1021;
[0049] A P-type source region 105 , wherein the lower side of the P-type source region 105 is connected to the upper side of the super junction structure layer 103 , and the inner side of the P-type source region 105 is connected to the N-type source region 104 ;
[0050] A source metal layer 106 , wherein the source metal layer 106 is connected to the N-type source region 104 and the P-type source region 105 ;
[0051] A gate dielectric layer 107, wherein the bottom of the gate dielectric layer 107 is connected to the upper side of the drift layer 102, and the outer side of the gate dielectric layer 107 is connected to the inner side of the well region 1021 and the inner side of the N-type source region 104; a groove 1071 is provided on the gate dielectric layer 107;
[0052] The insulating layer 108 has a lower side connected to the upper side of the silicon carbide substrate 101, and an inner side of the insulating layer 108 is respectively connected to the outer side of the super junction structure layer 103 and the outer side of the P-type source region 105.
[0053] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1071;
[0054] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .
[0055] like Figures 2 to 14 As shown, the method for preparing the above silicon carbide VDMOS comprises the following steps:
[0056] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102;
[0057] Step a, forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, and etching the drift layer 102 to the top of the silicon carbide substrate 101, and depositing to form an insulating layer 108;
[0058] Step 2, removing the barrier layer a, and re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer to form a super junction structure layer, the ion implantation energy is 200-7000 to 10000kev, corresponding to a drift layer thickness of 20-30μm;
[0059] Step 3, removing the barrier layer a, and re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 102 to form a well region 1021 with a thickness of 300 nm and an ion implantation energy of 500-600 kev;
[0060] Step 4: remove the barrier layer a, and re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation on the drift layer 102 to form a P-type source region 105 with a thickness of 600 nm and an ion implantation energy of 300-500 kev;
[0061] Step 5, removing the barrier layer a, and re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 102 to form an N-type source region 104 with a thickness of 600 nm and an ion implantation energy of 300-500 kev;
[0062] Step 6, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, the drift layer 102 and the well region 1021 to form a through hole, and then perform dry oxygen oxidation to form a gate dielectric layer 107, the bottom of the gate dielectric layer 107 is connected to the upper side of the drift layer 102, and a groove 1071 is provided in the gate dielectric layer 107; the barrier layer a, the drift layer 102 and the well region 1021 can be etched by wet chemical solution, the chemical solution is a mixture of sulfuric acid and hydrogen peroxide, first configure the ratio of sulfuric acid and water to form a sulfuric acid solution, the ratio is 1:2; then configure the concentration of hydrogen peroxide, the concentration of hydrogen peroxide is 45%, and finally the sulfuric acid solution and hydrogen peroxide are mixed to form a chemical solution, the ratio of sulfuric acid solution to hydrogen peroxide is 3:2; dry etching or plasma etching can also be used;
[0063] Step 7, removing the barrier layer a, and re-forming the barrier layer a, etching the barrier layer a to form a through hole, and depositing metal to form a gate metal layer 109;
[0064] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 102 to a depth of 300nm, perform metal deposition to form a source metal layer 106, remove the barrier layer a, and complete the preparation.
[0065] The super junction structure layer 103 and the well region 1021 are both P-type, the silicon carbide substrate 101 and the drift layer 102 are both N-type, and the doping concentration of the silicon carbide substrate 101 is 5e18cm -3 The doping concentration of the drift layer 102 is 2e17cm -3 The doping concentration of the super junction structure layer 103 is 1e18cm -3 The doping concentration of the P-type source region 105 is 4e19cm -3 The doping concentration of the P-type well region 1021 is 5e17 cm -3 The doping concentration of the N-type source region 104 is 8e18cm -3 The doping concentration of the N-type drift layer structure of the traditional superjunction structure is 1e16cm -3 -5e16cm -3 Within the concentration range, the on-resistance of the device is mainly affected by the resistance of the drift layer. The device structure can effectively increase the doping concentration of the drift region, thereby reducing the on-resistance of the device; the P-type well region 1021 of the device completes the inversion control of the device gate metal layer 109 and then controls the on and off of the device freewheeling channel to realize the on-off control of the device. Its bottom is flush with the bottom of the gate dielectric layer 107 of the device, which can effectively suppress the reliability problems caused by the electric field concentration at the corners of the gate dielectric layer 107 of the device, thereby improving the reliability of the device gate.
[0066] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the N-type drift layer 102 is 20-30 μm, the thickness of the P-type well region 1021 is 600 nm, the thickness of the N-type source region 104 and the P-type source region 105 are 600 nm, the bottom thickness of the gate dielectric layer 107 is 300 nm, the side wall thickness is 100 nm, the thickness from the top of the source metal layer 106 to the top of the N-type source region 104 is 300 nm, the device withstand voltage is 1200-3000 V, the doping concentration and thickness of the P-type well region 1021 are designed to increase the gate control capability of the device to the P-type well region 1021 while taking into account the inhibitory effect of the device P-type well region 1021 on the electric field concentration at the corner of the gate dielectric layer 107, the doping concentration of the N-type drift layer 102 is to take into account the compromise between the withstand voltage and the on-resistance of the device, and the P-type source region 105 is to realize the parasitic body diode of the device. The tube is in low-resistance contact with the P-type super junction structure layer 103 to ensure the realization of the device super junction structure. The device insulating layer 108 is used to increase the doping concentration of the device drift region without reducing the device withstand voltage, that is, to reduce the device on-resistance on the basis of realizing the super junction structure. When the device drain is subjected to a large voltage, the pn junction formed by the P-type super junction structure layer 103 and the N-type drift layer 102 is subjected to the voltage. As the voltage increases, the space charge region diffuses from bottom to top while the electric field diffuses to the edge of the device. However, when the outermost layer is the insulating layer, the dielectric constant is large, which can effectively improve the equivalent dielectric constant of the device in the lateral direction and reduce the influence of excessive ionized impurities on the withstand voltage. At the same time, the critical breakdown field strength of silicon dioxide is greater than that of silicon carbide, and it can effectively withstand a large electric field at the bottom of the device; and the insulating layer area of the device provides a slicing track for the device while ensuring the improvement of the device characteristics to achieve functional integration.
[0067] When the device is turned off, the device drain is subjected to high voltage, and the device drain voltage extends to the N-type drift layer 102. Since the P-type super junction structure layer 103 contacts the N-type drift layer 102 from the N-type silicon carbide substrate 101, the potential is borne by the pn junction between the P-type super junction structure layer 103 and the N-type drift layer 102 from bottom to top, and the vertical withstand voltage structure is transformed into a combination of vertical and horizontal to achieve super junction capability. When the device gate is turned on by a positive voltage, the P-type well region 1021 is inverted to n-type, forming a conductive channel of source metal layer 106-N-type source region 104-P-type well region 1021-N-type drift layer 102-N-type silicon carbide substrate 101-drain metal layer 110.
[0068] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A low on-resistance trench gate superjunction silicon carbide VDMOS, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a well region is provided on the drift layer; A super junction structure layer, wherein the lower side of the super junction structure layer is connected to the upper side of the silicon carbide substrate, and the inner side of the super junction structure layer is connected to the outer side of the drift layer and the outer side of the well region; An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the super junction structure layer, and the inner side of the P-type source region is connected to the N-type source region; A source metal layer, the source metal layer is connected to the N-type source region and the P-type source region respectively; A gate dielectric layer, wherein the bottom of the gate dielectric layer is connected to the upper side of the drift layer, and the outer side of the gate dielectric layer is connected to the inner side of the well region and the inner side of the N-type source region; A groove is provided on the gate dielectric layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer connected to the lower side of the silicon carbide substrate.
2. A low on-resistance trench gate superjunction silicon carbide VDMOS according to claim 1, characterized in that: It also includes an insulating layer, the lower side of the insulating layer is connected to the upper side of the silicon carbide substrate, and the inner side of the insulating layer is respectively connected to the outer side of the super junction structure layer and the outer side of the P-type source region.
3. The low on-resistance trench gate superjunction silicon carbide VDMOS according to claim 1, characterized in that: The bottom thickness of the gate dielectric layer is 300 nm, and the side wall thickness is 100 nm.
4. The low on-resistance trench gate superjunction silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the N-type source region is equal to that of the P-type source region.
5. The low on-resistance trench gate superjunction silicon carbide VDMOS according to claim 1, characterized in that: The drift layer has a thickness of 20-30 microns.
6. The low on-resistance trench gate superjunction silicon carbide VDMOS according to claim 1, characterized in that: The super junction structure layer and the well region are both P-type, and the silicon carbide substrate and the drift layer are both N-type.