A logic AND gate relay driving circuit for signal processing
By designing flyback and forward PWM signal generation circuits, the problems of frequent operation of the prior art relays, high transformer size and cost, narrow input voltage range, and computer platform calculation occupation are solved, and stable output and low-cost design within a wide voltage input range are realized.
Patent Information
- Application Number
- CN202421248051.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-03
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-06-03
AI Technical Summary
The prior art has problems such as frequent operation, high transformer size, high cost and narrow input voltage range when driving relays, and requires occupancy of the computing volume of the computer platform.
A logic AND gate relay driving circuit is designed, using flyback PWM signal generation circuit and forward PWM signal generation circuit. By collecting the output voltages of the flyback power circuit and forward power circuit, a PWM signal that maintains output stability is generated, reducing dependence on the computer platform, and maintaining stable output within a wide voltage input range.
It realizes maintaining stable output within a wide voltage input range, reducing the transformer size and cost, avoiding frequent relay operations, and reducing the computing usage of computer platforms.
Smart Images
Figure CN222706486U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic power technology, and in particular to a logic AND gate relay driving circuit for signal processing. Background Art
[0002] In the fields of subway, light rail, high-speed rail, etc., in order to meet the requirements of functional safety, two-out-of-two control systems are often used to achieve SIL4 safety level. Such control systems generally contain a "logic AND gate" circuit structure, and its load is usually a relay. The safety computer platform in the system will output two dynamic pulse signals to the logic AND gate circuit. The logic AND gate circuit drives the relay by outputting a stable voltage through the "AND" operation of these two signals. The failure of any dynamic pulse signal indicates that the system is abnormal, and the output voltage of the "logic AND gate" circuit is zero to ensure the safety of the relay.
[0003] In the related art, the logic AND gate circuit is composed of two cascaded forward circuits, and two pulse width modulation signals (Pulse Width Modulation, hereinafter referred to as PWM signals) are often used to drive the two forward circuits to work. There are generally two series connection schemes for this type of circuit:
[0004] (1) The output voltage of the first-stage forward-pulse circuit serves as the power supply for the optocoupler isolation device of the second-stage circuit, and the output voltage of the second-stage circuit can drive the relay. When the logic AND gate circuit is working, due to the fluctuation of the input voltage, the output voltage of the output end of the forward-pulse circuit also fluctuates. Since the output end of the first-stage circuit is connected to the optocoupler isolation device of the second-stage circuit, the power is small and the fluctuation of the output voltage is acceptable. However, the output end of the second-stage circuit is connected to the relay. The output power of the second-stage circuit is 4-8 times that of the first-stage circuit, and the load is relatively large. Therefore, the output voltage of the second-stage circuit fluctuates greatly. The greatly fluctuating voltage will cause the relay to operate frequently, affecting the safety of the circuit.
[0005] (2) The output voltage of the first-stage forward-pulse circuit is used as the power supply of the second-stage forward-pulse circuit. Since the first-stage circuit plays a role of pre-stabilization, the output voltage of the second-stage circuit is relatively stable, overcoming the disadvantage of large output voltage fluctuations, and can drive the relay load well. The energy required by the load of this scheme requires two transformers to be cascaded and converted twice, and the required first-stage forward-pulse transformer is large, occupies a large area, and has high cost.
[0006] Both of the above solutions have the problem of narrow input voltage range adaptability, and generally can only meet the 22v-32v input requirements. In some systems with input voltage range of 18v-36v, they are not applicable. Moreover, during use, the input voltage may fluctuate within the range of 22v-32v, and the PWM signal is issued by the logic part of the safety computer platform in the system, so the safety computer platform needs to modulate the duty cycle of the two PWM signals, which occupies a part of the calculation amount of the safety computer platform. Utility Model Content
[0007] Based on this, in response to the above technical problems, a logic AND gate relay driving circuit for signal processing is provided to solve the problems that the prior art cannot simultaneously meet the requirements, resulting in frequent relay action, the transformer is large, occupies a large area, and has high cost, and the voltage input range applicable to the prior art is narrow, and requires a lot of calculations on the computer platform.
[0008] A logic AND gate relay driving circuit for signal processing, comprising: a first-level circuit and a second-level circuit;
[0009] The first stage circuit includes a first coupler IC1 and a flyback regulated power supply circuit; the second stage circuit includes a second optical coupling driver IC11 and a forward regulated power supply circuit; the anode of the light emitting diode in the first coupler IC1 is the input end of the first square wave signal; the anode of the light emitting diode in the second optical coupling driver IC11 is the input end of the second square wave signal;
[0010] The flyback voltage-stabilized power supply circuit comprises a flyback PWM signal generating circuit and a flyback power circuit, wherein the flyback PWM signal generating circuit comprises a three-terminal voltage regulator VT1, a transistor Q1, an optocoupler IC2, a voltage regulator Z1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, and a capacitor C2; the input end of the three-terminal voltage regulator VT1 is a power input end, the output end of the three-terminal voltage regulator VT1 is connected to the collector of the transistor Q1, and a first node is set on the connection line between the output end of the three-terminal voltage regulator VT1 and the collector of the transistor Q1, A first branch is led out from the first node to connect one end of a resistor R1, and the other end of the resistor R1 is connected to the base of the transistor Q1; the base of the transistor Q1 is connected to the collector of the phototransistor in the first coupler IC1; the emitter of the transistor Q1 is connected to one end of a resistor R2, and the other end of the resistor R2 is connected to the emitter of the phototransistor in the first coupler IC1; a second branch is led out from the connection point between the other end of the resistor R1 and the base of the transistor Q1, and the second branch is connected to one end of the capacitor C1. The other end of C1 is connected to the other end of the resistor R2 and the emitter connection line of the phototransistor in the first coupler IC1 and then grounded; one end of the resistor R3 is connected to the flyback power circuit, and the other end of the resistor R3 is connected to the other end of the resistor R2. A second node is set on the connection line between the emitter of the transistor Q1 and one end of the resistor R2, and a third branch is drawn from the second node to connect one end of the capacitor C2. The other end of the capacitor C2 is connected to the connection line between one end of the resistor R3 and the flyback power circuit. A third node is set on the line connected to the flyback power circuit, a fourth branch is drawn from the third node to connect the collector of the phototransistor in the optocoupler IC2, and the emitter of the phototransistor in the optocoupler IC2 is connected to the other end of the resistor R3; the anode of the photosensitive diode in the optocoupler IC2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the output power supply end of the flyback power circuit; the cathode of the photosensitive diode in the optocoupler IC2 is connected to one end of the voltage regulator Z1, and the other end of the voltage regulator Z1 is connected to the other end of the resistor R3 and then grounded;
[0011] The forward voltage-stabilized power supply circuit comprises a forward PWM signal generating circuit, a forward power circuit and a front-stage voltage-stabilizing circuit; the forward PWM signal generating circuit comprises a transistor Q11, a transistor Q12, an optical coupler IC12, a diode D10, a voltage-stabilizing diode D13, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C11, and a capacitor C12; the output power supply end of the flyback power circuit is respectively connected to the collector of the transistor Q11 and the driving side input end of the second optical coupling driver IC11; the base of the transistor Q11 is connected in series with the capacitor C11, the resistor R11 in sequence; The emitter of the transistor Q11 is connected to the emitter of the transistor Q12, the base of the transistor Q12 is connected to the anode of the diode D10, the cathode of the diode D10 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is connected to the emitter of the photosensitive transistor in the optical coupler IC12; a fourth node is set on the connecting line between the cathode of the diode D10 and one end of the capacitor C12 to lead out a fifth branch, the fifth branch is connected to one end of the resistor R13, and the resistor R13 The other end is connected to the capacitor C12 and the emitter connection line of the photosensitive transistor in the optocoupler IC12, a fifth node is set on the capacitor C12 and the emitter connection line of the photosensitive transistor in the optocoupler IC12 to lead out a sixth branch, and the sixth branch is grounded; a sixth node is set on the connection line between the capacitor C11 and the base of the transistor Q11 to lead out a seventh branch, and the seventh branch is connected to the base of the transistor Q12 and the anode connection line of the diode D10; a seventh node is set on the connection line between the resistor R11 and the capacitor C11 to lead out an eighth branch, and the eighth branch is connected to the optocoupler I The collector of the phototransistor in C12; an eighth node is set on the connecting line between the emitter of the transistor Q11 and the emitter of the transistor Q12 to lead out a ninth branch, and the ninth branch is connected to the resistor R14 and then connected to the forward power circuit; the anode of the diode in the optocoupler IC12 is connected to the resistor R12 and the voltage regulator diode D13 in sequence and then connected to the load positive output port of the forward power circuit; the cathode of the diode in the optocoupler IC12 is the load negative output port; the input port of the front-stage voltage regulator circuit is the power input terminal, and the output terminal of the front-stage voltage regulator circuit is connected to the forward power circuit.
[0012] In the above scheme, optionally, the flyback power circuit includes: a transformer T1, a MOS tube Q2, a rectifier tube D1 and a capacitor C3; one end of the primary winding of the transformer T1 is the input power supply end, the other end of the primary winding of the transformer T1 is connected to the drain of the MOS tube Q2, and the source of the MOS tube Q2 is connected to the resistor R3; one end of the secondary winding of the transformer T1 is connected to one end of the rectifier tube D1, the other end of the rectifier tube D1 is connected to the output power supply end, and the other end of the secondary winding of the transformer T1 is connected to the gate of the MOS tube Q2; a ninth node is set on the connecting line between the other end of the rectifier tube D1 and the output power supply end to lead out a tenth branch, the tenth branch is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the gate of the MOS tube Q2.
[0013] In the above solution, optionally, the forward power circuit includes: a transformer T11, a MOS tube Q13, a rectifier tube D11, a rectifier tube D12 and a capacitor C13;
[0014] One end of the first primary coil of the transformer T11 is connected to the output end of the front-stage voltage stabilizing circuit, and the other end of the first primary coil of the transformer T11 is connected to the drain of the MOS tube Q13; a connection line between one end of the first primary coil of the transformer T11 and the output end of the front-stage voltage stabilizing circuit is provided with a tenth node to lead out an eleventh branch, the eleventh branch is connected to one end of the rectifier tube D11, and the other end of the rectifier tube D11 is connected to one end of the second primary coil of the transformer T11; the other end of the second primary coil of the transformer T11 is connected to the source of the MOS tube Q13; the gate of the MOS tube Q13 is connected to the resistor R14;
[0015] One end of the secondary coil of the transformer T11 is connected to one end of the rectifier D12, and the other end of the rectifier D12 is connected to the positive output port of the load; an eleventh node is set on the connection line between the other end of the rectifier D12 and the positive output port of the load to lead out a twelfth branch, the twelfth branch is connected to one end of the capacitor C13, and the other end of the capacitor C13 is connected to the other end of the secondary coil of the transformer T11; a twelfth node is set on the connection line between the other end of the capacitor C13 and the other end of the secondary coil of the transformer T11 to lead out a thirteenth branch, and the thirteenth branch is connected to the negative output port of the load.
[0016] In the above scheme, further optionally, the pre-stage voltage stabilization circuit includes: a pre-stage voltage regulator VT11, the input end of the pre-stage voltage regulator VT11 is the power input end, and the output end of the pre-stage voltage regulator VT11 is connected to one end of the primary coil of the transformer T11 in the forward power circuit.
[0017] In the above solution, optionally, the model of the three-terminal regulator VT1 is LM7812 or LM7815.
[0018] This application has at least the following beneficial effects:
[0019] The present application uses the flyback PWM signal generation circuit to use the input voltage as the power supply, uses the fixed frequency of the cpu1 square wave signal as its own fixed frequency, collects the output voltage of the flyback power circuit, and generates a PWM signal with a duty cycle required to maintain output stability; at the same time, the forward PWM signal generation circuit uses the fixed frequency of the cpu2 square wave signal as its own fixed frequency, collects the output voltage of the forward power circuit, and generates a PWM signal with a duty cycle required to maintain output stability. As a result, there is no need to occupy the computing power of the computer platform to regulate the two PWM signals. Moreover, the first-stage circuit can generate a stable voltage V1 output under the full range of the input power supply, and provide power to the output side of the second optocoupler driver in the second stage and the forward PWM signal generation circuit, thereby maintaining a stable output within a wide voltage input range; the first-stage power output device adopts a flyback power supply topology, with a small power load, and does not require a large transformer, reducing costs and PCB area. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A circuit diagram of a logic AND gate relay driving circuit for signal processing is provided for one embodiment of the present application.
[0021] Figure 2 A principle block diagram of a logic AND gate relay driving circuit for signal processing is provided for one embodiment of the present application;
[0022] Figure 3 A specific circuit diagram of a first-level circuit provided in one embodiment of the present application;
[0023] Figure 4 A specific circuit diagram of a second-level circuit provided for one embodiment of the present application;
[0024] Figure 5 A specific circuit schematic diagram of a buck circuit, a boost circuit or a buck-boost circuit provided in one embodiment of the present application. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0026] In one embodiment, Figure 1As shown, a logic AND gate relay driving circuit for signal processing is provided, comprising: a first-stage circuit and a second-stage circuit;
[0027] The first stage circuit includes a first coupler IC1 and a flyback regulated power supply circuit; the second stage circuit includes a second optical coupling driver IC11 and a forward regulated power supply circuit; the anode of the light emitting diode in the first coupler IC1 is the input end of the first square wave signal; the anode of the light emitting diode in the second optical coupling driver IC11 is the input end of the second square wave signal;
[0028] Specifically, Figure 2 As shown, the input end of the first coupler IC1 in the first stage circuit is the input end of the first square wave signal, and the output end of the first coupler IC1 is connected to the flyback voltage-stabilized power supply circuit, which includes a flyback PWM signal generating circuit and a flyback power circuit, and the output end of the flyback PWM signal generating circuit is connected to the flyback power circuit, and the power input provides power for both the flyback PWM signal generating circuit and the flyback power circuit. The input end of the second optical coupling driver IC11 in the second stage circuit is the input end of the second square wave signal, and the output end of the second optical coupling driver IC11 is connected to the forward voltage-stabilized power supply circuit, which includes a forward PWM signal generating circuit and a forward power circuit and a front-stage voltage-stabilizing circuit, and the output end of the forward PWM signal generating circuit is connected to the forward power circuit, and the power input provides power for the front-stage voltage-stabilizing circuit, and the front-stage voltage-stabilizing circuit provides power and is connected to the forward power circuit; the flyback power circuit in the first stage circuit provides input power for the second optical coupling driver IC11 and the forward PWM signal generating circuit.
[0029] like Figure 1 and Figure 3As shown, the flyback voltage-stabilized power supply circuit includes a flyback PWM signal generating circuit and a flyback power circuit, and the flyback PWM signal generating circuit includes a three-terminal voltage regulator VT1, a transistor Q1, an optocoupler IC2, a voltage regulator Z1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, and a capacitor C2; the input end of the three-terminal voltage regulator VT1 is a power input end, the output end of the three-terminal voltage regulator VT1 is connected to the collector of the transistor Q1, and a first junction is set on the output end of the three-terminal voltage regulator VT1 and the collector connection line of the transistor Q1 A first branch is led out from the first node to connect one end of a resistor R1, and the other end of the resistor R1 is connected to the base of the transistor Q1; the base of the transistor Q1 is connected to the collector of the phototransistor in the first coupler IC1; the emitter of the transistor Q1 is connected to one end of a resistor R2, and the other end of the resistor R2 is connected to the emitter of the phototransistor in the first coupler IC1, and a second branch is led out from the connection point between the other end of the resistor R1 and the base of the transistor Q1, and the second branch is connected to one end of the capacitor C1, and the The other end of the capacitor C1 is connected to the other end of the resistor R2 and the emitter connection line of the phototransistor in the first coupler IC1 and then grounded; one end of the resistor R3 is connected to the flyback power circuit, the other end of the resistor R3 is connected to the other end of the resistor R2, a second node is set on the connection line between the emitter of the transistor Q1 and one end of the resistor R2, a third branch is drawn from the second node to connect one end of the capacitor C2, the other end of the capacitor C2 is connected to the connection line between one end of the resistor R3 and the flyback power circuit, and a third branch is drawn from the second node to connect one end of the capacitor C2. A third node is set on the connecting line between the end and the flyback power circuit, a fourth branch is led out from the third node to connect the collector of the phototransistor in the optocoupler IC2, and the emitter of the phototransistor in the optocoupler IC2 is connected to the other end of the resistor R3; the anode of the photosensitive diode in the optocoupler IC2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the output power supply end of the flyback power circuit; the cathode of the photosensitive diode in the optocoupler IC2 is connected to one end of the voltage regulator Z1, and the other end of the voltage regulator Z1 is connected to the other end of the resistor R3 and then grounded.
[0030] Specifically, in the flyback PWM signal generation circuit, the input power is used as the input of the three-terminal voltage regulator VT1, and the output of VT1 is connected to one end of the resistor R1 and the collector of the NPN transistor Q1. One end of the resistor R1 is connected to the base of the NPN transistor Q1, one end of the capacitor C1, and the collector of the phototransistor of IC1. The emitter of the NPN transistor Q1 is connected to one end of the capacitor C2 and one end of the resistor R2. The other end of C2 is connected to the collector of the phototransistor in the optocoupler IC2, one end of the resistor R3, and the gate of the MOS tube Q2. The cathode of the photosensitive diode in the optocoupler IC2 is connected to the cathode of the voltage regulator tube Z1. The anode of the photosensitive diode in the optocoupler IC2 is connected to one end of the resistor R4. One end of the resistor R4 is connected to the output V1 of the flyback voltage regulator power supply circuit. The transformer T1, the MOS tube Q2, the rectifier tube D1 and the capacitor C3 form a typical flyback power topology circuit. The ground of the three-terminal regulator VT1, the emitter of the phototransistor of IC1, the other end of C1, the other end of R2, the other end of R3, the other end of Z1, and the emitter of the phototransistor of IC2 are connected to the ground of the flyback power topology circuit.
[0031] Since the input voltage fluctuation range is relatively wide, Figure 3 VT1 is a three-terminal voltage regulator (including but not limited to LM7812, LM7815, etc.) that converts the input fluctuating voltage into a stable voltage. This voltage is provided to the signal generation circuit composed of resistor R1, resistor R2, resistor R3, capacitor C1, capacitor C2, transistor Q1, and optocoupler IC1. The fixed frequency cpu1 square wave pulse signal emitted by the secure computer platform passes through the light-emitting diode of the optocoupler IC1, causing the phototransistor of IC1 to turn on and off at the same frequency. When the phototransistor of IC1 is turned off, the capacitor C1 is charged through the resistor R1, and when the phototransistor of IC1 is turned on, the capacitor C1 is discharged. Since the capacitor C1 has a charging and discharging process, a high and low level signal is synchronously formed at the emitter of the NPN transistor Q1. This high and low level signal is used as the driving signal of the switch tube Q2 in the flyback power circuit through the DC isolation circuit composed of capacitor C2 and resistor R3.
[0032] The output V1 of the flyback power circuit controls the light intensity of IC2's light-emitting diode through resistor R4 and voltage regulator Z1, thereby affecting the magnitude of the current flowing through IC2's phototransistor. The magnitude of the current flowing through IC2's phototransistor determines the time that the drive signal generated by NPN transistor Q1 is higher than the gate threshold voltage of MOS tube Q2. When the voltage of V1 is high, IC2's light-emitting diode emits strong light, the current flowing through IC2's phototransistor is large, and the time that the drive signal is higher than the gate threshold voltage of MOS tube Q2 is short. When the voltage of V1 is low, IC2's light-emitting diode emits weak light, the current flowing through IC2's phototransistor is small, and the time that the drive signal is higher than the gate threshold voltage of MOS tube Q2 is long. Thus, the modulation of the flyback PWM signal is completed. The flyback power circuit uses the input voltage as the power supply and generates a stable voltage output under the control of the flyback PWM signal.
[0033] Since the transformer in the flyback power circuit must be under alternating voltage to transfer energy from the primary winding to the secondary winding, if the cpu1 square wave signal disappears, the flyback PWM signal disappears, the switch tube in the flyback power circuit does not work, and cannot generate alternating voltage to the primary winding of the transformer, so the secondary winding of the transformer will not couple out energy, and the flyback power circuit has no output.
[0034] like Figure 1 and Figure 4As shown, the forward voltage-stabilized power supply circuit includes a forward PWM signal generating circuit, a forward power circuit and a pre-stage voltage-stabilizing circuit; the forward PWM signal generating circuit includes a transistor Q11, a transistor Q12, an optical coupler IC12, a diode D10, a voltage-stabilizing diode D13, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C11, and a capacitor C12; the output power supply end of the flyback power circuit is respectively connected to the collector of the transistor Q11 and the driving side input end of the second optical coupling driver IC11; the base of the transistor Q11 is sequentially connected to the capacitor C11, the resistor R1 1 are connected in series with the driving side output end of the second optical coupling driver IC11; the emitter of the transistor Q11 is connected to the emitter of the transistor Q12, the base of the transistor Q12 is connected to the anode of the diode D10, the cathode of the diode D10 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is connected to the emitter of the photosensitive transistor in the optical coupler IC12; a fourth node is set on the connecting line between the cathode of the diode D10 and one end of the capacitor C12 to lead out a fifth branch, the fifth branch is connected to one end of the resistor R13, and the resistor R The other end of 13 is connected to the capacitor C12 and the emitter connection line of the photosensitive transistor in the optocoupler IC12, and a fifth node is set on the capacitor C12 and the emitter connection line of the photosensitive transistor in the optocoupler IC12 to lead out a sixth branch, and the sixth branch is grounded; a sixth node is set on the connection line between the capacitor C11 and the base of the transistor Q11 to lead out a seventh branch, and the seventh branch is connected to the base of the transistor Q12 and the anode connection line of the diode D10; a seventh node is set on the connection line between the resistor R11 and the capacitor C11 to lead out an eighth branch, and the eighth branch is connected to the optocoupler The collector of the phototransistor in IC12; an eighth node is set on the connecting line between the emitter of the transistor Q11 and the emitter of the transistor Q12 to lead out a ninth branch, and the ninth branch is connected to the resistor R14 and then connected to the forward power circuit; the anode of the diode in the optocoupler IC12 is connected to the resistor R12 and the voltage stabilizing diode D13 in sequence and then connected to the load positive output port of the forward power circuit; the cathode of the diode in the optocoupler IC12 is the load negative output port; the input port of the front-stage voltage stabilizing circuit is the power input terminal, and the output terminal of the front-stage voltage stabilizing circuit is connected to the forward power circuit.
[0035] Specifically, the second stage circuit includes a second optical coupling driver IC11 and a forward voltage stabilizing power supply circuit. The forward voltage stabilizing power supply circuit contains a forward PWM signal generating circuit, a pre-stage voltage stabilizing circuit and a forward power circuit. The light emitting diode input end of IC11 is used to receive the cpu2 square wave signal, and the output end of IC11 is connected to the signal input end of the forward voltage stabilizing power supply circuit.
[0036] In the forward PWM signal generation circuit, the first-stage output V1 is used as the power supply, and V1 is connected to the driving side input end of the second optical coupling driver IC11 and the collector of the NPN transistor Q11. The driving side output end of the optical coupling driver IC11 is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to one end of the capacitor C11 and the collector of the photosensitive transistor of IC12. The other end of the capacitor C11 is connected to the base of the NPN transistor Q11, the base of the PNP transistor Q12, and the anode of the diode D10. The cathode of the diode D10 is connected to one end of the capacitor C12 and one end of the resistor R13. The emitter of the NPN transistor Q11 is connected to the emitter of the PNP transistor Q12 and one end of the resistor R14. The input voltage supplies power to the front-stage voltage stabilization circuit, and the output of the front-stage voltage stabilization circuit supplies power to the forward power circuit. Transformer T11, MOS tube Q13, rectifier tube D11, rectifier tube D12 and capacitor C13 form a typical forward power circuit. The ground of the driving side of the optical coupling driver IC11, the other end of the capacitor C12, the other end of the resistor R13, the collector of the PNP transistor Q12, the emitter of the phototransistor of IC12, the ground of the pre-stage regulator, and the ground of the forward power circuit are connected.
[0037] The cathode of the photosensitive diode in the optocoupler IC12 is connected to the negative output Vo- of the second stage, and the anode of the photosensitive diode in the optocoupler IC12 is connected to one end of the resistor R12. The other end of the resistor R12 is connected to the anode of the Zener diode D13. The cathode of the Zener diode D13 is connected to the output Vo+ of the secondary circuit.
[0038] The fixed frequency cpu2 square wave pulse signal emitted by the secure computer platform passes through the light-emitting diode of the optocoupler IC11, so that the output end of IC11 outputs high voltage and pulls down voltage at the same frequency. When the output end of IC11 outputs high voltage, the capacitors C11 and C12 are charged through the resistor R11. When the output end of IC11 pulls down voltage, the capacitor C11 is discharged through the resistor R11 and the PNP transistor Q12. Since the capacitor C11 has a charging and discharging process, the totem pole circuit composed of the NPN transistor Q11 and the PNP transistor Q12 is driven to form high and low level signals. In order to make the totem pole circuit easier to output a high level, a voltage holding circuit composed of a diode D10, a capacitor C12, and a resistor R13 is designed.
[0039] The output Vo+ of the forward power circuit controls the light intensity of the light-emitting diode of IC12 through the resistor R12 and the voltage regulator Z13, thereby affecting the magnitude of the current flowing through the phototransistor of IC12. The magnitude of the current flowing through the phototransistor of IC12 determines the time when the totem pole circuit outputs a high voltage. When the Vo+ voltage is high, the light-emitting diode of IC12 emits strong light, the current flowing through the phototransistor of IC12 is large, and the time when the totem pole circuit outputs a high voltage is short. When the Vo+ voltage is low, the light-emitting diode of IC12 emits weak light, the current flowing through the phototransistor of IC12 is small, and the time when the totem pole circuit outputs a high voltage is long, thus completing the modulation of the forward PWM signal.
[0040] The forward power circuit uses Vdc as input and generates a stable voltage output under the control of the forward PWM signal. Since the transformer in the forward power circuit must be under alternating voltage to transfer energy from the primary winding to the secondary winding, if the cpu2 square wave signal disappears, the forward PWM signal disappears, the switch tube in the forward power circuit does not work, and cannot generate alternating voltage to the primary winding of the transformer, so the secondary winding of the transformer will not couple out energy, and the forward power circuit has no output.
[0041] If the output V1 of the first-stage circuit is zero, the forward PWM signal of the second-stage forward PWM signal generating circuit disappears, and the second-stage forward voltage stabilizing circuit has no voltage output.
[0042] In the above-mentioned logic and gate relay driving circuit for signal processing, the flyback PWM signal generating circuit uses the input voltage as the power supply, takes the fixed frequency of the cpu1 square wave signal as its own fixed frequency, collects the output voltage of the flyback power circuit, and generates a PWM signal with a duty cycle required to maintain output stability; at the same time, the forward PWM signal generating circuit uses the fixed frequency of the cpu2 square wave signal as its own fixed frequency, collects the output voltage of the forward power circuit, and generates a PWM signal with a duty cycle required to maintain output stability. Therefore, it is not necessary to occupy the calculation amount of the computer platform to regulate the two PWM signals. Moreover, the first-stage circuit can generate a stable voltage V1 output under the full range of the input power supply, and provide power to the output side of the second optocoupler driver in the second stage and the forward PWM signal generating circuit, thereby maintaining a stable output within a wide voltage input range; the first-stage power output device adopts a flyback power supply topology, with a small power load, and does not require a large transformer, reducing costs and PCB area.
[0043] In one embodiment, Figure 1 and Figure 3As shown, the flyback power circuit includes: a transformer T1, a MOS tube Q2, a rectifier tube D1 and a capacitor C3; one end of the primary winding of the transformer T1 is the input power supply end, the other end of the primary winding of the transformer T1 is connected to the drain of the MOS tube Q2, and the source of the MOS tube Q2 is connected to the resistor R3; one end of the secondary winding of the transformer T1 is connected to one end of the rectifier tube D1, the other end of the rectifier tube D1 is connected to the output power supply end, and the other end of the secondary winding of the transformer T1 is connected to the gate of the MOS tube Q2; a ninth node is set on the connecting line between the other end of the rectifier tube D1 and the output power supply end to lead out a tenth branch, the tenth branch is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the gate of the MOS tube Q2.
[0044] In one embodiment, Figure 1 or Figure 4 As shown, the forward power circuit includes: a transformer T11, a MOS tube Q13, a rectifier tube D11, a rectifier tube D12 and a capacitor C13;
[0045] One end of the first primary coil of the transformer T11 is connected to the output end of the front-stage voltage stabilizing circuit, and the other end of the first primary coil of the transformer T11 is connected to the drain of the MOS tube Q13; a connection line between one end of the first primary coil of the transformer T11 and the output end of the front-stage voltage stabilizing circuit is provided with a tenth node to lead out an eleventh branch, the eleventh branch is connected to one end of the rectifier tube D11, and the other end of the rectifier tube D11 is connected to one end of the second primary coil of the transformer T11; the other end of the second primary coil of the transformer T11 is connected to the source of the MOS tube Q13; the gate of the MOS tube Q13 is connected to the resistor R14;
[0046] One end of the secondary coil of the transformer T11 is connected to one end of the rectifier D12, and the other end of the rectifier D12 is connected to the positive output port of the load; an eleventh node is set on the connection line between the other end of the rectifier D12 and the positive output port of the load to lead out a twelfth branch, the twelfth branch is connected to one end of the capacitor C13, and the other end of the capacitor C13 is connected to the other end of the secondary coil of the transformer T11; a twelfth node is set on the connection line between the other end of the capacitor C13 and the other end of the secondary coil of the transformer T11 to lead out a thirteenth branch, and the thirteenth branch is connected to the negative output port of the load.
[0047] In one embodiment, the pre-stage voltage stabilization circuit includes: a pre-stage voltage regulator VT11, the input end of the pre-stage voltage regulator VT11 is a power input end, and the output end of the pre-stage voltage regulator VT11 is connected to one end of the primary coil of the transformer T11 in the forward power circuit.
[0048] Specifically, since the input voltage fluctuation range is relatively wide, the pre-stage voltage stabilization circuit can use a buck circuit, a boost circuit or a buck-boost circuit to convert the input fluctuating voltage into a stable voltage Vdc output to supply the forward power circuit, such as Figure 5 The forward PWM signal generated by the totem pole drives the MOS tube Q13 in the forward power circuit through the resistor R14, so that the forward power circuit outputs a stable voltage.
[0049] In one embodiment, the model of the three-terminal regulator VT1 is LM7812 or LM7815.
[0050] In this application, receiving the first cpu1 square wave signal and the second cpu2 square wave signal is the only way to establish oscillation. In the case of interruption of the first cpu1 square wave signal or the second cpu2 square wave signal, the voltage outputted by the output terminal of the second stage circuit is zero, which complies with the "fail-safe" principle.
[0051] If any circuit output in the present application is abnormal or a device is damaged, the oscillation output cannot be established by itself, and the voltage output at the output end of the second-stage circuit is zero, which complies with the "fail-safe" principle.
[0052] This application includes at least the following advantages:
[0053] 1. Modular structure, consisting of a first optical coupler, a flyback PWM signal generating circuit, a flyback power circuit, a second optical coupler driver, a forward PWM signal generating circuit, a front-stage voltage stabilizing circuit, and a forward power circuit.
[0054] 2. The first-stage power output device adopts a flyback power supply topology with a small power load and does not require a large transformer, thus reducing costs and PCB area.
[0055] 3. The requirements for the security computer platform are simple, and the security computer platform does not need to calculate the duty cycle, and the application adaptability is strong;
[0056] 4. It has strong adaptability to input voltage fluctuations and can maintain stable output within a wide voltage input range;
[0057] 5. After failure mode analysis, any component failure in the circuit will not affect the guidance safety function.
[0058] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0059] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A logic AND gate relay driving circuit for signal processing, characterized in that: include: A first level circuit and a second level circuit; The first stage circuit includes a first coupler IC1 and a flyback regulated power supply circuit; the second stage circuit includes a second optical coupling driver IC11 and a forward regulated power supply circuit; the anode of the light emitting diode in the first coupler IC1 is the input end of the first square wave signal; the anode of the light emitting diode in the second optical coupling driver IC11 is the input end of the second square wave signal; The flyback voltage-stabilized power supply circuit comprises a flyback PWM signal generating circuit and a flyback power circuit, wherein the flyback PWM signal generating circuit comprises a three-terminal voltage regulator VT1, a transistor Q1, an optocoupler IC2, a voltage regulator Z1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, and a capacitor C2; the input end of the three-terminal voltage regulator VT1 is a power input end, the output end of the three-terminal voltage regulator VT1 is connected to the collector of the transistor Q1, and a first node is set on the connection line between the output end of the three-terminal voltage regulator VT1 and the collector of the transistor Q1, A first branch is led out from the first node to connect one end of a resistor R1, and the other end of the resistor R1 is connected to the base of the transistor Q1; the base of the transistor Q1 is connected to the collector of the phototransistor in the first coupler IC1; the emitter of the transistor Q1 is connected to one end of a resistor R2, and the other end of the resistor R2 is connected to the emitter of the phototransistor in the first coupler IC1; a second branch is led out from the connection point between the other end of the resistor R1 and the base of the transistor Q1, and the second branch is connected to one end of the capacitor C1. The other end of C1 is connected to the other end of the resistor R2 and the emitter connection line of the phototransistor in the first coupler IC1 and then grounded; one end of the resistor R3 is connected to the flyback power circuit, and the other end of the resistor R3 is connected to the other end of the resistor R2. A second node is set on the connection line between the emitter of the transistor Q1 and one end of the resistor R2, and a third branch is drawn from the second node to connect one end of the capacitor C2. The other end of the capacitor C2 is connected to the connection line between one end of the resistor R3 and the flyback power circuit. A third node is set on the line connected to the flyback power circuit, a fourth branch is drawn from the third node to connect the collector of the phototransistor in the optocoupler IC2, and the emitter of the phototransistor in the optocoupler IC2 is connected to the other end of the resistor R3; the anode of the photosensitive diode in the optocoupler IC2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the output power supply end of the flyback power circuit; the cathode of the photosensitive diode in the optocoupler IC2 is connected to one end of the voltage regulator Z1, and the other end of the voltage regulator Z1 is connected to the other end of the resistor R3 and then grounded; The forward voltage-stabilized power supply circuit comprises a forward PWM signal generating circuit, a forward power circuit and a front-stage voltage-stabilizing circuit; the forward PWM signal generating circuit comprises a transistor Q11, a transistor Q12, an optical coupler IC12, a diode D10, a voltage-stabilizing diode D13, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C11, and a capacitor C12; the output power supply end of the flyback power circuit is respectively connected to the collector of the transistor Q11 and the driving side input end of the second optical coupling driver IC11; the base of the transistor Q11 is connected in series with the capacitor C11, the resistor R11 in sequence; The emitter of the transistor Q11 is connected to the emitter of the transistor Q12, the base of the transistor Q12 is connected to the anode of the diode D10, the cathode of the diode D10 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is connected to the emitter of the photosensitive transistor in the optical coupler IC12; a fourth node is set on the connecting line between the cathode of the diode D10 and one end of the capacitor C12 to lead out a fifth branch, the fifth branch is connected to one end of the resistor R13, and the resistor R13 The other end is connected to the capacitor C12 and the emitter connection line of the photosensitive transistor in the optocoupler IC12, a fifth node is set on the capacitor C12 and the emitter connection line of the photosensitive transistor in the optocoupler IC12 to lead out a sixth branch, and the sixth branch is grounded; a sixth node is set on the connection line between the capacitor C11 and the base of the transistor Q11 to lead out a seventh branch, and the seventh branch is connected to the base of the transistor Q12 and the anode connection line of the diode D10; a seventh node is set on the connection line between the resistor R11 and the capacitor C11 to lead out an eighth branch, and the eighth branch is connected to the optocoupler I The collector of the phototransistor in C12; an eighth node is set on the connecting line between the emitter of the transistor Q11 and the emitter of the transistor Q12 to lead out a ninth branch, and the ninth branch is connected to the resistor R14 and then connected to the forward power circuit; the anode of the diode in the optocoupler IC12 is connected to the resistor R12 and the voltage regulator diode D13 in sequence and then connected to the load positive output port of the forward power circuit; the cathode of the diode in the optocoupler IC12 is the load negative output port; the input port of the front-stage voltage regulator circuit is the power input terminal, and the output terminal of the front-stage voltage regulator circuit is connected to the forward power circuit.
2. The logic AND gate relay driving circuit for signal processing according to claim 1, characterized in that: The flyback power circuit includes: a transformer T1, a MOS tube Q2, a rectifier tube D1 and a capacitor C3; one end of the primary winding of the transformer T1 is an input power supply end, the other end of the primary winding of the transformer T1 is connected to the drain of the MOS tube Q2, and the source of the MOS tube Q2 is connected to the resistor R3; one end of the secondary winding of the transformer T1 is connected to one end of the rectifier tube D1, the other end of the rectifier tube D1 is connected to the output power supply end, and the other end of the secondary winding of the transformer T1 is connected to the gate of the MOS tube Q2; a ninth node is set on the connecting line between the other end of the rectifier tube D1 and the output power supply end to lead out a tenth branch, the tenth branch is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the gate of the MOS tube Q2.
3. The logic AND gate relay driving circuit for signal processing according to claim 1, characterized in that: The forward power circuit includes: a transformer T11, a MOS tube Q13, a rectifier tube D11, a rectifier tube D12 and a capacitor C13; One end of the first primary coil of the transformer T11 is connected to the output end of the front-stage voltage stabilizing circuit, and the other end of the first primary coil of the transformer T11 is connected to the drain of the MOS tube Q13; a connection line between one end of the first primary coil of the transformer T11 and the output end of the front-stage voltage stabilizing circuit is provided with a tenth node to lead out an eleventh branch, the eleventh branch is connected to one end of the rectifier tube D11, and the other end of the rectifier tube D11 is connected to one end of the second primary coil of the transformer T11; the other end of the second primary coil of the transformer T11 is connected to the source of the MOS tube Q13; the gate of the MOS tube Q13 is connected to the resistor R14; One end of the secondary coil of the transformer T11 is connected to one end of the rectifier D12, and the other end of the rectifier D12 is connected to the positive output port of the load; an eleventh node is set on the connection line between the other end of the rectifier D12 and the positive output port of the load to lead out a twelfth branch, the twelfth branch is connected to one end of the capacitor C13, and the other end of the capacitor C13 is connected to the other end of the secondary coil of the transformer T11; a twelfth node is set on the connection line between the other end of the capacitor C13 and the other end of the secondary coil of the transformer T11 to lead out a thirteenth branch, and the thirteenth branch is connected to the negative output port of the load.
4. The logic AND gate relay driving circuit for signal processing according to claim 3, characterized in that: The front-stage voltage stabilization circuit comprises: a front-stage voltage stabilizer VT11, the input end of the front-stage voltage stabilizer VT11 is a power input end, and the output end of the front-stage voltage stabilizer VT11 is connected to one end of the primary coil of the transformer T11 in the forward power circuit.
5. The logic AND gate relay driving circuit for signal processing according to claim 1, characterized in that: The model of the three-terminal voltage regulator VT1 is LM7812 or LM7815.