Semiconductor package

Abstract

A semiconductor package includes a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, a non-conductive film formed between the first semiconductor die and the package substrate, and a capillary underfill material formed between the second semiconductor die and the package substrate. A non-conductive film may be formed in a first region over a surface of the package substrate, and a capillary underfill material may be formed in a second region over the surface of the package substrate such that the second region surrounds the first region in a plan view. The semiconductor package may further include a multi-die frame surrounding the first and second semiconductor dies such that a multi-die chip including the first and second semiconductor dies and the multi-die frame is formed.

Description

Technical Field

[0001] The embodiments of the utility model relate to packaging technology, and in particular to a semiconductor package. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are generally made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography techniques to form circuit components and elements thereon. Dozens, hundreds, or thousands of integrated circuits can be manufactured on a single semiconductor wafer, and the individual dies on the wafer can be separated by sawing along the dicing lines between the integrated circuits. The individual dies can be individually packaged, for example, in a multi-chip module or other type of package.

[0003] As semiconductor packages become more complex, package sizes have tended to become larger to accommodate a greater number of integrated circuits and / or dies per package. These larger and more complex semiconductor packages present additional challenges for achieving effective and reliable electrical interconnects within the semiconductor package. Other challenges include mechanical issues associated with coefficient of thermal expansion (CTE) mismatches between package components, leading to warping, cracking, delamination, etc. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor package to solve at least one of the above problems.

[0005] In some embodiments, a semiconductor package is provided, which includes a packaging substrate; a first semiconductor die electrically and mechanically coupled to the packaging substrate; a second semiconductor die electrically and mechanically coupled to the packaging substrate; a non-conductive film formed between the first semiconductor die and the packaging substrate; and a capillary bottom filling material formed between the second semiconductor die and the packaging substrate.

[0006] According to one embodiment of the present invention, the non-conductive film is formed in a first area above a surface of the packaging substrate, and the capillary bottom filling material is formed in a second area above the surface of the packaging substrate, and wherein in a plan view, the second area surrounds the first area.

[0007] According to one embodiment of the present invention, one or more additional second semiconductor dies are further included, which are located in the second region, so that the capillary bottom filling material is disposed between the one or more additional second semiconductor dies and the packaging substrate.

[0008] According to one embodiment of the present invention, the non-conductive film comprises a first width, and the capillary bottom filling material comprises a second width, wherein the second width is at least 20% greater than the first width.

[0009] According to one embodiment of the present invention, the non-conductive film includes a first area, and the capillary bottom filling material includes a second area, and the second area is at least 50% larger than the first area.

[0010] According to one embodiment of the present invention, a molding compound is further included, partially surrounding the first semiconductor die and the second semiconductor die to form a multi-die frame, so as to form a multi-die chip including the first semiconductor die, the second semiconductor die and the multi-die frame.

[0011] According to one embodiment of the present invention, the multi-die chip includes a chip width that is smaller than the second width.

[0012] According to one embodiment of the present invention, the semiconductor package also includes a first spacing distance between a bottom surface of the multi-grain chip and the surface of the packaging substrate and a second spacing distance between a top surface of the multi-grain chip and the surface of the packaging substrate; the capillary bottom filling material includes a bottom filling fillet that contacts and extends laterally beyond the side of the multi-grain chip and contacts a portion of the surface of the packaging substrate; and the bottom filling fillet includes a fillet height that is greater than the first spacing distance and less than the second spacing distance.

[0013] In some embodiments, a semiconductor package is provided, the semiconductor package comprising a packaging substrate; a multi-die chip attached to the packaging substrate; a non-conductive film formed in a first region between the multi-die chip and the packaging substrate; and a capillary bottom filling material formed in a second region between the multi-die chip and the packaging substrate.

[0014] According to one embodiment of the present invention, in a plan view, the capillary bottom filling material surrounds the first area, the capillary bottom filling material includes a second width that is at least 20% larger than a first width of the non-conductive film, and the capillary bottom filling material includes a second area that is at least 50% larger than a first area of ​​the non-conductive film. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0016] Figure 1A An exploded vertical cross-sectional view of the components of a semiconductor package during package assembly and surface mount processing.

[0017] Figure 1B A schematic vertical cross-sectional view showing an assembled semiconductor package mounted on a surface of a carrier substrate.

[0018] Figure 2A FIG. 4 is a top view of a semiconductor package including an external reinforcement structure.

[0019] Figure 2B for Figure 2A A schematic vertical cross-sectional view of a semiconductor package.

[0020] Figure 2C for Figure 2B A schematic vertical cross-sectional view of an enlarged portion of a semiconductor package.

[0021] Figure 3A FIG. 1 is a top view of a semiconductor package including a multi-die chip according to various embodiments.

[0022] Figure 3B According to various embodiments, Figure 3A A schematic vertical cross-sectional view of a semiconductor package.

[0023] Figure 4A FIG. 4 is a vertical cross-sectional view of another semiconductor package including a multi-die chip and a hybrid underfill structure according to various embodiments.

[0024] Figure 4B To remove a multi-die chip according to various embodiments Figure 4A A top view of a semiconductor package is shown to show details of the hybrid underfill structure.

[0025] Figure 4C FIG. 4 is a vertical cross-sectional view of another semiconductor package including a hybrid underfill structure according to various embodiments.

[0026] Figure 5A FIG. 2 is a schematic vertical cross-sectional view of an intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0027] Figure 5B FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0028] Figure 5C FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0029] Figure 5D FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0030] Figure 5E FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0031] Fig. 5F FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0032] Figure 5G FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0033] Figure 5H FIG. 2 is a schematic vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0034] Figure 6 A flow chart is shown of various operations in a method of forming a semiconductor package in accordance with various embodiments.

[0035] The reference numerals are as follows:

[0036] 100,200,300,400a,400c:Semiconductor package

[0037] 102: Carrying base

[0038] 104: first semiconductor grain

[0039] 106: second semiconductor grain

[0040] 107: Semiconductor grains

[0041] 108: Intermediary layer

[0042] 110: packaging substrate

[0043] 112: Solder ball

[0044] 114: Lower surface

[0045] 116,126: Upper surface

[0046] 118: Arrow

[0047] 120,124: Metal bumps

[0048] 122: first bottom filling material portion

[0049] 128: Second bottom filling material portion

[0050] 130,132: Conductive bonding pads

[0051] 134: Third bottom filling material portion

[0052] 202:Multi-die epoxy molding compound frame

[0053] 204: External reinforcement structure

[0054] 206: Adhesive

[0055] 208: Area

[0056] 210: Crack

[0057] 302: Multi-die chip

[0058] 304: Rewiring layer

[0059] 306: Conductive chip bonding structure

[0060] 308: Flux

[0061] 310: Gap

[0062] 402: Non-conductive film

[0063] 404: First Width

[0064] 406: Second Width

[0065] 408: Chip width

[0066] 409: Package width

[0067] 410: First separation distance

[0068] 412: Second separation distance

[0069] 414: Bottom fillet

[0070] 416: Fillet height

[0071] 419: Pad diameter

[0072] 420: Spacing

[0073] 422: Conductive grain bonding structure

[0074] 424: Bump height

[0075] 426: Initial membrane height

[0076] 500a,500b,500c,500d,500e,500f,500g,500h:Intermediate structure

[0077] 502: Film dispensing equipment

[0078] 504: Flux dispensing equipment

[0079] 506: Thermocompression bonding head

[0080] 508: Capillary bottom fill material dispenser

[0081] 600: Method

[0082] 602,604,606,608: Operation

[0083] C: Dashed rectangle DETAILED DESCRIPTION

[0084] It should be understood that the following disclosure provides many different embodiments or examples to implement different parts of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the utility model. For example, the size of the component is not limited to the scope or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed in direct contact, and may also include an additional component that can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the appearance structure.

[0085] Furthermore, in order to facilitate the description of the relationship between an element or component and another (plural) element or (plural) component in the drawings, spatially related terms, such as "under...", "below", "lower", "above...", "upper" and similar terms, may be used. In addition to the orientation shown in the drawings, spatially related terms also cover different orientations of the device in use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the description of the spatially related terms used shall be interpreted accordingly. Unless otherwise expressly stated, each element with the same reference symbol is assumed to have the same material composition and have a thickness in the same thickness range.

[0086] Generally, in a semiconductor package, one or more semiconductor integrated circuit (IC) dies may be mounted on a common substrate, which may also be referred to as a "package substrate". In some embodiments, electrical connection to the semiconductor package may be achieved by mounting the package substrate on a carrier substrate containing electrical interconnects (e.g., a printed circuit board (PCB)). The semiconductor die or multi-die chip may be attached to the package substrate by using a bulk reflow process to melt a portion of the solder and then resolidify to form metallurgical bonds between the semiconductor die (or multi-die chip) and the corresponding electrical bonding structure on the package substrate. A cleaning fluid may be introduced to remove the flux used in the bulk reflow process, which may remain between the semiconductor die (or multi-die chip) and the package substrate. Then, a capillary underflow material may be introduced between the semiconductor die (or multi-die chip) and the package substrate to protect the bonding structure from heat-induced stress / strain.

[0087] However, in larger semiconductor packages containing fine pitch interconnects, limited capillary flow can result in reduced efficiency of the flux cleaning process and reduced ability of the capillary underfill material to completely fill the narrow space between the semiconductor die and the package substrate, which can result in flux residue and voids in the capillary underflow material. The remaining flux residue can have a corrosive effect, which can damage the electrical bonding structure, and the presence of voids can reduce the ability of the capillary underfill material to effectively protect the bonding structure from thermal stress / strain.

[0088] Various embodiments disclosed herein may provide an improved method for assembling a semiconductor package that can mitigate mechanical issues associated with thermal expansion mismatches between package components that may otherwise result in warping, cracking, delamination, and the like. In this regard, embodiments disclosed herein provide a hybrid bottom fill structure that includes a non-conductive film in a central region between a semiconductor die (or a multi-die chip) and a package substrate in a plan view and a capillary bottom fill material surrounding the non-conductive film. Before attaching the semiconductor die (or multi-die chip) to the package substrate, the non-conductive film may be placed on the surface of the package substrate. The presence of the non-conductive film in the central region may reduce the volume occupied by the capillary bottom fill material in the surrounding region. Thus, the capillary flow distance may be reduced, thereby more efficiently cleaning flux residues and more efficiently placing capillary underflow materials. In this way, the presence of flux residues and voids between the semiconductor die (or multi-die chip) and the package substrate may be reduced or eliminated to increase the protection of the electrical bonding structure, resulting in improved device performance.

[0089] An embodiment of a semiconductor package may include a package substrate; a first semiconductor die electrically and mechanically coupled to the package substrate; a second semiconductor die electrically and mechanically coupled to the package substrate; a non-conductive film formed between the first semiconductor die and the package substrate; and a capillary underfill material formed between the second semiconductor die and the package substrate. The non-conductive film may be formed in a first region above a surface of the package substrate, and the capillary underfill material may be formed in a second region above a surface of the package substrate, such that in a plan view, the second region surrounds the first region. The semiconductor package may further include a multi-die frame, the multi-die frame partially surrounding the first semiconductor die and the second semiconductor die, so that a multi-die chip including the first semiconductor die, the second semiconductor die, and the multi-die frame is formed.

[0090] Another embodiment of a semiconductor package may include a packaging substrate; a multi-die chip attached to the packaging substrate; a non-conductive film formed in a first region between the multi-die chip and the packaging substrate; and a capillary bottom fill material formed in a second region between the multi-die chip and the packaging substrate. In a plan view, the capillary bottom fill material may surround the first region and may have a second width that is at least 20% greater than the first width of the non-conductive film. The capillary bottom fill material may also have a second area that is at least 50% greater than the first area of ​​the non-conductive film. In various embodiments, the multi-die chip may have a chip width greater than or equal to 50 mm and a bonding structure having a pitch less than or equal to 300 μm. In some embodiments, the packaging substrate has a package width greater than or equal to 72 mm.

[0091] An embodiment of a method for forming a semiconductor package may include forming a non-conductive film over a first region of a package substrate; attaching a first semiconductor die to the package substrate over the first region so that the non-conductive film is disposed between the package substrate and the first semiconductor die; attaching a second semiconductor die to a second region of the package substrate; and forming a capillary underfill material between the second semiconductor die and the package substrate. Attaching the first semiconductor die and the second semiconductor die to the package substrate may further include placing the first semiconductor die over the first region of the package substrate, placing the second semiconductor die over the second region of the package substrate; and performing a thermocompression bonding process to electrically and mechanically couple the first semiconductor die and the second semiconductor die to the package substrate.

[0092] Figure 1A FIG. 1 is a vertical cross-sectional exploded view of components of the semiconductor package 100 during package assembly and surface mounting processes. Figure 1B A vertical cross-sectional view of an assembled semiconductor package 100 mounted on a surface of a carrier substrate 102, such as a printed circuit board (PCB), is shown. The semiconductor package 100 in this example is a chip-on-wafer-on-substrate (CoWoS) semiconductor package, but it should be understood that similar assembly and mounting processes can be used for other types of semiconductor packages, such as an integrated fan-out (InFO) semiconductor package, a flip-chip semiconductor package, etc.

[0093] Please refer to Figure 1A and Figure 1B , the semiconductor package may include an integrated circuit (IC) semiconductor device, such as a first semiconductor die 104 and a second semiconductor die 106. During the package assembly process, the first semiconductor die 104 and the second semiconductor die 106 may be mounted on an interposer 108, and the interposer 108 containing the first semiconductor die 104 and the second semiconductor die 106 may be mounted on a package substrate 110 to form a semiconductor package 100. Then, the package substrate 110 is mounted to a carrier substrate 102 by using an array of solder balls 112 on a lower surface 114 of the semiconductor package 100, and the semiconductor package 100 may be mounted on a carrier substrate 102 (e.g., a printed circuit board (PCB)).

[0094] The parameters that can ensure proper interconnection between the package substrate 110 and the carrier substrate 102 are the mounting surface (i.e. Figure 1AThe coplanarity between the surfaces of the solder balls 112 that contact the upper surface 116 of the carrier substrate 102 is determined by the solder ball 112. Low coplanarity between the solder balls 112 may result in a cold solder joint condition (i.e., insufficient melting of the solder, resulting in a poor joint that is easily cracked and separated) and / or solder bridging problems (i.e., solder material from one solder ball 112 contacts material from an adjacent solder ball 112), resulting in unintended connections (i.e., electrical shorts) during the reflow process.

[0095] Deformation of the package substrate 110 , such as stress-induced warping of the package substrate 110 , may be a cause of low coplanarity of the solder balls 112 during surface mounting of the package substrate 110 onto the carrier substrate 102 . Figure 1B The package substrate 110 is shown to include warpage. The warpage of the package substrate 110 may result in a change in the distance between the lower surface 114 of the package substrate 110 and the upper surface 116 of the carrier substrate 102. Such deformation of the package substrate 110 may increase the risk of defective solder connections to the underlying carrier substrate 102. Figure 1B As shown, for example, the deformation of the package substrate 110 may cause at least some of the solder joints between the package substrate 110 and the carrier substrate 102 to fail completely, such as Figure 1B As shown by arrow 118 in FIG. Figure 1B In the exemplary embodiment shown, the deformation of the packaging substrate 110 can have a bow shape or a cup shape, so that the spacing between the lower surface 114 of the packaging substrate 110 and the upper surface 116 of the supporting substrate 102 can be smallest at the periphery of the packaging substrate 110 and can increase toward the center of the packaging substrate 110.

[0096] Deformation of the package substrate 110 is not uncommon, particularly in the case of semiconductor packages used in high-performance computing applications. These high-performance semiconductor packages 100 are often relatively large and may include multiple semiconductor dies (e.g., the first semiconductor die 104 and the second semiconductor die 106) mounted to the package substrate 110, which may increase the likelihood that the package substrate 110 may warp or otherwise deform. Such deformation may present challenges for effectively solder-mounting these types of package substrates 110 to the carrier substrate 102.

[0097] In various embodiments, the first semiconductor die 104 (sometimes referred to as a three-dimensional semiconductor die, or a first three-dimensional semiconductor die) may be a three-dimensional device, such as a three-dimensional integrated circuit (3DICs), a system-on-chip (SoC) device, or a system on integrated circuit (SoIC) device. The first semiconductor die 104 may be formed by placing a chip on top of a chip at the semiconductor wafer level. These three-dimensional devices may provide improved integration density and other advantages, such as faster speed and higher bandwidth, due to the reduced interconnect length between stacked chips. In some embodiments, the first semiconductor die 104 may also be referred to as a "first die stack".

[0098] The second semiconductor die 106 may be different from the first semiconductor die 104 in structure, design and / or functionality. One or more second semiconductor die 106 may be three-dimensional semiconductor die, and the second semiconductor die 106 may also be referred to as a "second die stack". In some embodiments, the one or more second semiconductor die 106 may include a memory device, such as a high bandwidth memory (HBM) device. Figure 1A and Figure 1B In the illustrated embodiment, the semiconductor package 100 may include a system chip die stack (a first semiconductor die 104 ) and a high bandwidth memory die stack (a second semiconductor die 106 ), but it should be understood that the semiconductor package 100 may include a greater or lesser number of semiconductor dies.

[0099] Please refer to Figure 1B, the first semiconductor die 104 and the second semiconductor die 106 may be mounted on the interposer 108. In some embodiments, the interposer 108 may be an organic interposer, which includes a polymer dielectric material (e.g., a polyimide material) having a plurality of metal interconnect structures extending therethrough. In other embodiments, the interposer 108 may be a semiconductor interposer, such as a silicon interposer having a plurality of interconnect structures (e.g., through-silicon vias) extending therethrough. Other configurations suitable for the interposer 108 are within the contemplation of the embodiments of the present invention. The interposer 108 may include a plurality of conductive bonding pads on the upper and lower surfaces of the interposer and a plurality of conductive interconnects extending through the interposer 108 between the upper and lower bonding pads of the interposer 108. The conductive interconnects may distribute and route electrical signals between the first semiconductor die 104, the second semiconductor die 106, and the underlying package substrate 110.

[0100] A plurality of metal bumps 120 (e.g., micro-bumps) may electrically connect conductive bonding pads on the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 106 to the upper surface of the interposer 108. In a non-limiting embodiment, the metal bumps 120 in the form of micro-bumps may include a plurality of first metal stacks (e.g., a plurality of copper-nickel-copper stacks) located on the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 106 and a plurality of second metal stacks (e.g., copper-nickel-copper stacks) located on the upper surface of the interposer 108. Solder material (e.g., tin (Sn)) may be located between the corresponding first and second metal stacks to electrically connect the first semiconductor die 104 and the second semiconductor die 106 to the interposer 108. Other materials suitable for the metal bumps 120 are within the contemplation of the embodiments of the present invention.

[0101] After the first semiconductor die 104 and the second semiconductor die 106 are mounted to the interposer 108, a first underfill material portion 122 may be selectively provided in the space surrounding the metal bump 120 and in the space between the bottom surface of the first semiconductor die 104, the second semiconductor die 106 and the upper surface of the interposer 108. Figure 1B A first bottom filling material portion 122 may also be provided in the space laterally separating the adjacent first semiconductor die 104 and second semiconductor die 106 of the semiconductor package 100. In various embodiments, the first bottom filling material portion 122 may include an epoxy-based material, which may include a composite material of a resin and a filling material.

[0102] Please refer to Figure 1B, the interposer 108 may be mounted on a package substrate 110, which may provide mechanical support for the interposer 108 and the first semiconductor die 104 and the second semiconductor die 106 mounted on the interposer 108. The package substrate 110 may include suitable materials, such as organic materials (e.g., polymers and / or thermoplastic materials), semiconductor materials (e.g., semiconductor wafers, such as silicon wafers), ceramic materials, glass materials, combinations of the foregoing, and the like. Other suitable substrate materials are within the scope of embodiments of the present invention. In various embodiments, the package substrate 110 may include a plurality of conductive bonding pads (not shown) in an upper surface 126 of the package substrate 110. A plurality of metal bumps 124 (e.g., C4 solder bumps) may electrically connect the conductive bonding pads (not shown) on the bottom surface of the interposer 108 to the conductive bonding pads on the upper surface 126 of the package substrate 110. In various embodiments, the metal bumps 124 may include suitable solder materials, such as tin (Sn), but other suitable solder materials are within the contemplation scope of embodiments of the present invention.

[0103] A second underfill material portion 128 may be provided in the space surrounding the metal bump 124 and in the space between the bottom surface of the interposer 108 and the upper surface 126 of the package substrate 110, such as Figure 1B In various embodiments, the second bottom filling material portion 128 may include an epoxy resin-based material, which may include a composite material of a resin and a filling material. In some embodiments, a cover or covering (not shown) Figure 1A and Figure 1B ) can be mounted to the package substrate 110 and can provide a housing surrounding the upper surface and side surfaces of the first semiconductor die 104 and the second semiconductor die 106 .

[0104] As described above, the package substrate 110 can be mounted to a carrier substrate 102, such as a printed circuit board (PCB). Other suitable carrier substrates 102 are within the contemplation of the present utility model embodiments. The package substrate 110 can include a plurality of conductive bonding pads 130 (sometimes also referred to as package bonding structures) in the lower surface 114 of the package substrate 110. A plurality of conductive interconnects (not shown) can extend through the package substrate 110 between the conductive bonding pads on the upper surface 126 and the lower surface 114 of the package substrate 110. A plurality of solder balls 112 (or bump structures) can electrically connect the conductive bonding pads 130 on the lower surface 114 of the package substrate 110 to a plurality of conductive bonding pads 132 on the upper surface 116 of the carrier substrate 102.

[0105] The conductive bonding pads 130 of the package substrate 110 and the conductive bonding pads 132 of the carrier substrate 102 can be formed of suitable conductive materials, such as copper. Other suitable conductive materials are within the scope of consideration of the present utility model embodiment. A plurality of solder balls 112 on the lower surface 114 of the package substrate 110 can form an array of solder balls 112, such as a ball grid array (BGA) that can include an array pattern corresponding to the conductive bonding pads 132 on the upper surface 116 of the carrier substrate 102. In a non-limiting example, the array of solder balls 112 can include a grid pattern and can have a spacing (i.e., the distance between the center of each solder ball 112 and the center of each adjacent solder ball 112). In an exemplary embodiment, the spacing can be between about 0.8 and 1.0 mm, but larger and smaller spacings can be used. The solder balls 112 can include any suitable soldering material, such as tin, lead, silver, indium, zinc, nickel, bismuth, antimony, cobalt, copper, germanium, the aforementioned alloys, the aforementioned combinations or the like. Other suitable materials for the solder balls 112 are within the contemplated scope of the present invention.

[0106] In some embodiments, the lower surface 114 of the package substrate 110 may include a coating of a solder resist (SR) material (not shown), which may also be referred to as a "solder mask". The solder resist coating may provide a protective coating for the package substrate 110 and any underlying circuit patterns formed on or in the package substrate 110. The solder resist coating may also inhibit solder material from adhering to the lower surface 114 of the package substrate 110 during a reflow process. In embodiments where the lower surface 114 of the package substrate 110 includes a solder resist coating, the solder resist coating may include a plurality of openings that may expose the conductive bonding pads 130.

[0107] In various embodiments, each conductive bonding pad 130 in different regions of the package substrate 110 may have the same size and shape. Figure 1A and Figure 1B In the illustrated embodiment, the surface of the conductive bonding pad 130 may be substantially coplanar with the lower surface 114 of the package substrate 110, and in some embodiments, the lower surface 114 of the package substrate 110 may include a solder resist (SR) coating. Alternatively, the surface of the conductive bonding pad 130 may be recessed relative to the lower surface 114 of the package substrate 110. In some embodiments, the surface of the conductive bonding pad 130 may be elevated relative to the lower surface 114 of the package substrate 110.

[0108] Please refer to Figure 1A and Figure 1B, solder balls 112 may be provided over corresponding conductive bonding pads 130. In a non-limiting example, the conductive bonding pads 130 may have a width dimension between about 500 μm and about 550 μm (e.g., about 530 μm), and the solder balls 112 may have an outer diameter between about 600 μm and about 650 μm (e.g., about 630 μm), but larger and smaller dimensions of the solder balls 112 and / or the conductive bonding pads 130 are within the contemplation of the present invention.

[0109] The first solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250° C.) to melt the solder balls 112 and cause the solder balls 112 to adhere to the conductive bonding pads 130. After the first reflow process, the package substrate 110 may be cooled so that the solder balls 112 resolidify. After the first reflow process, the solder balls 112 may adhere to the conductive bonding pads 130. Each solder ball 112 may extend a vertical height from the lower surface 114 of the package substrate 110, which may be less than an outer diameter of the solder ball 112 before the first reflow process. For example, where the outer diameter of the solder ball 112 is between about 600 μm and about 650 μm (e.g., about 630 μm), the vertical height of the solder ball 112 after the first reflow process may be between about 500 μm and about 550 μm (e.g., about 520 μm).

[0110] In various embodiments, Figure 1B The process of mounting the package substrate 110 to the carrier substrate 102 as shown may include aligning the package substrate 110 above the carrier substrate 102 so that the solder balls 112 contacting the conductive bonding pads 130 of the package substrate 110 may be located above the corresponding bonding pads (e.g., conductive bonding pads 132) on the carrier substrate 102. Next, a second solder reflow process may be performed. The second solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250° C.) to melt the solder balls 112 and cause the solder balls 112 to adhere to the corresponding conductive bonding pads 132 on the carrier substrate 102. As the solder material cools and solidifies, surface tension may cause the semi-liquid solder to keep the package substrate 110 aligned with the carrier substrate 102. After the solder balls 112 solidify, the package substrate 110 may be located above the upper surface 116 of the carrier substrate 102 at a stand-off height of between about 0.4 mm and about 0.5 mm, but greater or lesser stand-off heights are within the contemplation of embodiments of the present invention.

[0111] After the package substrate 110 is mounted to the carrier substrate 102, a third underfill material portion 134 may be provided in the space surrounding the solder balls 112 and in the space between the lower surface 114 of the package substrate 110 and the upper surface 116 of the carrier substrate 102. Figure 1BIn various embodiments, the third underfill material portion 134 may include an epoxy-based material, which may include a composite material of a resin and a filling material.

[0112] Figure 2A The top view of the semiconductor package 200 including the external reinforcement structure 204 is shown. The external reinforcement structure 204 may be provided to reduce or eliminate Figure 1B The dotted line BB' represents the warpage of the package substrate 110. Figure 2B 1A and 1B. In this regard, the semiconductor package 200 may include a first semiconductor die 104 and a second semiconductor die 106 mounted to an interposer 108 (see, for example, FIG. 1A and FIG. 1B ). Figure 2B ). The interposer 108 may be mounted to the package substrate 110 as described above with reference to Figure 1A and Figure 1B The semiconductor package 200 may include a first underfill material portion 122 provided in a space laterally separating the adjacent first semiconductor die 104 and second semiconductor die 106 of the semiconductor package 200. The semiconductor package 200 may also include a second underfill material portion 128 provided in a space surrounding the metal bump 120 and in a space between the bottom surface of the interposer 108 and the upper surface 126 of the package substrate 110, as shown in FIG. Figure 2B shown.

[0113] The semiconductor package 200 may further include an epoxy molding compound (EMC) that may be applied to the gaps formed between the interposer 108, the first semiconductor die 104, and the second semiconductor die 106 to further form a multi-die epoxy molding compound frame 202 (sometimes simply referred to as a multi-die frame). The epoxy molding compound material may include an epoxy-containing compound that can be hardened (i.e., cured) to provide a dielectric material portion with sufficient rigidity and mechanical strength. The epoxy molding compound may include an epoxy resin, a curing agent, silicon dioxide (as a filler material), and other additives. Depending on the viscosity and fluidity, the epoxy molding compound material may be provided in a liquid form or a solid form.

[0114] Liquid epoxy molding compound can provide better handling, good flowability, fewer voids, better filling effect and fewer flow marks. Solid liquid epoxy molding compound can provide less cure shrinkage, better holding force and less die drift. Higher filler content (e.g., 85% by weight) in epoxy molding compound can shorten the time in mold, reduce mold shrinkage and reduce mold warpage. Uniform distribution of filler size in epoxy molding compound can reduce flow marks and improve flowability. The curing temperature of epoxy molding compound can be in the range of 125° C. to 150° C. The multi-grain epoxy molding compound frame 202 can be cured at the curing temperature to form an epoxy molding compound matrix that laterally surrounds each of the first semiconductor die 104 and the second semiconductor die 106. The multi-die epoxy molding compound frame 202 above a level including top surfaces of the first semiconductor die 104 and the second semiconductor die 106 may be removed by a planarization process such as chemical mechanical polishing.

[0115] Figure 2B for Figure 2A 2 is a vertical cross-sectional view of a semiconductor package 200. The external reinforcement structure 204 may be attached to the package substrate 110 using an adhesive 206 and may be formed of a metal, an insulator, a semiconductor, a ceramic, etc. For example, in one embodiment, the external reinforcement structure 204 may include an atomic percentage of copper greater than 80%, such as greater than 90%, greater than 95%, greater than 99%, etc. In other embodiments, a larger or smaller percentage may be used. Figure 2A As shown, the external reinforcement structure 204 can be configured as a ring around the perimeter of the packaging substrate 110. In this way, the external reinforcement structure 204 can form a single structure. Alternatively, the external reinforcement structure 204 can include several disconnected parts (not shown). Furthermore, the external reinforcement structure 204 need not be located near the perimeter of the packaging substrate 110. Instead, the external reinforcement structure 204 can be located in any area on the packaging substrate 110 that may be subject to mechanical deformation, such as warping.

[0116] The external reinforcement structure 204 can provide enhanced mechanical support to the package substrate 110, thereby reducing or eliminating mechanical deformation, such as the above-mentioned and Figure 1BThe warpage of the package substrate 110 is shown. Therefore, the external reinforcement structure 204 can be selected to have a mechanical strength (e.g., modulus) greater than the mechanical strength of the package substrate 110. As described above, the package substrate 110 can include organic materials (e.g., polymers and / or thermoplastic materials), semiconductor materials (e.g., semiconductor chips, such as silicon chips), ceramic materials, glass materials, combinations of the foregoing, etc. In this way, the material of the external reinforcement structure 204 can be selected based on the mechanical properties of the package substrate 110. Figure 2B As shown, for example, the presence of the external reinforcement structure 204 can reduce or eliminate Figure 1B However, the presence of the external reinforcement structure 204 may cause other mechanical problems, as shown in the following reference Figure 2C Describe in more detail.

[0117] Figure 2C for Figure 2B A cross-sectional schematic diagram of an enlarged portion of a semiconductor package. Figure 2C The displayed area is Figure 2B For some material compositions, there may be a mismatch between the thermal expansion coefficients of the components of the semiconductor package 200 and the thermal expansion coefficients of the external reinforcement structure 204. As a result, thermal expansion stresses may be generated during thermal cycling. Such thermal stresses may cause mechanical degradation of the semiconductor package 200. For example, Figure 2C As shown, the crack 210 may be in the first underfill material portion 122, in the second underfill material portion 128, at an interface, in the metal bump 124, etc. Furthermore, one or both of the first underfill material portion 122 and the second underfill material portion 128 may delaminate from the package substrate 110 and / or from the interposer 108 (not shown).

[0118] In various disclosed embodiments, one or more additional reinforcement structures (not shown) may be provided to compensate for thermal stresses generated between components of the semiconductor package 200 and the external reinforcement structure 204. For example, in some embodiments, a package reinforcement structure (not shown) may be formed in the package substrate 110 (e.g., at Figure 2C Alternatively, other methods of forming a semiconductor package may mitigate the above-mentioned problems associated with mechanical deformation / deterioration that may occur due to thermally induced stress / strain, as described below with reference to Figures 4A to 5H Describe in more detail.

[0119] Figure 3A FIG. 1 is a top view of a semiconductor package 300 including a multi-die chip 302 according to various embodiments. Figure 3B According to various embodiments, Figure 3AA vertical cross-sectional view of a semiconductor package 300 is shown. Figure 3B The vertical plane of the cross-sectional diagram is marked on Figure 3A The cross section BB' of the multi-die chip 302 can be formed in an integrated fan-out wafer-level packaging (FOWLP) process. In this regard, a plurality of known good semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107) can be cut from a starting wafer and can be assembled on a temporary substrate to form a reconstructed wafer (not shown). Next, a multi-die epoxy resin molding compound frame 202 can be formed to surround the plurality of semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107), and the semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107) can be buried in the multi-die epoxy resin molding compound frame 202. Next, one or more redistribution layers 304 may be formed over the semiconductor dies (the first semiconductor dies 104, the second semiconductor dies 106, the semiconductor dies 107) to form electrical connections over the semiconductor dies (the first semiconductor dies 104, the second semiconductor dies 106, the semiconductor dies 107). Next, a conductive chip bonding structure 306 (e.g., a C2 bonding column or a C4 bonding pad) may be formed so that the multi-die chip 302 may be electrically connected to the package substrate 110 in a subsequent mounting operation. Next, the reconstructed wafer may be cut to produce a plurality of multi-die chips 302, which may then be electrically connected to the package substrate 110, as shown in FIG. Figure 3B shown.

[0120] The fan-out wafer-level packaging process described above may be referred to as a “chip first” process, wherein semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107) are first placed on a reconstructed wafer, and then one or more redistribution layers 304 are formed over the semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107). Alternatively, in a “chip last” process, one or more redistribution layers 304 may be formed on a carrier substrate in a first operation. In a subsequent operation, the semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107) may then be attached to the one or more redistribution layers 304, and a multi-die epoxy molding compound frame 202 may be formed around the attached semiconductor dies (first semiconductor die 104, second semiconductor die 106, semiconductor die 107). In the chip-first and chip-last fan-out wafer level packaging processes, the one or more redistribution layers 304 may have a fan-out appearance, so that the pitch of the conductive chip bonding structure 306 is greater than the pitch of the electrical connectors (not shown) formed on the semiconductor dies (the first semiconductor die 104, the second semiconductor die 106, the semiconductor die 107). For example, in one embodiment, the electrical connectors (not shown) formed on the semiconductor dies (the first semiconductor die 104, the second semiconductor die 106, the semiconductor die 107) may have a pad diameter between 55 μm and 65 μm and a pitch between 95 μm and 110 μm, and the conductive chip bonding structure 306 formed on the one or more redistribution layers 304 may have a pad diameter between 90 μm and 120 μm and a pitch between 295 μm and 305 μm. The above dimensions are provided as examples only, and in other embodiments, various other dimensions may be provided.

[0121] like Figure 3A and Figure 3B As shown, semiconductor package 300 may include a first semiconductor die 104 and a plurality of second semiconductor dies 106. In various embodiments, first semiconductor die 104 may be configured as a three-dimensional device, such as a three-dimensional integrated circuit (3DICs), a system-on-chip (SoC) device, or a system-on-IC (SoIC) device.

[0122] Each first semiconductor die 104 may be formed by placing chips on top of chips at the semiconductor wafer level to form a three-dimensional device. Due to the reduced interconnect length between stacked chips, these three-dimensional devices may provide improved integration density and other advantages, such as faster speed and higher bandwidth. In some embodiments, each first semiconductor die 104 may also be referred to as a "first die stack". In some embodiments, each first semiconductor die 104 may be a die or chip, such as a logic die or a power management die.

[0123] exist Figure 3A In the semiconductor package 300 of FIG. 1 , the first semiconductor die 104 may include a first die stack, and the first die stack may be configured as a system chip device. In various embodiments, the first semiconductor die 104 may be located in a central region of the semiconductor package 300. A plurality of second semiconductor dies 106 may be located adjacent to the first semiconductor die 104, such as Figure 3A As shown. In this exemplary embodiment, the plurality of second semiconductor dies 106 may include two semiconductor dies. In some embodiments, the plurality of second semiconductor dies 106 may be a three-dimensional integrated circuit semiconductor device, and may also be referred to as a "second die stack". In some embodiments, the plurality of second semiconductor dies 1066 may each be a semiconductor memory device, such as a high bandwidth memory (HBM) device. Although the semiconductor package 300 in this exemplary embodiment includes seven semiconductor dies (the first semiconductor die 104, the second semiconductor die 106, and the semiconductor die 107), in other embodiments, more or fewer die stacks may be included in other semiconductor packages.

[0124] like Figure 3B As shown, one or more redistribution layers 304 may eliminate the need for a separate interposer, e.g. Figure 1A and Figure 1B The semiconductor package 100 and Figure 2A to Figure 2C Thus, the multi-die chip 302 (i.e., a "chip-first" integrated fan-out device) of the embodiment of FIGS. 3A and 3B can also eliminate the need for Figure 1A and Figure 1B The semiconductor package 100 and Figure 2A to Figure 2C The semiconductor package 200 has a plurality of metal bumps 120 (eg, micro bumps) and a first bottom filling material portion 122. In this way, Figure 3A and Figure 3B The semiconductor package 300 of the embodiment can alleviate the problems that may otherwise occur in the semiconductor die (the first semiconductor die 104, the second semiconductor die 106), the interposer 108, and the first underfill material portion 122 (ie, Figures 1A to 2Cbetween the semiconductor packages 100 and 200) (for example, see Figure 2C ) cracking and other mechanical deformation / deterioration.

[0125] However, if Figure 3B As shown, in some embodiments, mechanical deformation / degradation may still occur between the multi-die chip 302 and the package substrate 110. In this regard, in embodiments where the semiconductor package 300 is large enough, cracks 210, delamination, and other mechanical deformations may form in the second underfill material portion 128, the plurality of metal bumps 124, etc. Furthermore, in embodiments where, for example, Figure 3A and Figure 3B In large semiconductor packages such as the semiconductor package 300 of FIG. 1 , it may be difficult to remove flux 308 residues used in a reflow operation to reflow the plurality of metal bumps 124 to attach the multi-die chip 302 to the package substrate. As such, the flux cleaning operation may not be completely effective and, therefore, various portions of flux 308 residues may be left behind. Similarly, in large semiconductor packages, due to limited capillary flow, the process of forming the second bottom fill material portion 128 may not be completely effective and, therefore, various voids 310 may be left in the second bottom fill material portion 128. Various disclosed embodiments may include hybrid bottom fill structures that may mitigate issues associated with crack 210, void 310, and flux 308 residue formation between the multi-die chip 302 and the package substrate 110, as described below with reference to FIG. Figure 4A and Figure 4B Describe in more detail.

[0126] Figure 4A FIG. 4 is a vertical cross-sectional view of another semiconductor package 400 a including a multi-die chip 302 and a hybrid underfill structure according to various embodiments. Figure 4B According to various embodiments, the multi-die chip 302 is removed. Figure 4A A top view of a semiconductor package showing the details of the hybrid underfill structure. Figure 4A The vertical plane of the cross-sectional diagram is similar to the above reference Figure 3A and Figure 3B The semiconductor package 300 is described in the context of Figure 3A The cross section B-B'. Figure 4A As shown, the semiconductor package 400a may include a package substrate 110 and a multi-die chip 302 attached to the package substrate 110. The multi-die chip 302 may be formed in a fan-out wafer level packaging process, as described above with reference to Figure 3A and Figure 3B describe.

[0127] like Figure 4A and Figure 4BAs shown, the hybrid bottom filling structure may include a non-conductive film 402 formed in a first region between the multi-die chip 302 and the package substrate 110 and a capillary bottom filling material (e.g., a second bottom filling material portion 128) formed in a second region between the multi-die chip 302 and the package substrate 110. Each of the non-conductive film 402 and the second bottom filling material portion 128 may be a thermosetting polymer-based material and may or may not include a filling material (e.g., silicon dioxide or glass filler). Figure 4B As shown, in a plan view, the second region (containing the second bottom filling material portion 128) may surround the first region (containing the non-conductive film 402). Figure 4A and Figure 4B As shown, the first area containing the non-conductive film 402 may have a first width 404, and the second area containing the second bottom filling material portion 128 may have a second width 406. As shown, the first width 404 may be smaller than the second width 406. In some embodiments, the second width 406 may be at least 20% larger than the first width 404. For example, the second width 406 may be 10% to 100% larger than the first width 404. In further embodiments, the second bottom filling material portion 128 may have a second area that is at least 50% larger than the non-conductive film 402. For example, the second bottom filling material portion 128 may have a second area that is 25% to 300% larger than the non-conductive film 402.

[0128] In some embodiments, the multi-die chip 302 may include a chip width 408 that is smaller than the second width 406. Figure 4A In some embodiments, the chip width 408 may be greater than or equal to 50 mm (but less than 75 mm), and the package substrate 110 may have a package width 409 greater than or equal to 72 mm (but less than 108 mm). Figure 4A As shown, the semiconductor package 400a may further include a first spacing distance 410 between the bottom surface of the multi-die chip 302 and the upper surface 126 of the package substrate 110 and a second spacing distance 412 between the top surface of the multi-die chip 302 and the upper surface 126 of the package substrate 110. The second bottom fill material portion 128 may include an underfill fillet 414 that contacts and extends laterally beyond the side of the multi-die chip 302 and contacts a portion of the upper surface 126 of the package substrate 110. Figure 4A As shown, the underfill fillet 414 may include a fillet height 416 greater than the first standoff distance 410 and less than the second standoff distance 412. The multi-die chip 302 may include the conductive chip bond structures 306 having a pitch 420 less than or equal to 300 μm.

[0129] In various embodiments, the second bottom fill material portion 128 may have a first modulus greater than 10 GPa at 25°C, and the non-conductive film 402 may include a second modulus less than 10 GPa at 25°C. For example, the modulus of the non-conductive film 402 may be in the range of 5 GPa to 9 GPa. The relationship between the modulus of the second bottom fill material portion 128 and the modulus of the non-conductive film 402 (i.e., the second bottom fill material portion 128 has a larger modulus than the non-conductive film 402) may provide improved reliability in terms of reducing mechanical deformation / damage caused by thermal cycling. In some embodiments, the non-conductive film 402 may have a first glass transition temperature (glass temperature), and the second bottom fill material portion 128 may have a second glass transition temperature, such that the first glass transition temperature and the second glass transition temperature are both greater than 100°C. In some embodiments, the non-conductive film 402 may have a first thermal expansion coefficient greater than about 20 ppm / °C at less than the first glass transition temperature, and the second bottom fill material portion 128 may have a second thermal expansion coefficient greater than about 20 ppm / °C at less than the second glass transition temperature.

[0130] Figure 4C FIG. 4 is a vertical cross-sectional view of another semiconductor package 400c including a hybrid bottom fill structure according to various embodiments. In this embodiment, the conductive die bonding structure 422 may have a size and spacing (i.e., spacing 420) comparable to the conductive bonding pad 130. In these embodiments, the interposer 108 ( Figures 1A to 2C ) and the redistribution layer 304 (eg Figure 3B and Figure 4A ), and the semiconductor die (first semiconductor die 104, second semiconductor die 106) can be directly connected to the package substrate 110. In this regard, the semiconductor package 400c can include the package substrate 110, the first semiconductor die 104 electrically and mechanically coupled to the package substrate 110, and the second semiconductor die 106 electrically and mechanically coupled to the package substrate 110. FIG. 3A to FIG. 4B In the embodiment (semiconductor package 300, 400a), the hybrid bottom filling structure may include a non-conductive film 402 formed between the first semiconductor die 104 and the package substrate 110 and a second bottom filling material portion 128 formed between the second semiconductor die 106 and the package substrate 110. Figure 4B and Figure 4C As shown, the non-conductive film 402 may be formed in a first region above the upper surface 126 of the package substrate 110, and the second bottom filling material portion 128 may be formed in a second region above the upper surface 126 of the package substrate 110, so that in a plan view, the second region surrounds the first region (see Figure 4B ).

[0131] like Figure 4C As shown, the semiconductor package 400c may include one or more additional second semiconductor dies 106 (eg, Figure 4C The second bottom filling material portion 128 is disposed between one or more additional second semiconductor dies 106 and the package substrate 110. Figure 4C As shown, the non-conductive film 402 may have a first width 404, and the second bottom fill material portion 128 may have a second width 406, such that the second width 406 is at least 20% larger than the first width 404. For example, the second width 406 may be 10% to 100% larger than the first width 404. The non-conductive film 402 may have a first area, and the second bottom fill material portion 128 may include a second area, such that the second area is at least 50% larger than the first area. In some embodiments, the semiconductor package 400c may further include a molding compound that partially surrounds the first semiconductor die 104 and the second semiconductor die 106 (or multiple second semiconductor dies 106) to form a multi-die epoxy molding compound frame 202, so that a multi-die chip 302 that may include the first semiconductor die 104, the second semiconductor die 106, and the multi-die epoxy molding compound frame 202 is formed, as shown. Figure 4C shown.

[0132] like Figure 4C As shown, the multi-die chip 302 may have a chip width 408 that is smaller than the second width 406. The semiconductor package 400c may further include a first separation distance 410 between a bottom surface of the multi-die chip 302 and an upper surface 126 of the package substrate 110 and a second separation distance 412 between a top surface of the multi-die chip 302 and the upper surface 126 of the package substrate 110. Figure 4A and Figure 4B As shown in the embodiment of the semiconductor package 400a, the second underfill material portion 128 may include an underfill fillet 414 that contacts and extends laterally beyond the side of the multi-die chip 302 and contacts a portion of the upper surface 126 of the package substrate 110. Figure 4C As shown, the underfill fillet 414 may include a fillet height 416 that is greater than the first standoff distance 410 and less than the second standoff distance 412 .

[0133] FIG. 5A to FIG. 5H Schematic diagrams of vertical cross-sections of intermediate structures 500 a to 500 h that may be used to form semiconductor packages 400 a and 400 c according to various embodiments. Figure 5AThe intermediate structure 500a may include a package substrate 110 having a conductive bonding pad 130. The conductive bonding pad 130 may be electrically connected to an electrical interconnect structure (not shown) in the package substrate 110. The conductive bonding pad 130 may have a pad diameter 419 between 90 μm and 120 μm and a pitch 420 between 295 μm and 305 μm. The package substrate 110 may further include a plurality of metal bumps 124. For example, the plurality of metal bumps 124 may include a soldering portion formed above the conductive bonding pad 130. In this regard, the conductive bonding pad 130 and the plurality of metal bumps 124 may be configured to be used to connect a multi-die chip 302 (e.g., see Figure 5D ) is bonded to the C4 bonding structure of the package substrate 110, as shown below with reference to Figure 5E More detailed description. In other embodiments, the package substrate may include a C2 bonding pillar structure (not shown). According to various embodiments, the conductive bonding pad 130 and the plurality of metal bumps 124 may have a bump height 424 between 90 μm and 300 μm. The above dimensions are provided as examples only, and in other embodiments, various other dimensions may be provided.

[0134] Figure 5B FIG. 5 is a vertical cross-sectional view of another intermediate structure 500 b that can be used to form the semiconductor packages 400 a and 400 c according to various embodiments. Figure 5A The intermediate structure 500a is formed by forming a non-conductive film 402 over a portion of the upper surface 126 of the package substrate 110. The non-conductive film 402 may be provided by using a thin film dispensing device 502 (not drawn to scale). The non-conductive film 402 may be a polymer-based material that may or may not contain a filler material. In this regard, the non-conductive film 402 may be heat-curable by raising the non-conductive film 402 to an elevated temperature for a period of time. In various embodiments, the non-conductive film 402 may be a mixture of epoxy resin, curing agent, filler, additive, and flux material. For example, according to one embodiment, the non-conductive film 402 may be an epoxy-based thermosetting material containing nano-scale filler particles. Various other filling materials may be used in other embodiments. The non-conductive film 402 may have an initial film height 426 that may be greater than the bump height 424. For example, in some embodiments, the initial film height 426 may be at least 10 μm greater than the bump height 424.

[0135] Figure 5CSchematic diagram of a vertical cross-section of another intermediate structure 500c that can be used to form semiconductor packages 400a, 400c according to various embodiments. The intermediate structure 500c can be formed by the intermediate structure 500b by forming a layer of flux 308 around the non-conductive film 402 in the second region. As shown, the flux dispensing device 504 can provide the flux 308 in liquid form, and the flux 308 can flow around the bonding structure (metal bump 124, conductive bonding pad 130) in the second region. The presence of the flux 308 can remove the oxide film on the surface of the plurality of metal bumps 124 (e.g., solder bumps), and can increase the wetting ability of the plurality of metal bumps 124, thereby forming a metallurgical bond in a subsequent thermal compression bonding operation, as described below. Figure 5E Describe in more detail.

[0136] Figure 5D 2 is a schematic vertical cross-sectional view of another intermediate structure 500d that can be used to form semiconductor packages 400a, 400c according to various embodiments. In this regard, the multi-die chip 302 can be disposed above the intermediate structure 500c to form the intermediate structure 500d. As described above, the multi-die chip 302 can include a first semiconductor die 104 and one or more second semiconductor die 106. The first semiconductor die 104 and the one or more second semiconductor die 106 can be embedded in the multi-die epoxy resin molding compound frame 202, and one or more redistribution layers 304 can be formed above the first semiconductor die 104 and the one or more second semiconductor die 106. In this regard, the multi-die chip 302 can be formed by the fan-out wafer level packaging process described above. The multi-die chip 302 can also include a conductive chip bonding structure 306 that can be electrically connected to the interconnect structure formed in the one or more redistribution layers 304. The multi-die chip 302 may be arranged such that the conductive chip bonding structure 306 is aligned with the corresponding plurality of metal bumps 124 formed on the package substrate 110. In a subsequent bonding operation, the multi-die chip 302 may be arranged such that the conductive chip bonding structure 306 directly contacts the plurality of metal bumps 124. Next, a thermocompression bonding operation may be performed to electrically and mechanically bond the multi-die chip 302 to the package substrate 110, as described below with reference to Figure 5E Describe in more detail.

[0137] Figure 5E FIG. 5 is a schematic vertical cross-sectional view of another intermediate structure 500 e that may be used to form the semiconductor packages 400 a and 400 c according to various embodiments. Figure 5E The intermediate structure 500e can be composed of Figure 5DThe intermediate structure 500d is formed by performing a thermocompression bonding operation on the intermediate structure 500d. In this regard, the thermocompression bonding head 506 may contact the multi-crystal chip 302 that has been positioned above the package substrate 110. The thermocompression bonding head 506 may provide thermal energy to the multi-crystal chip 302 and may introduce a compressive force. For example, the thermocompression bonding head 506 may provide thermal energy to increase the temperature of the intermediate structure 500e to a range between 230°C and 400°C. The thermocompression bonding head 506 may also apply a force in the range of 0.1N to 30N to the multi-crystal chip 302. The temperature may be raised to above the melting point of the plurality of metal bumps 124 to melt the plurality of metal bumps 124. The intermediate structure 500e may be maintained at the elevated temperature for a certain period of time. For example, the elevated temperature may be maintained for 60 seconds or less. Then, the plurality of metal bumps 124 may resolidify when cooled, thereby forming a metallurgical bond between the multi-crystal chip 302 and the package substrate 110. After completing the thermocompression bonding operation, the non-conductive film 402 may have a thickness from 60 μm to 90 μm.

[0138] Fig. 5F FIG. 5 is a vertical cross-sectional view of another intermediate structure 500 f that may be used to form the semiconductor packages 400 a and 400 c according to various embodiments. Fig. 5F The intermediate structure 500f can be composed of Figure 5E The intermediate structure 500e is removed by removing the thermocompression bonding head 506 and by performing a flux cleaning operation to remove the flux surrounding the second area of ​​the non-conductive film 402 (see, for example, Figure 5E ) to form. In this regard, the intermediate structure 500f can maintain a temperature in a range between 70°C and 90°C, and a solvent can be introduced to remove the flux 308. Various solvents can be used depending on the chemical composition of the flux 308. For example, when an epoxy-based flux 308 is used, chlorofluorocarbons can be used to decompose and remove the remaining flux 308. Alternatively, a water-based flux 308 can be cleaned with various types of cleaning solutions. In some embodiments, a no-clean flux 308 that does not require cleaning can be used.

[0139] Figure 5G FIG. 5 is a schematic vertical cross-sectional view of another intermediate structure 500 g that may be used to form semiconductor packages 400 a and 400 c according to various embodiments. Figure 5G The intermediate structure 500g can be made of Fig. 5FThe intermediate structure 500f is formed by introducing the second bottom filling material portion 128 into the space surrounding the non-conductive film 402. In this regard, the intermediate structure 500g and the capillary bottom filling material dispenser 508 can maintain a temperature in the range between 70°C and 90°C while dispensing the second bottom filling material portion 128 in liquid form. The second bottom filling material portion 128 can be a mixture of epoxy resin, curing agent, one or more additives and / or filling materials. The second bottom filling material portion 128 can be introduced into the space between the multi-die chip 302 and the packaging substrate 110 by capillary force. Then, when the second bottom filling material portion 128 is heat-treated, the second bottom filling material portion 128 can be cured, as described below with reference to FIG. Figure 5H Describe in more detail.

[0140] Figure 5H FIG. 5 is a vertical cross-sectional view of another intermediate structure 500 h that may be used to form the semiconductor packages 400 a and 400 c according to various embodiments. Figure 5H The intermediate structure 500h can be Figure 5G The intermediate structure 500g is formed by heat treating the non-conductive film 402 and the second bottom filling material portion 128. For example, the intermediate structure 500h can be heated to a temperature in the range between 130°C and 170°C and for a duration between 60 minutes and 120 minutes. The heat treatment can further lead to the solidification of the non-conductive film 402 and the second bottom filling material portion 128. After cooling, the solidified second bottom filling material portion 128 can have a modulus greater than 10GPa at 25°C, and the non-conductive film 402 can have a modulus less than 10GPa at 25°C. The relatively large modulus of the second bottom filling material portion 128 can strengthen the bonding structure near the outer edges and corners of the multi-crystalline chip 302, while the relatively small modulus of the non-conductive film 402 can allow a certain degree of elastic deformation to reduce stress / strain caused by thermal expansion. Next, Figure 4A The semiconductor package 400a may be composed of Figure 5H The intermediate structure 500h is formed by attaching the external reinforcement structure 204 to the upper surface 126 of the package substrate 110. In other embodiments, Figure 4C The semiconductor package 400c can be similar to the reference FIG. 5A to FIG. 5H The above processing operations are used to form, except that one or more redistribution layers 304 are not included (for example, please refer to Figure 4A ) of the multi-die chip 302.

[0141] Figure 6A flowchart showing various operations of a method 600 for forming a semiconductor package 400a, 400c according to various embodiments. At operation 602, the method 600 may include forming a non-conductive film 402 (eg, see FIG. 4 ) over a first region of the package substrate 110. Figure 4B ). At operation 604, the method 600 may include attaching the first semiconductor die 104 to the package substrate 110 over the first region such that the non-conductive film 402 is disposed between the package substrate 110 and the first semiconductor die 104. At operation 606, the method 600 may include attaching the second semiconductor die 106 to the second region of the package substrate 110 (e.g., see Figure 4B At operation 608 , the method 600 may include forming a capillary underfill material (a second underfill material portion 128 ) between the second semiconductor die 106 and the package substrate 110 .

[0142] According to the method 600, the operation 604 of attaching the first semiconductor die 104 to the package substrate 110 and the operation 606 of attaching the second semiconductor die 106 to the package substrate 110 may further include disposing the first semiconductor die 104 above the first region of the package substrate 110, disposing the second semiconductor die 106 above the second region of the package substrate 110, and performing a thermocompression bonding process to electrically and mechanically couple the first semiconductor die 104 and the second semiconductor die 106 to the package substrate 110. According to the method 600, the operation 606 of attaching the second semiconductor die 106 to the second region of the package substrate 110 may further include performing a reference Figure 5E Prior to the described thermocompression bonding process, flux 308 is dispensed over the electrical bonding structures (metal bumps 124 , conductive bonding pads 130 ) located in the second region of the package substrate 110 .

[0143] The method 600 may further include performing a flux 308 cleaning operation after performing the thermocompression bonding process and before forming the second underfill material portion 128 between the second semiconductor die 106 and the package substrate 110. The method 600 may further include forming the first semiconductor die 104 and the second semiconductor die 106 as a multi-die chip 302, the multi-die chip 302 including a chip width 408 greater than or equal to 50 mm, and forming the conductive chip bonding structure 306 with a pitch 420 less than or equal to 300 μm. The method 600 may further include attaching the multi-die chip 302 to the package substrate 110, the package substrate 110 may have a package width 409 greater than or equal to 72 mm. The method 600 may further include forming the second underfill material portion 128 in the second region to have a second width 406 that is at least 20% greater than the first width 404 of the non-conductive film 402 in the first region. The method 600 may further include forming the second underfill material portion 128 in the second region to have a second area that is at least 50% larger than the first area of ​​the non-conductive film 402 in the first region.

[0144] With reference to all the drawings and according to various embodiments of the present invention, semiconductor packages 400a and 400c are provided. The semiconductor packages 400a and 400c may include a packaging substrate 110; a first semiconductor die 104 electrically and mechanically coupled to the packaging substrate 110; a second semiconductor die 106 electrically and mechanically coupled to the packaging substrate 110; a non-conductive film 402 formed between the first semiconductor die 104 and the packaging substrate 110; and a capillary bottom filling material (a second bottom filling material portion 128) formed between the second semiconductor die 106 and the packaging substrate 110. In some embodiments, the non-conductive film 402 may be formed in a first region above the upper surface 126 of the packaging substrate 110, and the capillary bottom filling material (the second bottom filling material portion 128) may be formed in a second region above the upper surface 126 of the packaging substrate 110 (for example, please refer to Figure 4B ). In germanium, in various embodiments, in a plan view, the second region may surround the first region.

[0145] In various embodiments, the semiconductor package 400a, 400c may further include one or more additional second semiconductor dies 106 located in the second region, such that the capillary underfill material (second underfill material portion 128) is disposed between the one or more additional second semiconductor dies 106 and the package substrate 110. In some embodiments, the capillary underfill material (second underfill material portion 128) may have a first modulus greater than 10 GPa at 25°C, and the non-conductive film 402 may have a second modulus less than 10 GPa at 25°C. In some embodiments, the non-conductive film 402 may have a first glass transition temperature, and the capillary underfill material (second underfill material portion 128) may have a second glass transition temperature, such that both the first glass transition temperature and the second glass transition temperature are greater than 100°C.

[0146] In various embodiments, the non-conductive film 402 may have a first coefficient of thermal expansion greater than 20 ppm / ° C. at less than the first glass transition temperature, and the capillary underfill material (second underfill material portion 128) may have a second coefficient of thermal expansion greater than about 20 ppm / ° C. at less than the second glass transition temperature. In some embodiments, the non-conductive film may have a first width 404, and the capillary underfill material (second underfill material portion 128) may have a second width 406, such that the second width 406 is at least 20% greater than the first width 404. Similarly, the non-conductive film 402 may have a first area, and the capillary underfill material (second underfill material portion 128) may have a second area, such that the second area is at least 50% greater than the first area. In some embodiments, the semiconductor packages 400a and 400c may further include a molding compound that partially surrounds the first semiconductor die 104 and the second semiconductor die 106 to form a multi-die frame (multi-die epoxy molding compound frame 202), so as to form a multi-die chip 302 that may include the first semiconductor die 104, the second semiconductor die 106, and the multi-die frame (multi-die epoxy molding compound frame 202). The multi-die chip 302 may have a chip width 408 that is smaller than the second width 406 (for example, see Figure 4A and Figure 4C ).

[0147] In various embodiments, the semiconductor packages 400a, 400c may further have a first standoff distance 410 between the bottom surface of the multi-die chip 302 and the upper surface 126 of the package substrate 110 and a second standoff distance 412 between the top surface of the multi-die chip 302 and the upper surface 126 of the package substrate 110. In some embodiments, the capillary underfill material (the second underfill material portion 128) may further include an underfill fillet 414 that contacts and extends laterally beyond the side of the multi-die chip 302 and contacts a portion of the upper surface 126 of the package substrate 110. In these embodiments, the underfill fillet 414 may have a fillet height 416 that is greater than the first standoff distance 410 and less than the second standoff distance 412.

[0148] According to another embodiment, a semiconductor package 400a, 400c is provided. The semiconductor package 400a, 400c may include a package substrate 110; a multi-die chip 302 attached to the package substrate 110; a non-conductive film 402 formed in a first region between the multi-die chip 302 and the package substrate 110; and a capillary underfill material (a second underfill material portion 128) formed in a second region between the multi-die chip 302 and the package substrate 110. In various embodiments, in a plan view, the capillary underfill material (the second underfill material portion 128) may surround the first region (e.g., see FIG. 1 ). Figure 4B ), the capillary bottom filling material (the second bottom filling material portion 128) may have a second width 406 that is at least 20% larger than the first width 404 of the non-conductive film 402, and the capillary bottom filling material (the second bottom filling material portion 128) may have a second area that is at least 50% larger than the first area of ​​the non-conductive film 402.

[0149] In some embodiments, the multi-die chip 302 may have a chip width 408 that is less than the second width 406. The semiconductor packages 400a, 400c may also have a first standoff distance 410 between a bottom surface of the multi-die chip 302 and an upper surface 126 of the package substrate 110 and a second standoff distance 412 between a top surface of the multi-die chip 302 and an upper surface 126 of the package substrate 110. Furthermore, the capillary underfill material (the second underfill material portion 128) may include an underfill fillet 414 that contacts and extends laterally beyond the side of the multi-die chip 302 and contacts a portion of the upper surface 126 of the package substrate 110. In these embodiments, the underfill fillet 414 may have a fillet height 416 that is greater than the first standoff distance 410 and less than the second standoff distance 412. In some embodiments, the chip width 408 may be greater than or equal to 50 mm, the multi-grain chip 302 may include a conductive bonding structure (conductive chip bonding structure 306, conductive grain bonding structure 422), the conductive bonding structure (conductive chip bonding structure 306, conductive grain bonding structure 422) has a spacing 420 less than or equal to 300 μm, and the packaging substrate 110 has a packaging width 409 greater than or equal to 72 mm.

[0150] According to another embodiment, a method for forming a semiconductor package is provided, the method comprising forming a non-conductive film over a first region of a package substrate; attaching a first semiconductor die to the package substrate over the first region so that the non-conductive film is disposed between the package substrate and the first semiconductor die; attaching a second semiconductor die to a second region of the package substrate; and forming a capillary underfill material between the second semiconductor die and the package substrate. In other embodiments, the step of attaching the first semiconductor die and the second semiconductor die to the package substrate further comprises: placing the first semiconductor die over the first region of the package substrate; placing the second semiconductor die over the second region of the package substrate; and performing a thermocompression bonding process to electrically and mechanically couple the first semiconductor die and the second semiconductor die to the package substrate. In other embodiments, the step of attaching the second semiconductor die to the second region of the package substrate further comprises: dispensing flux over an electrical bonding structure located in the second region of the package substrate before performing the thermocompression bonding process; and performing a flux cleaning operation after the thermocompression bonding process and before forming the capillary underfill material between the second semiconductor die and the package substrate. In other embodiments, the method further includes forming the first semiconductor die and the second semiconductor die as a multi-die chip, the multi-die chip including a chip width greater than or equal to 50 mm and a chip bonding structure including a pitch less than or equal to 300 μm; and attaching the multi-die chip to a package substrate, the package substrate having a package width greater than or equal to 72 mm. In other embodiments, the method further includes forming a capillary bottom fill material in the second region to have a second width that is at least 20% greater than the first width of the non-conductive film in the first region; and forming a capillary bottom fill material in the second region to have a second area that is at least 50% greater than the first area of ​​the non-conductive film in the first region.

[0151] Various embodiments disclosed herein may provide improved methods for assembling semiconductor packages 400a, 400c that may mitigate mechanical issues associated with thermal expansion mismatches between package components that may otherwise result in warping, cracking, delamination, etc. In this regard, embodiments of the present invention provide a hybrid underfill structure that includes a non-conductive film 402 in a central region between a semiconductor die (a first semiconductor die 104, a second semiconductor die 106, a multi-die chip 302) and a package substrate 110 and a capillary underfill material (a second underfill material portion 128) surrounding the non-conductive film 402 in a plan view. The non-conductive film 402 may be placed on the upper surface 126 of the package substrate 110 before the semiconductor die (a first semiconductor die 104, a second semiconductor die 106, a multi-die chip 302) is attached to the package substrate 110. Having the non-conductive film 402 in the central region may reduce the volume of the surrounding region occupied by the capillary underfill material (the second underfill material portion 128). Therefore, the capillary flow distance can be reduced, so that the flux 308 residue is cleaned more effectively and the capillary bottom filling material (second bottom filling material portion 128) is set more effectively. In this way, the flux 308 residue and the void 310 between the semiconductor die (first semiconductor die 104, second semiconductor die 106) (or multi-die chip 302) and the package substrate 110 can be reduced or eliminated, and the device performance is improved by enhancing the protection of the conductive bonding structure (conductive bonding pad 130, conductive chip bonding structure 306, conductive die bonding structure 422).

[0152] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the utility model from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the utility model, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the embodiments of the utility model. Various changes, substitutions or modifications can be made to the embodiments of the utility model without departing from the spirit and scope of the embodiments of the utility model.

Claims

1. A semiconductor package, characterized in that: include: a packaging substrate; A first semiconductor die electrically and mechanically coupled to the package substrate; a second semiconductor die electrically and mechanically coupled to the package substrate; a non-conductive film formed between the first semiconductor die and the package substrate; and A capillary bottom filling material is formed between the second semiconductor die and the package substrate.

2. The semiconductor package according to claim 1, wherein: The non-conductive film is formed in a first region above a surface of the package substrate, and the capillary bottom filling material is formed in a second region above the surface of the package substrate, and in a plan view, the second region surrounds the first region.

3. The semiconductor package according to claim 2, wherein: Also included is one or more additional second semiconductor dies located in the second region, such that the capillary underfill material is disposed between the one or more additional second semiconductor dies and the package substrate.

4. The semiconductor package according to claim 2, wherein: The non-conductive film comprises a first width, and the capillary bottom filling material comprises a second width, and the second width is at least 20% greater than the first width.

5. The semiconductor package according to claim 2, wherein: The non-conductive film includes a first area, and the capillary bottom filling material includes a second area, and the second area is at least 50% larger than the first area.

6. The semiconductor package according to any one of claims 1 to 5, wherein: The invention also includes a molding compound partially surrounding the first semiconductor die and the second semiconductor die to form a multi-die frame, so as to form a multi-die chip including the first semiconductor die, the second semiconductor die and the multi-die frame.

7. The semiconductor package according to claim 6, wherein: The multi-die chip includes a chip width that is smaller than the second width.

8. The semiconductor package according to claim 7, wherein: in: The semiconductor package further includes a first separation distance between a bottom surface of the multi-die chip and the surface of the package substrate and a second separation distance between a top surface of the multi-die chip and the surface of the package substrate; The capillary underfill material includes an underfill fillet that contacts and extends laterally beyond a side of the multi-die chip and contacts a portion of the surface of the package substrate; and The underfill fillet includes a fillet height that is greater than the first standoff distance and less than the second standoff distance.

9. A semiconductor package, characterized in that: include: a packaging substrate; a multi-die chip attached to the package substrate; A non-conductive film is formed in a first region between the multi-die chip and the package substrate; as well as A capillary bottom filling material is formed in a second region between the multi-die chip and the package substrate.

10. The semiconductor package according to claim 9, wherein: In a plan view, the capillary bottom filling material surrounds the first area, the capillary bottom filling material includes a second width that is at least 20% larger than a first width of the non-conductive film, and the capillary bottom filling material includes a second area that is at least 50% larger than a first area of ​​the non-conductive film.

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