A high linearity and low power consumption control circuit

Abstract

The utility model relates to the technical field of low-power control circuits, and specifically discloses a high-linearity low-power control circuit, including: a PMOS control circuit, including a plurality of parallel PMOS paths, each PMOS path including a working PMOS tube, some or all of the PMOS paths also including a series switch and a parallel switch, and the working PMOS tubes of some or all of the PMOS paths form a series-parallel structure with the series switch and the parallel switch; an NMOS control circuit, including a plurality of parallel NMOS paths, each NMOS path including a working NMOS tube, some or all of the NMOS paths also including a series switch and a parallel switch, and some or all of the working NMOS tubes form a series-parallel structure with the series switch and the parallel switch. The utility model realizes a low-power configuration and improves the linearity performance of the circuit by forming a series-parallel structure with the working PMOS tube, the working NMOS tube and the switch.

Description

Technical Field

[0001] The utility model relates to the technical field of low power consumption control circuits, in particular to a high linearity low power consumption control circuit. Background Art

[0002] The traditional way to implement low-power control circuits is to add switches to the gate signal path of the transistor, such as Figure 1 Switches SW1_PM2 and SW1_NM2 in.

[0003] For the PMOS low power control implementation, in low power mode, SW1_PM2 is disconnected, and SW2_PM2 is used to connect to VDD when SW1_PM2 is disconnected to turn off PM2. In normal working mode, switch SW1_PM2 is closed, SW2_PM2 is disconnected, and PM2 works normally.

[0004] For the NMOS low power control implementation, in low power mode, SW1_NM2 is disconnected, and SW2_NM2 is used to connect to GND when SW1_NM2 is disconnected to turn off NM2. In normal working mode, switch SW1_NM2 is closed, SW2_NM2 is disconnected, and NM2 works normally.

[0005] The problem with this implementation is that for the PMOS low-power control implementation, since the switch SW1_PM2 is located on the signal path from VINP to the PM2 gate; the switch SW1_PM2 itself is nonlinear, and the signal swing of VINP is relatively large, resulting in relatively large nonlinear energy of SW1_PM2, which will cause the THD performance of the module using this device to deteriorate.

[0006] For the NMOS low-power control implementation, since the switch SW1_NM2 is located on the signal path from VINN to the NM2 gate, the switch SW1_NM2 itself is nonlinear, and the signal swing of VINN is relatively large, resulting in relatively large nonlinear energy of SW1_NM2, which will cause the THD performance of the module using this device to deteriorate.

[0007] Based on this technical background, the utility model studies a high linearity and low power consumption control circuit. Utility Model Content

[0008] In view of the shortcomings of the prior art, the utility model proposes a high-linearity and low-power consumption control circuit. The circuit improves the linearity performance of the circuit unit in each mode when realizing a configurable low-power consumption mode by connecting a working PMOS tube and a series switch into a series structure, connecting two ends of the parallel switch in parallel with the source and drain of the working PMOS tube to form a parallel structure, connecting a working NMOS tube and the series switch into a series structure, and connecting two ends of the parallel switch in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0009] In order to achieve the above object, the utility model provides a high linearity and low power consumption control circuit, comprising:

[0010] A PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel, each of which includes a working PMOS tube, and some or all of the PMOS paths also include a series switch and a parallel switch, wherein the working PMOS tube of the PMOS path including the series switch and the parallel switch is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0011] The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube. Some or all of the NMOS paths also include a series switch and a parallel switch. The working NMOS tube of the NMOS path including the series switch and the parallel switch is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure.

[0012] The beneficial effects of the utility model include:

[0013] (1) The high linearity and low power consumption control circuit proposed in the utility model improves the linearity performance of the circuit unit in each mode when realizing a configurable low power consumption mode by connecting a working PMOS tube and a series switch into a series structure, connecting the two ends of the parallel switch in parallel with the source and drain of the working PMOS tube to form a parallel structure, connecting the working NMOS tube and the series switch into a series structure, and connecting the two ends of the parallel switch in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0014] (2) The high-linearity, low-power control circuit proposed in the utility model selects working NMOS tubes or PMOS path combinations of different sizes of the corresponding NMOS paths or PMOS paths through the coordination of the series switches and parallel switches in each NMOS path or PMOS path, thereby providing a high-linearity, high-precision NMOS source current for the analog circuit.

[0015] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present invention.

[0017] Figure 1 It is a circuit structure diagram of an existing control circuit.

[0018] Figure 2 The present invention is a schematic diagram of a circuit structure of a specific implementation of the high linearity and low power consumption control circuit proposed by the present invention.

[0019] Figure 3 This is a circuit structure schematic diagram of another specific implementation of the high linearity and low power consumption control circuit proposed by the utility model.

[0020] Figure 4 This is a circuit structure diagram of a third specific implementation of the high linearity and low power consumption control circuit proposed by the utility model.

[0021] Figure 5 This is a circuit structure diagram of a fourth specific implementation mode of the high linearity and low power consumption control circuit proposed by the utility model.

[0022] Figure 6 This is a circuit structure diagram of the fifth specific implementation mode of the high linearity and low power consumption control circuit proposed by the utility model.

[0023] Figure 7 This is a circuit structure diagram of a sixth specific implementation manner of the high linearity and low power consumption control circuit proposed by the utility model.

[0024] Figure 8 This is a circuit structure diagram of the seventh specific implementation mode of the high linearity and low power consumption control circuit proposed by the utility model.

[0025] Fig. 9 This is a circuit structure diagram of the eighth specific implementation mode of the high linearity and low power consumption control circuit proposed by the utility model.

[0026] Fig.10 The present invention provides a schematic structural diagram of a PMOS switch, an NMOS switch and a CMOS switch used in series switches and parallel switches in a high linearity and low power consumption control circuit proposed by the utility model.

[0027] Description of reference numerals:

[0028] PM1, PM2... multiple working PMOS tubes in PMN-PMOS control circuit, NM1, NM2... multiple working NMOS tubes in NMN-NMOS control circuit, SW1_PM1, SW1_PM2... multiple series switches in SW1_PMN-PMOS control circuit, SW2_PM1, SW2_PM2... multiple parallel switches in SW2_PMN-PMOS control circuit, SW1_NM1, SW1_NM2... multiple series switches in SW1_NMN-NMOS control circuit, SW2_NM1, SW2_NM2... multiple parallel switches in SW2_NMN-NMOS control circuit;

[0029] VINP-PMOS input, VINN-NMOS input, OUT1, OUT2-output of PMOS control circuit or NMOS control circuit, VDD-power supply, GND-ground. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein.

[0031] In the present utility model, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present utility model, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0032] The utility model provides a high linearity and low power consumption control circuit, as shown in FIG. Figure 2-10 As shown, including:

[0033] A PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel, each of which includes a working PMOS tube, and some or all of the PMOS paths also include a series switch and a parallel switch, wherein the working PMOS tube of the PMOS path including the series switch and the parallel switch is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0034] The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube. Some or all of the NMOS paths also include a series switch and a parallel switch. The working NMOS tube of the NMOS path including the series switch and the parallel switch is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure.

[0035] In the utility model, by connecting the working PMOS tube and the series switch into a series structure, connecting the two ends of the parallel switch in parallel with the source and drain of the working PMOS tube to form a parallel structure, connecting the working NMOS tube and the series switch into a series structure, connecting the two ends of the parallel switch in parallel with the source and drain of the working NMOS tube to form a parallel structure, when realizing the configurable low power consumption mode, the linearity performance of the circuit unit in each mode is improved.

[0036] According to the utility model, the gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form a PMOS input terminal or an NMOS input terminal;

[0037] The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form an NMOS input terminal or a PMOS input terminal.

[0038] According to the utility model, when the gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form a PMOS input terminal,

[0039] The source of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the drain serves as the output end of the PMOS path in which it is located;

[0040] The series structure of the PMOS path including the series switch and the parallel switch is:

[0041] One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the source of the working PMOS tube, and the drain of the working PMOS tube serves as the output end of the PMOS path in which it is located, or,

[0042] The source of the working PMOS tube is electrically connected to the power supply, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located;

[0043] The output ends of the PMOS paths are electrically connected to each other to form the output end of the PMOS control circuit.

[0044] According to the utility model, when the gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form an NMOS input terminal,

[0045] The drain of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the source serves as the output end of the PMOS path;

[0046] The series structure of the PMOS path including the series switch and the parallel switch is:

[0047] One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the drain of the working PMOS tube, and the source of the working PMOS tube serves as the output end of the PMOS path in which it is located, or,

[0048] The drain of the working PMOS tube is electrically connected to the ground, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located;

[0049] The output ends of the PMOS paths are electrically connected to each other to form the output end of the NMOS control circuit.

[0050] Preferably, the sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values.

[0051] According to the utility model, when the gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form an NMOS input terminal,

[0052] The source of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the drain serves as the output end of the NMOS path in which it is located;

[0053] The series structure of the NMOS path including the series switch and the parallel switch is:

[0054] One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the source of the working NMOS tube, and the drain of the working NMOS tube serves as the output end of the NMOS path in which it is located, or,

[0055] The source of the working NMOS tube is electrically connected to the ground, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located;

[0056] The output ends of the NMOS paths are electrically connected to each other to form the output end of the NMOS control circuit.

[0057] According to the utility model, when the gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form a PMOS input terminal,

[0058] The drain of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the source serves as the output end of the NMOS path;

[0059] The series structure of the NMOS path including the series switch and the parallel switch is:

[0060] One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the drain of the working NMOS tube, and the source of the working NMOS tube serves as the output end of the NMOS path in which it is located, or,

[0061] The drain of the working NMOS tube is electrically connected to the power supply, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located;

[0062] The output ends of the NMOS paths are electrically connected to each other to form the output end of the PMOS control circuit.

[0063] Preferably, the sizes of the working NMOS tubes of each NMOS path are arranged in sequence according to the weight values.

[0064] According to the utility model, each series switch and parallel switch of a PMOS path including a series switch and a parallel switch are independently selected from a PMOS switch or a CMOS switch.

[0065] According to the utility model, each series switch and parallel switch of an NMOS path including a series switch and a parallel switch are independently selected from an NMOS switch or a CMOS switch.

[0066] In the present invention, the structures of the PMOS switch, the NMOS switch and the CMOS switch are as follows: Figure 6 shown.

[0067] In the utility model, by coordinating the on-off of the series switches and the parallel switches in each NMOS path or PMOS path, working NMOS tubes or PMOS path combinations of different sizes of the corresponding NMOS path or PMOS path are selected to provide a high-linearity and high-precision NMOS source current for the analog circuit.

[0068] In the utility model, Figure 2As shown, for the implementation of the PMOS control circuit, the positions of switches SW2_PM1, SW2_PM2, ... SW2_PMN are changed, such as connecting SW1_PM2 between the source end of the working PMOS tube PM2 and the power supply VDD. In low power mode, SW1_PM2 is disconnected and SW2_PM2 is closed; in normal working mode, SW1_PM2 is closed and SW2_PM2 is disconnected; for the implementation of the NMOS low control circuit, the positions of switches SW1_NM2, SW2_NM2, ... SW2_NMN are changed, such as connecting SW1_NM2 between the source end of the working NMOS tube NM2 and the ground GND. In low power mode, SW1_NM2 is disconnected and SW2_NM2 is closed; in normal working mode, SW1_NM2 is closed and SW2_NM2 is disconnected.

[0069] In the utility model, the PMOS control circuit and the NMOS control circuit can be used separately or in combination to achieve low power consumption control and ensure the performance in each working mode.

[0070] In the utility model, Figure 2-5 As shown, for the PMOS control circuit implementation, the series switch and the working PMOS tube can be swapped, and the purpose of power consumption mode switching and ensuring linearity performance in each mode can still be achieved; the control method is replaced, and for the NMOS control circuit implementation, the series switch and the working NMOS tube can be swapped, and the purpose of power consumption mode switching and ensuring linearity performance in each mode can still be achieved.

[0071] The present invention is described in more detail below through specific embodiments.

[0072] Example 1

[0073] like Figure 2 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0074] A PMOS control circuit includes two parallel PMOS paths, each PMOS path includes a working PMOS tube, one of the PMOS paths also includes a series switch and a parallel switch, the working PMOS tube of the PMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0075] The NMOS control circuit includes two parallel NMOS paths, each NMOS path includes a working NMOS tube, one of the NMOS paths also includes a series switch and a parallel switch, the working NMOS tube of the NMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0076] The gates of the working PMOS tubes of the two PMOS paths are electrically connected to each other to form a PMOS input terminal;

[0077] The gates of the working NMOS tubes of the two NMOS paths are electrically connected to each other to form an NMOS input terminal;

[0078] The source of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the drain serves as the output end of the PMOS path in which it is located;

[0079] The series structure of the PMOS path including the series switch and the parallel switch is:

[0080] One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the source of the working PMOS tube, and the drain of the working PMOS tube serves as the output end of the PMOS path in which it is located;

[0081] The output ends of the two PMOS paths are electrically connected to each other to form an output end of the PMOS control circuit;

[0082] In this embodiment, the sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values;

[0083] The source of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the drain serves as the output end of the NMOS path in which it is located;

[0084] The series structure of the NMOS path including the series switch and the parallel switch is:

[0085] One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the source of the working NMOS tube, and the drain of the working NMOS tube serves as the output end of the NMOS path in which it is located;

[0086] The output ends of the two NMOS paths are electrically connected to each other to form an output end of the NMOS control circuit;

[0087] In this embodiment, the sizes of the working NMOS tubes of the two NMOS paths are arranged in sequence according to the weight values;

[0088] The series switch and the parallel switch of the PMOS path including the series switch and the parallel switch are both CMOS switches;

[0089] The series switches and parallel switches of the NMOS paths including the series switches and the parallel switches are both CMOS switches.

[0090] Example 2

[0091] like Figure 3 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0092] A PMOS control circuit includes two parallel PMOS paths, each PMOS path includes a working PMOS tube, one of the PMOS paths also includes a series switch and a parallel switch, the working PMOS tube of the PMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0093] The NMOS control circuit includes two parallel NMOS paths, each NMOS path includes a working NMOS tube, one of the NMOS paths also includes a series switch and a parallel switch, the working NMOS tube of the NMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0094] The gates of the working PMOS tubes of the two PMOS paths are electrically connected to each other to form a PMOS input terminal;

[0095] The gates of the working NMOS tubes of the two NMOS paths are electrically connected to each other to form an NMOS input terminal;

[0096] The source of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the drain serves as the output end of the PMOS path in which it is located;

[0097] The series structure of the PMOS path including the series switch and the parallel switch is:

[0098] The source of the working PMOS tube is electrically connected to the power supply, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located;

[0099] The output ends of the two PMOS paths are electrically connected to each other to form an output end of the PMOS control circuit;

[0100] The sizes of the working PMOS tubes of the two PMOS paths are arranged in sequence according to the weight values;

[0101] The source of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the drain serves as the output end of the NMOS path in which it is located;

[0102] The series structure of the NMOS path including the series switch and the parallel switch is:

[0103] The source of the working NMOS tube is electrically connected to the ground, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located;

[0104] The output ends of the two NMOS paths are electrically connected to each other to form an output end of the NMOS control circuit;

[0105] The sizes of the working NMOS tubes of the two NMOS paths are arranged in order according to the weight values;

[0106] The series switch and the parallel switch of the PMOS path including the series switch and the parallel switch are both PMOS switches;

[0107] The series switch and the parallel switch of the NMOS path including the series switch and the parallel switch are both NMOS switches.

[0108] Example 3

[0109] like Figure 4 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0110] A PMOS control circuit includes two parallel PMOS paths, each PMOS path includes a working PMOS tube, one of the PMOS paths also includes a series switch and a parallel switch, the working PMOS tube of the PMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0111] The NMOS control circuit includes two parallel NMOS paths, each NMOS path includes a working NMOS tube, one of the NMOS paths also includes a series switch and a parallel switch, the working NMOS tube of the NMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0112] The gates of the working PMOS tubes of the two PMOS paths are electrically connected to each other to form an NMOS input terminal;

[0113] The gates of the working NMOS tubes of the two NMOS paths are electrically connected to each other to form a PMOS input terminal;

[0114] The drain of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the source serves as the output end of the PMOS path;

[0115] The series structure of the PMOS path including the series switch and the parallel switch is:

[0116] One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the drain of the working PMOS tube, and the source of the working PMOS tube serves as the output end of the PMOS path in which it is located;

[0117] The output ends of the two PMOS paths are electrically connected to each other to form the output end of the NMOS control circuit;

[0118] The sizes of the working PMOS tubes of the two PMOS paths are arranged in sequence according to the weight values;

[0119] The drain of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the source serves as the output end of the NMOS path;

[0120] The series structure of the NMOS path including the series switch and the parallel switch is:

[0121] One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the drain of the working NMOS tube, and the source of the working NMOS tube serves as the output end of the NMOS path in which it is located;

[0122] The output ends of the two NMOS paths are electrically connected to each other to form the output end of the PMOS control circuit.

[0123] The sizes of the working NMOS tubes of the two NMOS paths are arranged in order according to the weight values;

[0124] The series switch and the parallel switch of the PMOS path including the series switch and the parallel switch are both CMOS switches;

[0125] The series switches and parallel switches of the NMOS paths including the series switches and the parallel switches are both CMOS switches.

[0126] Example 4

[0127] like Figure 5 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0128] A PMOS control circuit includes two parallel PMOS paths, each PMOS path includes a working PMOS tube, one of the PMOS paths also includes a series switch and a parallel switch, the working PMOS tube of the PMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0129] The NMOS control circuit includes two parallel NMOS paths, each NMOS path includes a working NMOS tube, one of the NMOS paths also includes a series switch and a parallel switch, the working NMOS tube of the NMOS path is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure;

[0130] The gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form an NMOS input terminal;

[0131] The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form a PMOS input terminal;

[0132] The drain of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the source serves as the output end of the PMOS path;

[0133] The series structure of the PMOS path including the series switch and the parallel switch is:

[0134] The drain of the working PMOS tube is electrically connected to the ground, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located;

[0135] The output ends of the two PMOS paths are electrically connected to each other to form the output end of the NMOS control circuit;

[0136] The sizes of the working PMOS tubes of the two PMOS paths are arranged in sequence according to the weight values;

[0137] The drain of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the source serves as the output end of the NMOS path;

[0138] The series structure of the NMOS path including the series switch and the parallel switch is:

[0139] The drain of the working NMOS tube is electrically connected to the power supply, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located;

[0140] The output ends of the two NMOS paths are electrically connected to each other to form the output end of the PMOS control circuit;

[0141] The sizes of the working NMOS tubes of the two NMOS paths are arranged in order according to the weight values;

[0142] The series switch and the parallel switch of the PMOS path including the series switch and the parallel switch are both PMOS switches;

[0143] The series switches and the parallel switches of the NMOS path including the series switches and the parallel switches are both NMOS switches.

[0144] Example 5

[0145] like Figure 6 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0146] The PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel. Each PMOS path includes a working PMOS tube, a series switch and a parallel switch. The working PMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working PMOS tube to form a parallel structure.

[0147] The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube, a series switch and a parallel switch. The working NMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0148] The gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form a PMOS input terminal;

[0149] The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form an NMOS input terminal;

[0150] The series structure of each PMOS path is:

[0151] One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the source of the working PMOS tube, and the drain of the working PMOS tube serves as the output end of the PMOS path in which it is located;

[0152] The output ends of the PMOS paths are electrically connected to each other to form the output end of the PMOS control circuit;

[0153] The sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values;

[0154] The series structure of each NMOS path is:

[0155] One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the source of the working NMOS tube, and the drain of the working NMOS tube serves as the output end of the NMOS path in which it is located;

[0156] The output ends of the NMOS paths are electrically connected to each other to form an output end of the NMOS control circuit;

[0157] The sizes of the working NMOS tubes of each NMOS path are arranged in sequence according to the weights;

[0158] In this embodiment, the series switch and the parallel switch of each PMOS path are CMOS switches;

[0159] The series switch and parallel switch of each NMOS path are CMOS switches.

[0160] Example 6

[0161] like Figure 7 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0162] The PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel. Each PMOS path includes a working PMOS tube, a series switch and a parallel switch. The working PMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working PMOS tube to form a parallel structure.

[0163] The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube, a series switch and a parallel switch. The working NMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0164] The gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form a PMOS input terminal;

[0165] The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form an NMOS input terminal;

[0166] The series structure of each PMOS path is:

[0167] The source of the working PMOS tube is electrically connected to the power supply, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located;

[0168] The output ends of the PMOS paths are electrically connected to each other to form the output end of the PMOS control circuit.

[0169] The sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values.

[0170] The series structure of each NMOS path is:

[0171] The source of the working NMOS tube is electrically connected to the ground, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located;

[0172] The output ends of the NMOS paths are electrically connected to each other to form an output end of the NMOS control circuit;

[0173] The sizes of the working NMOS tubes of each NMOS path are arranged in sequence according to the weights;

[0174] The series switch and parallel switch of each PMOS path are both PMOS switches;

[0175] The series switch and the parallel switch of each NMOS path are both NMOS open.

[0176] Example 7

[0177] like Figure 8 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0178] The PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel. Each PMOS path includes a working PMOS tube, a series switch and a parallel switch. The working PMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working PMOS tube to form a parallel structure.

[0179] The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube, a series switch and a parallel switch. The working NMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0180] The gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form an NMOS input terminal;

[0181] The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form a PMOS input terminal;

[0182] The series structure of each PMOS path is:

[0183] One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the drain of the working PMOS tube, and the source of the working PMOS tube serves as the output end of the PMOS path in which it is located;

[0184] The output ends of the PMOS paths are electrically connected to each other to form the output end of the NMOS control circuit;

[0185] The sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values;

[0186] The series structure of each NMOS path is:

[0187] One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the drain of the working NMOS tube, and the source of the working NMOS tube serves as the output end of the NMOS path in which it is located;

[0188] The output ends of the NMOS paths are electrically connected to each other to form the output end of the PMOS control circuit;

[0189] The sizes of the working NMOS tubes of each NMOS path are arranged in sequence according to the weights;

[0190] The series switch and parallel switch of each PMOS path are CMOS switches;

[0191] The series switch and parallel switch of each NMOS path are CMOS switches.

[0192] Example 8

[0193] like Fig. 9 As shown, this embodiment provides a high linearity and low power consumption control circuit, including:

[0194] The PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel. Each PMOS path includes a working PMOS tube, a series switch and a parallel switch. The working PMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working PMOS tube to form a parallel structure.

[0195] The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube, a series switch and a parallel switch. The working NMOS tube and the series switch are connected to form a series structure. Both ends of the parallel switch are connected in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0196] The gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form an NMOS input terminal;

[0197] The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form a PMOS input terminal;

[0198] The series structure of each PMOS path is:

[0199] The drain of the working PMOS tube is electrically connected to the ground, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located;

[0200] The output ends of the PMOS paths are electrically connected to each other to form the output end of the NMOS control circuit;

[0201] The sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values;

[0202] The series structure of each NMOS path is:

[0203] The drain of the working NMOS tube is electrically connected to the power supply, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located;

[0204] The output ends of the NMOS paths are electrically connected to each other to form the output end of the PMOS control circuit;

[0205] The sizes of the working NMOS tubes of each NMOS path are arranged in sequence according to the weights;

[0206] The series switch and parallel switch of each PMOS path are both PMOS switches;

[0207] The series switch and the parallel switch of each NMOS path are both NMOS switches.

[0208] The high-linearity and low-power consumption control circuit proposed in the embodiment of the utility model improves the linearity performance of the circuit unit in each mode when realizing a configurable low-power consumption mode by connecting the working PMOS tube and the series switch into a series structure, connecting the two ends of the parallel switch in parallel with the source and drain of the working PMOS tube to form a parallel structure, connecting the working NMOS tube and the series switch into a series structure, and connecting the two ends of the parallel switch in parallel with the source and drain of the working NMOS tube to form a parallel structure.

[0209] The above description of various embodiments of the utility model is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A high linearity and low power consumption control circuit, characterized in that: include: A PMOS control circuit includes a plurality of PMOS paths, each of which is connected in parallel, each of which includes a working PMOS tube, and some or all of the PMOS paths also include a series switch and a parallel switch, wherein the working PMOS tube of the PMOS path including the series switch and the parallel switch is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure; The NMOS control circuit includes a plurality of NMOS paths, each of which is connected in parallel. Each NMOS path includes a working NMOS tube. Some or all of the NMOS paths also include a series switch and a parallel switch. The working NMOS tube of the NMOS path including the series switch and the parallel switch is connected to the series switch to form a series structure, and its source and drain are connected in parallel with two ends of the parallel switch to form a parallel structure.

2. The control circuit according to claim 1, characterized in that: The gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form a PMOS input terminal or an NMOS input terminal; The gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form an NMOS input terminal or a PMOS input terminal.

3. The control circuit according to claim 2, characterized in that: When the gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form the PMOS input terminal, The source of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the drain serves as the output end of the PMOS path in which it is located; The series structure of the PMOS path including the series switch and the parallel switch is: One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the source of the working PMOS tube, and the drain of the working PMOS tube serves as the output end of the PMOS path in which it is located, or, The source of the working PMOS tube is electrically connected to the power supply, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located; The output ends of the PMOS paths are electrically connected to each other to form the output end of the PMOS control circuit.

4. The control circuit according to claim 3, characterized in that: When the gates of the working PMOS tubes of each PMOS path are electrically connected to each other to form the NMOS input terminal, The drain of the working PMOS tube of the PMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the source serves as the output end of the PMOS path; The series structure of the PMOS path including the series switch and the parallel switch is: One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the drain of the working PMOS tube, and the source of the working PMOS tube serves as the output end of the PMOS path in which it is located, or, The drain of the working PMOS tube is electrically connected to the ground, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the PMOS path in which it is located; The output ends of the PMOS paths are electrically connected to each other to form the output end of the NMOS control circuit.

5. The control circuit according to claim 1, characterized in that: The sizes of the working PMOS tubes of each PMOS path are arranged in sequence according to the weight values.

6. The control circuit according to claim 2, characterized in that: When the gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form the NMOS input terminal, The source of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the ground, and the drain serves as the output end of the NMOS path in which it is located; The series structure of the NMOS path including the series switch and the parallel switch is: One end of the series switch is electrically connected to the ground, and the other end is electrically connected to the source of the working NMOS tube, and the drain of the working NMOS tube serves as the output end of the NMOS path in which it is located, or, The source of the working NMOS tube is electrically connected to the ground, the drain is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located; The output ends of the NMOS paths are electrically connected to each other to form the output end of the NMOS control circuit.

7. The control circuit according to claim 4, characterized in that: When the gates of the working NMOS tubes of each NMOS path are electrically connected to each other to form the PMOS input terminal, The drain of the working NMOS tube of the NMOS path excluding the series switch and the parallel switch is electrically connected to the power supply, and the source serves as the output end of the NMOS path; The series structure of the NMOS path including the series switch and the parallel switch is: One end of the series switch is electrically connected to the power supply, and the other end is electrically connected to the drain of the working NMOS tube, and the source of the working NMOS tube serves as the output end of the NMOS path in which it is located, or, The drain of the working NMOS tube is electrically connected to the power supply, the source is electrically connected to one end of the series switch, and the other end of the series switch serves as the output end of the NMOS path in which it is located; The output ends of the NMOS paths are electrically connected to each other to form the output end of the PMOS control circuit.

8. The control circuit according to claim 1, characterized in that: The sizes of the working NMOS tubes of each NMOS path are arranged in sequence according to the weight value.

9. The control circuit according to claim 1, characterized in that: The series switch and the parallel switch of each PMOS path including the series switch and the parallel switch are independently selected from PMOS switches or CMOS switches.

10. The control circuit according to claim 1, characterized in that: Each series switch and parallel switch of the NMOS path including the series switch and the parallel switch are independently selected from NMOS switches or CMOS switches.

Images