Planar gate silicon carbide MOSFET device

Abstract

The utility model discloses a planar gate silicon carbide MOSFET device, and relates to the technical field of semiconductors. In the SiC VDMOSFET device, an original grid electrode is separated into two independent grid electrodes through metal, a P region is formed on the SiC surface at the bottom through injection, a gate oxide layer is protected by adopting the P region, and the upper surface of the P region is in ohmic contact with the metal to realize grounding treatment, so that the protection capability of the SiC VDMOSFET device is further improved; therefore, the use reliability of the gate oxide layer of the device is improved. In addition, the separated grid electrode also reduces the grid-drain capacitance of the device, so that the switching characteristic of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a planar gate silicon carbide MOSFET device. Background Art

[0002] In the field of power electronics technology, Si materials have significant advantages such as high reserves in nature, mature preparation and purification processes, stable single crystal structure, high reliability and low price, making Si-based power devices the most important product of power electronics devices. However, with the continuous development of power electronics technology, power devices are developing in the direction of smaller size, higher density, higher frequency and greater power, which also puts more stringent requirements on semiconductor materials. However, due to the inherent limitations of Si materials, their performance development has reached its limit, so the third-generation wide bandgap semiconductor materials represented by SiC have begun to develop rapidly.

[0003] SiC materials have a series of advantages such as large bandgap, high critical breakdown field strength, low intrinsic carrier concentration, fast saturation drift rate, and high thermal conductivity. Compared with traditional Si-based power devices, the power devices prepared by them can have smaller chip size and volume while also having high voltage and high current capabilities. In particular, SiC MOSFET devices, compared with Si MOSFET and Si IGBT devices, have both excellent conduction and switching characteristics, and have shown great application prospects in high voltage, high temperature, high frequency and other fields. However, SiC MOSFET devices also have obvious disadvantages. Since SiC materials contain C elements, the interface state density of the SiC / SiO2 interface is large and there are many defects during the thermal oxidation growth process, resulting in poor quality of the grown gate oxide layer, which is easy to cause early breakdown failure during long-term use, greatly affecting the reliability of the device. Utility Model Content

[0004] In view of the above problems, the utility model provides a planar gate silicon carbide MOSFET device which improves its protection capability and the reliability of the gate oxide layer and reduces the gate-drain capacitance of the device.

[0005] The technical solution of the utility model is:

[0006] A planar gate silicon carbide MOSFET device, comprising a back electrode metal, a back ohmic alloy layer, a Sub layer, an Epi layer, an ohmic alloy layer and a front electrode metal arranged in sequence from bottom to top;

[0007] The Epi layer is provided with:

[0008] A P-body region extending downward from the top surface of the Epi layer;

[0009] An NP region extending downward from the top surface of the P-body region and having a spacing from the bottom surface of the P-body region;

[0010] A PP region, comprising a first PP region and a second PP region; the first PP region extends downward from the middle of the top surface of the Epi layer; the second PP region extends downward from the top surface of the P-body region and is connected to the NP region;

[0011] A gate oxide layer, a Poly layer and a dielectric layer are arranged in sequence from bottom to top between the front electrode metal and the Epi layer;

[0012] The bottom surface of the gate oxide layer is connected to the Epi layer, the P-body region and the NP region respectively;

[0013] The dielectric layer extends downward from the side of the Poly layer, is connected to the NP region, and is connected to the Ohmic alloy layer 9 .

[0014] Specifically, the back electrode metal is Ti / Ni / Ag metal.

[0015] Specifically, the thickness of the Ti / AlCu metal is 30nm / 300nm / 1200nm.

[0016] Specifically, the front electrode metal is Ti / AlCu metal.

[0017] Specifically, the thickness of the Ti / AlCu metal is 100nm / 5000nm.

[0018] In the SiCVDMOSFET device, the utility model separates the gate into two independent gates by metal, and forms a P region by implantation on the SiC surface at the bottom, and uses the P region to protect the gate oxide layer, and the ohmic contact formed between the upper surface of the P region and the metal enables the P region to achieve grounding, thereby further improving its protection capability, thereby improving the reliability of the gate oxide layer of the device. In addition, the separated gate also reduces the gate-drain capacitance of the device, thereby improving the switching characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0020] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0021] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0022] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0023] Figure 5 It is a structural schematic diagram of step S500 of the utility model;

[0024] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0025] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0026] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0027] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0028] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0029] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0030] In the figure, 1 is the Sub layer, 2 is the Epi layer, 3 is the P-body region, 4 is the NP region, 5 is the PP region, 6 is the gate oxide layer, 7 is the Poly layer, 8 is the dielectric layer, 9 is the front ohmic alloy layer, 10 is the front electrode metal, 11 is the back ohmic alloy layer, and 12 is the back electrode metal. DETAILED DESCRIPTION

[0031] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0032] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] A method for preparing a planar gate silicon carbide MOSFET device comprises the following steps:

[0035] S100, refer to Figure 1 As shown, an epitaxial Epi layer 2 is epitaxially grown on the Sub layer 1;

[0036] In step S100 , the conductivity types of the Sub layer 1 and the Epi layer 2 are both N-type.

[0037] S200, refer to Figure 2 As shown, a P-body region 3 is formed on the upper surface of the Epi layer 2 by ion implantation;

[0038] The ions implanted into the P-body region 3 in step S200 are Al ions, the implantation energy range is 30-500keV, and the implantation dose range is 1E12-1E16cm -2 , the injection temperature is 400℃-600℃.

[0039] S300, refer to Figure 3 As shown, an NP region 4 is formed on the upper surface of the Epi layer 2 by ion implantation;

[0040] In step S300, the ions implanted into the NP region 4 are N ions, the implantation energy range is 20-300keV, and the implantation dose range is 3.6E11-1E15cm -2 , the injection temperature is room temperature.

[0041] S400, refer to Figure 4 As shown, a PP region 5 is formed on the upper surface of the Epi layer 2 by ion implantation, and then the implanted region is completely formed by high temperature activated diffusion;

[0042] In step S400, the ions implanted into the PP region 5 are Al ions, the implantation energy range is 30-500keV, and the implantation dose range is 1E12-1E16cm -2 The injection temperature is 400℃-600℃, and the high temperature activation diffusion temperature is 1600℃-1900℃.

[0043] S500, refer to Figure 5As shown, a gate oxide layer 6 is grown on the top surface of the Epi layer 2 by dry oxygen oxidation;

[0044] S600, refer to Figure 6 As shown, a Poly layer 7 is formed on the top surface of the gate oxide layer 6 by depositing polysilicon to serve as the gate electrode of the VDMOSFET device;

[0045] S700, reference Figure 7 As shown, a dielectric layer 8 is formed on the top surface of the Epi layer 2 and the Poly layer 7 by oxide deposition to serve as an isolation function;

[0046] S800, reference Figure 8 As shown, a Ni metal layer is formed on the top surface of the Epi layer 2 by Ni metal sputtering, and then the two are alloyed by rapid thermal annealing to form a front ohmic alloy layer 9;

[0047] The Ni metal thickness in step S800 is 100 nm, the thermal annealing temperature is 1000° C., and the time is 5 min.

[0048] S900, refer to Fig. 9 As shown, a front electrode metal layer 10 is formed on the top surface of the dielectric layer 8 and the front ohmic alloy layer 9 by Ti / AlCu metal sputtering to serve as the source electrode of the VDMOSFET device;

[0049] The thickness of the Ti / AlCu metal in step S900 is 100 nm / 5000 nm.

[0050] S1000, refer to Fig.10 As shown, a Ni metal layer is formed on the bottom surface of the Sub layer 1 by Ni metal sputtering, and then the Sub layer 1 and the Ni metal layer are subjected to laser annealing to form a back ohmic alloy layer 11;

[0051] The thickness of the Ni metal in step S1000 is 100 nm.

[0052] S1100, reference Fig.11 As shown, a layer of back electrode metal 12 is formed on the bottom surface of the back ohmic alloy layer 11 by Ti / Ni / Ag metal evaporation to serve as the drain electrode of the VDMOSFET device;

[0053] The thickness of the Ti / Ni / Ag metal in step S1100 is 30nm / 300nm / 1200nm.

[0054] A planar gate silicon carbide MOSFET device, comprising a back electrode metal 12, a back ohmic alloy layer 11, a Sub layer 1, an Epi layer 2, an ohmic alloy layer 9 and a front electrode metal 10 arranged in sequence from bottom to top;

[0055] The Epi layer 2 is provided with:

[0056] A P-body region 3 extending downward from the top surface of the Epi layer 2;

[0057] The NP region 4 extends downward from the top surface of the P-body region 3 and is spaced apart from the bottom surface of the P-body region 3 by 0.4um-0.8um to ensure that there is sufficient depletion layer expansion space inside the P-body region 3 during the device blocking process to avoid breakdown.

[0058] PP region 5, including a first PP region and a second PP region; the first PP region extends downward from the middle of the top surface of the Epi layer 2; the second PP region extends downward from the top surface of the P-body region 3 and is connected to the NP region 4;

[0059] The first PP region and the second PP region are completed by a synchronous process, so their depths are consistent, and the depth of the PP region 5 is 0.2 um lower than the depth of the NP region 3 to ensure the reverse withstand voltage performance of the device during the blocking process.

[0060] A gate oxide layer 6, a Poly layer 7 and a dielectric layer 8 are arranged in sequence from bottom to top between the front electrode metal 10 and the Epi layer 2;

[0061] The bottom surface of the gate oxide layer 6 is connected to the Epi layer 2, the P-body region 3 and the NP region 4 respectively;

[0062] The dielectric layer 8 extends downward from the side of the Poly layer 7 , is connected to the NP region 4 , and is connected to the Ohmic alloy layer 9 .

[0063] Beneficial effects of the utility model:

[0064] 1. Improve the reliability of the gate oxide layer of the device:

[0065] Since the interface state density of SiC / SiO2 interface at the gate oxide of SiC MOSFET is large and there are many defects, the gate oxide layer is prone to premature breakdown failure, which affects the long-term reliability of the device. The utility model uses metal to separate the original gate into two independent gates in the SiC VDMOSFET device, and forms a P region on the surface of the SiC Epi layer, and uses the P region to protect the gate oxide layer, and an ohmic contact is formed between the upper surface of the P region and the metal, thereby achieving grounding treatment of the P region, further improving the protection of the P region, and improving the reliability of the gate oxide layer of the SiC VDMOSFET device.

[0066] 2. Improve the switching performance of the device:

[0067] The gate-drain capacitance inside SiC MOSFET is the most important factor affecting the switching characteristics of the device. The utility model separates the gate, thereby reducing the coupling area between the gate and the drain, thereby reducing the gate-drain capacitance of the device, thereby improving the switching performance of the device.

Claims

1. A planar gate silicon carbide MOSFET device, characterized in that: It comprises a back electrode metal (12), a back ohmic alloy layer (11), a Sub layer (1), an Epi layer (2), an ohmic alloy layer (9) and a front electrode metal (10) which are arranged in sequence from bottom to top; The Epi layer (2) is provided with: A P-body region (3) extending downward from the top surface of the Epi layer (2); An NP region (4) extending downward from the top surface of the P-body region (3) and having a spacing with the bottom surface of the P-body region (3); The PP region (5) comprises a first PP region and a second PP region; the first PP region extends downward from the middle of the top surface of the Epi layer (2); the second PP region extends downward from the top surface of the P-body region (3) and is connected to the NP region (4); A gate oxide layer (6), a Poly layer (7) and a dielectric layer (8) are provided between the front electrode metal (10) and the Epi layer (2) in order from bottom to top; The bottom surface of the gate oxide layer (6) is respectively connected to the Epi layer (2), the P-body region (3) and the NP region (4); The dielectric layer (8) extends downward from the side of the Poly layer (7), is connected to the NP region (4), and is connected to the Ohmic alloy layer 9.

2. A planar gate silicon carbide MOSFET device according to claim 1, characterized in that: The back electrode metal (12) is Ti / Ni / Ag metal.

3. A planar gate silicon carbide MOSFET device according to claim 2, characterized in that: The thickness of the Ti / AlCu metal is 30nm / 300nm / 1200nm.

4. A planar gate silicon carbide MOSFET device according to claim 1, characterized in that: The front electrode metal (10) is Ti / AlCu metal.

5. A planar gate silicon carbide MOSFET device according to claim 4, characterized in that: The thickness of the Ti / AlCu metal is 100nm / 5000nm.

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