Voltage balancing circuit, photovoltaic inverter and photovoltaic inverter system based on three-level topology

Abstract

The utility model relates to a voltage balancing circuit, a photovoltaic inverter and a photovoltaic inverter system based on a three-level topology. Compared with the prior art, the voltage balancing circuit includes a filter circuit, a clamp circuit, an inverter circuit, a first voltage balancing module and a second voltage balancing module; wherein the first output end of the filter circuit is connected to the positive pole of the bus, the input end is connected to the negative pole of the bus, and the second output end is connected to the clamp circuit; the first end of the inverter circuit is connected to the positive pole of the bus, and the second end is connected to the negative pole of the bus; the first end and the second end of the clamp circuit are respectively connected to the first clamp point and the second clamp point in the inverter circuit; and the first voltage balancing module is connected in parallel with the first inner tube module, and the second voltage balancing module is connected in parallel with the second inner tube module. Through this application, the problem of being unable to ensure voltage balancing when the inner and outer tubes are connected in series in a static state is solved, and ensuring voltage balancing when the inner and outer tubes are connected in series in a static state is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, in particular to a voltage balancing circuit, a photovoltaic inverter and a photovoltaic inverter system based on a three-level topology. Background Art

[0002] As the application of photovoltaic power generation in the field of new energy is gradually deepened, 3L-NPC three-level topology is widely used in high-power inverters. Among them, the structure of 3L-NPC three-level topology uses insulated gate bipolar transistors (IGBT) in series, so that the voltage borne by each IGBT is half of the bus voltage, thereby reducing the withstand voltage of the IGBT. At the same time, the topology has lower losses under high switching frequency conditions.

[0003] However, due to the unidirectional conductivity of the clamping diode in the three-level topology, the voltage of the clamped outer tube does not exceed half the bus, and there is a risk that the voltage of the inner tube will exceed half the bus, so it is impossible to ensure that the inner and outer tubes are connected in series in a static state. The uneven voltage phenomenon can easily cause device damage and reduce system reliability.

[0004] With regard to the problem in the related art that it is impossible to ensure pressure balance when the inner and outer tubes are connected in series in a static state, no effective solution has been proposed so far. Utility Model Content

[0005] Based on this, it is necessary to provide a voltage equalization circuit, photovoltaic inverter and photovoltaic inverter system based on a three-level topology to address the problem of being unable to ensure voltage equalization when the inner and outer tubes are connected in series in a static state.

[0006] In a first aspect, the utility model provides a voltage balancing circuit based on a three-level topology, wherein the voltage balancing circuit includes a filter circuit, a clamp circuit, an inverter circuit, a first voltage balancing module, and a second voltage balancing module;

[0007] The first output end of the filter circuit is connected to the positive pole of the bus; the input end of the filter circuit is connected to the negative pole of the bus; the second output end of the filter circuit is connected to the clamping circuit;

[0008] The first end of the inverter circuit is connected to the positive electrode of the bus; the second end of the inverter circuit is connected to the negative electrode of the bus;

[0009] The first end of the clamping circuit is connected to a first clamping point between a first inner tube module and a first outer tube module in the inverter circuit; the second end of the clamping circuit is connected to a second clamping point between a second inner tube module and a second outer tube module in the inverter circuit;

[0010] The first pressure equalizing module is connected in parallel with the first inner tube module;

[0011] The second pressure equalizing module is connected in parallel with the second inner tube module.

[0012] In some of the embodiments, the first voltage balancing module includes at least one voltage balancing resistor R1;

[0013] The resistance of the voltage-equalizing resistor R1 is smaller than the product of a preset ratio and an off resistance corresponding to the first outer tube module; wherein the preset ratio corresponds to the voltage balancing rate of the first outer tube module.

[0014] In some of the embodiments, the second voltage balancing module includes at least one voltage balancing resistor R2;

[0015] The resistance of the voltage-equalizing resistor R2 is smaller than the product of a preset ratio and an off resistance corresponding to the second outer tube module; wherein the preset ratio corresponds to a voltage balancing rate of the second outer tube module.

[0016] In some of the embodiments, the inner tube module and the outer tube module both include a power switch device and a freewheeling diode;

[0017] The freewheeling diode is connected in reverse parallel to the power switch device.

[0018] In some of the embodiments, the inner tube module and the outer tube module each further include an output junction capacitor;

[0019] The output junction capacitor is connected in parallel with the power switch device.

[0020] In some of the embodiments, the power switch device is an insulated gate bipolar transistor.

[0021] In some of the embodiments, the clamping circuit includes a clamping diode D1 and a clamping diode D2;

[0022] One end of the clamping diode D1 is connected to the first clamping point; the other end of the clamping diode D1 is connected to one end of the clamping diode D2;

[0023] The other end of the clamping diode D2 is connected to the second clamping point.

[0024] In some of the embodiments, the filter circuit includes a capacitor C1 and a capacitor C2;

[0025] One end of the capacitor C1 is connected to the positive electrode of the busbar; the other end of the capacitor C1 is connected to one end of the capacitor C2 and the clamping circuit respectively;

[0026] The other end of the capacitor C2 is connected to the negative electrode of the busbar.

[0027] In a second aspect, the utility model provides a photovoltaic inverter, wherein the photovoltaic inverter comprises a voltage balancing circuit based on a three-level topology as described in any one of the first aspects.

[0028] In a third aspect, the utility model provides a photovoltaic inverter system, wherein the photovoltaic inverter system comprises a voltage balancing circuit based on a three-level topology as described in any one of the first aspects.

[0029] The utility model provides a voltage balancing circuit, a photovoltaic inverter and a photovoltaic inverter system based on a three-level topology. Compared with the prior art, the voltage balancing circuit includes a filter circuit, a clamp circuit, an inverter circuit, a first voltage balancing module and a second voltage balancing module; wherein the first output end of the filter circuit is connected to the positive pole of the bus, the input end is connected to the negative pole of the bus, and the second output end is connected to the clamp circuit; the first end of the inverter circuit is connected to the positive pole of the bus, and the second end is connected to the negative pole of the bus; the first end and the second end of the clamp circuit are respectively connected to the first clamp point and the second clamp point in the inverter circuit; and the first voltage balancing module is connected in parallel with the first inner tube module, and the second voltage balancing module is connected in parallel with the second inner tube module, which solves the problem of being unable to ensure voltage balancing when the inner and outer tubes are connected in series in a static state, and ensures voltage balancing when the inner and outer tubes are connected in series in a static state. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a structural block diagram of a voltage balancing circuit based on a three-level topology according to an embodiment of the utility model;

[0031] Figure 2 This is a schematic diagram of an inverter circuit according to an embodiment of the utility model;

[0032] Figure 3 It is a schematic diagram of a voltage equalizing circuit based on a three-level topology according to a preferred embodiment of the utility model.

[0033] Figure numerals: 100, filter circuit; 200, clamping circuit; 300, inverter circuit; 310, first outer tube module; 320, first inner tube module; 330, second inner tube module; 340, second outer tube module; 400, first voltage equalizing module; 500, second voltage equalizing module. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0035] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more related listed items.

[0037] The utility model provides a voltage balancing circuit based on a three-level topology. Figure 1 FIG. 1 is a structural block diagram of a voltage balancing circuit based on a three-level topology according to an embodiment of the present invention. Figure 1 As shown, the voltage balancing circuit includes a filter circuit 100, a clamp circuit 200, an inverter circuit 300, a first voltage balancing module 400 and a second voltage balancing module 500;

[0038] The first output terminal of the filter circuit 100 is connected to the positive electrode of the bus; the input terminal of the filter circuit 100 is connected to the negative electrode of the bus; the second output terminal of the filter circuit 100 is connected to the clamping circuit 200;

[0039] The first end of the inverter circuit 300 is connected to the positive electrode of the bus; the second end of the inverter circuit 300 is connected to the negative electrode of the bus;

[0040] The first end of the clamping circuit 200 is connected to a first clamping point between the first inner tube module 320 and the first outer tube module 310 in the inverter circuit 300; the second end of the clamping circuit 200 is connected to a second clamping point between the second inner tube module 330 and the second outer tube module 340 in the inverter circuit 300;

[0041] A first pressure equalizing module 400 is connected in parallel with the first inner tube module 320;

[0042] The second pressure equalizing module 500 is connected in parallel with the second inner tube module 330 .

[0043] Specifically, the voltage balancing circuit of this embodiment includes a filter circuit 100, a clamp circuit 200, an inverter circuit 300 and two voltage balancing modules. The first output terminal and the input terminal of the filter circuit 100 are respectively connected to the positive and negative poles of the bus, and the second output terminal is connected to the clamp circuit 200, that is, the midpoint of the bus is connected to the clamp circuit 200.

[0044] The inverter circuit 300 includes an inner tube module and an outer tube module. The input end of the first outer tube module 310 is connected to the positive pole of the bus, and the output end of the second outer tube module 340 is connected to the negative pole of the bus. The first outer tube module 310, the first inner tube module 320, the second inner tube module 330 and the second outer tube module 340 are connected in series in sequence.

[0045] In the inverter circuit 300, the series connection point between the first inner tube module 320 and the first outer tube module 310 is the first clamping point, the series connection point between the second inner tube module 330 and the second outer tube module 340 is the second clamping point, and the two ends of the clamping circuit 200 are connected to the first clamping point and the second clamping point respectively.

[0046] In addition, the first pressure equalizing module 400 of this embodiment is connected in parallel with the first inner tube module 320, and the second pressure equalizing module 500 is connected in parallel with the second inner tube module 330. It should be noted that, since the pressure equalization of the inner and outer tubes in series is affected by their blocking characteristics under static operation, by connecting the pressure equalizing modules in parallel at both ends of the inner tube module, the blocking balance rate when the inner and outer tubes are turned off can be guaranteed, thereby achieving pressure equalization when the inner and outer tubes are connected in series in static state.

[0047] The current 3L-NPC three-level topology uses IGBTs in series, so that the voltage borne by each IGBT is half of the bus voltage, thereby reducing the withstand voltage of the IGBT. At the same time, the topology has lower losses under high switching frequency conditions. However, due to the unidirectional conductivity of the clamping diode in the three-level topology, the clamping outer tube voltage does not exceed half of the bus, and there is a risk that the inner tube voltage will exceed half of the bus. It is impossible to ensure that the inner and outer tubes are connected in series in a static state. The uneven voltage phenomenon can easily cause device damage and reduce system reliability.

[0048] Compared with the prior art, the present application sets up a voltage equalizing circuit including a filter circuit 100, a clamping circuit 200, an inverter circuit 300, a first voltage equalizing module 400 and a second voltage equalizing module 500, and connects the first voltage equalizing module 400 in parallel with the first inner tube module 320, and connects the second voltage equalizing module 500 in parallel with the second inner tube module 330, so that the resistance-off characteristics of the inner and outer tubes can be utilized to ensure the resistance-off balance rate when the inner and outer tubes are turned off, so that the voltage balance rate of the inner and outer tubes plays a role of static voltage equalization, which solves the problem of being unable to ensure voltage equalization when the inner and outer tubes are connected in series statically, and ensures voltage equalization when the inner and outer tubes are connected in series statically, reduces switching losses, avoids the risk of parasitic oscillations, and has a simple circuit structure, effectively reducing device costs.

[0049] In some of the embodiments, the first voltage balancing module 400 includes at least one voltage balancing resistor R1;

[0050] The resistance of the voltage balancing resistor R1 is smaller than the product of the preset ratio and the off resistance corresponding to the first outer tube module 310 ; wherein the preset ratio corresponds to the voltage balancing rate of the first outer tube module 310 .

[0051] Specifically, the first voltage balancing module 400 includes at least one voltage balancing resistor R1, which is connected in parallel with the first inner tube module 320, and different numbers of voltage balancing resistors are selected according to actual application requirements.

[0052] It should be noted that, under static operation, the main factor affecting the voltage balance of the inner and outer tubes in series is their blocking characteristics. If the inner and outer tubes have high off-resistance or small leakage current when turned off, they will withstand higher voltage. off =U CES / I CES , U CES Indicates the maximum forward voltage that can be sustained under shutdown conditions, I CES Indicates leakage current. When the leakage current I CES Different, the off resistance value R off It is also different.

[0053] Based on this, the static voltage equalization process of this embodiment is described. For the outer tube T1 and the inner tube T2, assuming that the leakage current I of T1 CES1 Greater than the leakage current I of T2 CES2 , and the voltage balance rate is a, then R off1 <R off2 , and the equivalent resistance of T2 when it is turned off is R T2 =R off2 *R1 / (R off2 +R1); Since the off-resistance of the inner and outer tubes is high or the leakage current is small when turned off, they will withstand a higher voltage. Therefore, the voltage that T2 withstands is higher than the voltage that T1 withstands. At this time, R T2 <(1+a)*R off1 , and R T2 =R off2 *R1 / (R off2 +R1) Substitute into R T2 <(1+a)*R off1 , simplify to get R1(1-1.2R off1 / R off2 )<1.2 Roff1 ; Further, in the most extreme state, when I CES1 When it reaches the maximum value, I CES2 is 0, then R off2 Approaching infinity, the above formula can be simplified to R1<1.2R off1, which means that when the resistance value of the voltage-equalizing resistor R1 is set to be smaller than the product of the preset ratio and the off-resistance value corresponding to the first outer tube module 310, by connecting the voltage-equalizing resistor R1 in parallel at both ends of the first inner tube module 320, the off-resistance balance rate when the inner and outer tubes are turned off can be guaranteed, thereby achieving voltage balancing when the inner and outer tubes are connected in series in a static state, wherein the preset ratio corresponds to the voltage balance rate of the first outer tube module 310.

[0054] Through this embodiment, the first voltage equalizing module 400 is set to include at least one voltage equalizing resistor R1, and the resistance value of the voltage equalizing resistor R1 is smaller than the product of a preset ratio and the off-resistance value corresponding to the first outer tube module 310, wherein the preset ratio corresponds to the voltage equalization rate of the first outer tube module 310, thereby utilizing the off-resistance characteristics of the inner and outer tubes to ensure the off-resistance equalization rate when the inner and outer tubes are turned off, thereby achieving voltage equalization when the inner and outer tubes are connected in series in a static state.

[0055] In some of the embodiments, the second voltage balancing module 500 includes at least one voltage balancing resistor R2;

[0056] The resistance of the voltage balancing resistor R2 is smaller than the product of the preset ratio and the off resistance value corresponding to the second outer tube module 340 ; wherein the preset ratio corresponds to the voltage balancing rate of the second outer tube module 340 .

[0057] Specifically, the second voltage balancing module 500 includes at least one voltage balancing resistor R2, which is connected in parallel with the second inner tube module 330, and different numbers of voltage balancing resistors are selected according to actual application requirements.

[0058] It should be noted that, under static operation, the main factor affecting the voltage balance of the inner and outer tubes in series is their blocking characteristics. If the inner and outer tubes have high off-resistance or small leakage current when turned off, they will withstand higher voltage. off =U CES / I CES , U CES Indicates the maximum forward voltage that can be sustained under shutdown conditions, I CES Indicates leakage current. When the leakage current I CES Different, the off resistance value R off Based on this, the static pressure equalization process of the second outer tube module 340 and the second inner tube module 330 in this embodiment is similar to the static pressure equalization process of the first outer tube module 310 and the first inner tube module 320. When the resistance value of the voltage equalization resistor R2 is set to be less than the product of the preset ratio and the off resistance value corresponding to the second outer tube module 340, the off resistance balance rate when the inner and outer tubes are turned off can be guaranteed by connecting the voltage equalization resistor R2 in parallel at both ends of the second inner tube module 330, thereby achieving static pressure equalization when the inner and outer tubes are connected in series, wherein the preset ratio corresponds to the voltage balance rate of the second outer tube module 340.

[0059] Through this embodiment, the second voltage equalizing module 500 is set to include at least one voltage equalizing resistor R2, and the resistance value of the voltage equalizing resistor R2 is smaller than the product of a preset ratio and the off-resistance value corresponding to the second outer tube module 340, wherein the preset ratio corresponds to the voltage equalization rate of the second outer tube module 340, thereby utilizing the off-resistance characteristics of the inner and outer tubes to ensure the off-resistance equalization rate when the inner and outer tubes are turned off, thereby achieving voltage equalization when the inner and outer tubes are connected in series in a static state.

[0060] In some of the embodiments, the inner tube module and the outer tube module both include a power switch device and a freewheeling diode;

[0061] The freewheeling diode is connected in reverse parallel with the power switch device.

[0062] Specifically, the inner tube module and the outer tube module both include a power switch device and a freewheeling diode. The power switch device is an insulated gate bipolar transistor; and the freewheeling diode is connected in reverse parallel with the power switch device, so that the current can be freewheeled when the power switch device is turned off, so as to protect the power switch device from damage by reverse voltage and reduce the loss of the power switch device.

[0063] Through this embodiment, the inner tube module and the outer tube module are both provided to include a power switching device and a freewheeling diode, and the freewheeling diode is reversely connected in parallel with the power switching device, so as to play a role in switch control and voltage regulation, ensure the normal operation of the circuit and provide the required voltage output, and use the freewheeling diode to reduce the loss of the device.

[0064] In some of the embodiments, the inner tube module and the outer tube module each further include an output junction capacitor;

[0065] The output junction capacitance is connected in parallel with the power switching device.

[0066] Specifically, output junction capacitors are provided in the inner tube module and the outer tube module, and the output junction capacitors are connected in parallel with the power switch device. By connecting the output junction capacitors in parallel with the power switch device, the output voltage of the power switch device is stabilized and the high-frequency noise generated by the switching process is filtered out.

[0067] Through this embodiment, both the inner tube module and the outer tube module are provided to further include an output junction capacitor, and the output junction capacitor is connected in parallel with the power switch device, thereby stabilizing the output voltage of the power switch device.

[0068] In some of the embodiments, the clamping circuit 200 includes a clamping diode D1 and a clamping diode D2;

[0069] One end of the clamping diode D1 is connected to the first clamping point; the other end of the clamping diode D1 is connected to one end of the clamping diode D2;

[0070] The other end of the clamping diode D2 is connected to the second clamping point.

[0071] Specifically, the clamping circuit 200 includes a clamping diode D1 and a clamping diode D2, wherein the cathode of the clamping diode D1 is connected to the first clamping point, the anode of the clamping diode D1 is connected to the cathode of the clamping diode D2, and the anode of the clamping diode D2 is connected to the second clamping point.

[0072] The serial connection point between the first inner tube module 320 and the first outer tube module 310 is a first clamping point, and the serial connection point between the second inner tube module 330 and the second outer tube module 340 is a second clamping point.

[0073] According to this embodiment, a clamping diode D1 and a clamping diode D2 are provided in the clamping circuit 200 , and a series connection point of the clamping diode D1 and the clamping diode D2 is connected to a neutral point to provide an additional voltage level and realize a three-level output voltage waveform.

[0074] In some of the embodiments, the filter circuit 100 includes a capacitor C1 and a capacitor C2;

[0075] One end of the capacitor C1 is connected to the positive electrode of the busbar; the other end of the capacitor C1 is connected to one end of the capacitor C2 and the clamping circuit 200 respectively;

[0076] The other end of capacitor C2 is connected to the negative electrode of the bus.

[0077] Specifically, the filter circuit 100 includes a capacitor C1 and a capacitor C2, one end of the capacitor C1 is connected to the positive electrode of the bus, the other end of the capacitor C1 is respectively connected to one end of the capacitor C2 and the middle node of the clamp circuit 200, and the other end of the capacitor C2 is connected to the negative electrode of the bus. The middle node of the clamp circuit 200 is the series connection point of the clamp diode D1 and the clamp diode D2.

[0078] According to this embodiment, capacitors C1 and C2 are provided in the filter circuit 100 , and two ends of the filter circuit 100 are respectively connected to the positive and negative electrodes of the busbar, so as to achieve voltage balancing and filtering effects.

[0079] The present embodiment is described and illustrated below through preferred embodiments.

[0080] Figure 3 is a schematic diagram of a voltage balancing circuit based on a three-level topology provided in a preferred embodiment of the present application, such as Figure 3As shown, the circuit includes: capacitor C1, capacitor C2, clamping diode D1, clamping diode D2, inverter circuit 300, equalizing resistor R1 and equalizing resistor R2; wherein, the inverter circuit 300 includes outer tubes T1 and T4, inner tubes T2 and T3, the freewheeling diode D3 and the output junction capacitor Cs1 are both connected in parallel with T1, the freewheeling diode D4 and the output junction capacitor Cs2 are both connected in parallel with T2, the freewheeling diode D5 and the output junction capacitor Cs3 are both connected in parallel with T3, and the freewheeling diode D6 and the output junction capacitor Cs4 are both connected in parallel with T4.

[0081] Specifically, one end of the capacitor C1 is connected to the bus positive electrode BUS+, and the other end of the capacitor C1 is respectively connected to one end of the capacitor C2 and the middle node of the clamp circuit 200, that is, the neutral point N is connected to the middle node of the clamp circuit 200, and the other end of the capacitor C2 is connected to the bus negative electrode BUS-. The middle node of the clamp circuit 200 is the series connection point of the positive electrode of the clamp diode D1 and the negative electrode of the clamp diode D2, and the negative electrode of the clamp diode D1 is connected to the first clamp point, and the positive electrode of the clamp diode D2 is connected to the second clamp point.

[0082] It should be noted that the first clamping point is the series connection point between the first inner tube module 320 and the first outer tube module 310 , and the second clamping point is the series connection point between the second inner tube module 330 and the second outer tube module 340 .

[0083] In static operation, the voltage balancing of the inner and outer tubes in series is affected by their blocking characteristics. If the inner and outer tubes have high off-resistance or small leakage current when turned off, they will bear higher voltage. Based on this, the voltage balancing resistor R1 is connected in parallel with T2, and the voltage balancing resistor R2 is connected in parallel with T3 to ensure the off-resistance balance rate when the inner and outer tubes are turned off, and to achieve voltage balancing when the inner and outer tubes are connected in series in static state.

[0084] Through this embodiment, the voltage equalizing resistor R1 is connected in parallel with T2, and the voltage equalizing resistor R2 is connected in parallel with T3, so as to utilize the off-resistance characteristics of the inner and outer tubes to ensure the off-resistance balance rate when the inner and outer tubes are turned off, so that the voltage balance rate of the inner and outer tubes plays a role of static voltage equalization, which solves the problem of not being able to ensure the voltage equalization when the inner and outer tubes are connected in series statically, and ensures the voltage equalization when the inner and outer tubes are connected in series statically, reduces switching losses and has a simple circuit structure.

[0085] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-mentioned embodiments only express several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A voltage balancing circuit based on a three-level topology, characterized in that: The voltage balancing circuit comprises a filter circuit (100), a clamp circuit (200), an inverter circuit (300), a first voltage balancing module (400) and a second voltage balancing module (500); The first output end of the filter circuit (100) is connected to the positive pole of the bus; the input end of the filter circuit (100) is connected to the negative pole of the bus; the second output end of the filter circuit (100) is connected to the clamping circuit (200); The first end of the inverter circuit (300) is connected to the positive electrode of the bus bar; the second end of the inverter circuit (300) is connected to the negative electrode of the bus bar; The first end of the clamping circuit (200) is connected to a first clamping point between a first inner tube module (320) and a first outer tube module (310) in the inverter circuit (300); the second end of the clamping circuit (200) is connected to a second clamping point between a second inner tube module (330) and a second outer tube module (340) in the inverter circuit (300); The first pressure equalizing module (400) is connected in parallel with the first inner tube module (320); The second pressure equalizing module (500) is connected in parallel with the second inner tube module (330).

2. The voltage balancing circuit based on three-level topology according to claim 1, characterized in that: The first voltage balancing module (400) comprises at least one voltage balancing resistor R1; The resistance of the voltage-equalizing resistor R1 is smaller than the product of a preset ratio and an off resistance corresponding to the first outer tube module (310); wherein the preset ratio corresponds to the voltage balancing rate of the first outer tube module (310).

3. The voltage balancing circuit based on three-level topology according to claim 1, characterized in that: The second voltage balancing module (500) comprises at least one voltage balancing resistor R2; The resistance of the voltage-equalizing resistor R2 is smaller than the product of a preset ratio and an off resistance corresponding to the second outer tube module (340); wherein the preset ratio corresponds to the voltage balancing rate of the second outer tube module (340).

4. The voltage balancing circuit based on three-level topology according to claim 1, characterized in that: The inner tube module and the outer tube module both include a power switch device and a freewheeling diode; The freewheeling diode is connected in reverse parallel to the power switch device.

5. The voltage balancing circuit based on three-level topology according to claim 4, characterized in that: The inner tube module and the outer tube module both further include an output junction capacitor; The output junction capacitor is connected in parallel with the power switch device.

6. The voltage balancing circuit based on three-level topology according to claim 4, characterized in that: The power switch device is an insulated gate bipolar transistor.

7. The voltage balancing circuit based on three-level topology according to claim 1, characterized in that: The clamping circuit (200) comprises a clamping diode D1 and a clamping diode D2; One end of the clamping diode D1 is connected to the first clamping point; the other end of the clamping diode D1 is connected to one end of the clamping diode D2; The other end of the clamping diode D2 is connected to the second clamping point.

8. The voltage balancing circuit based on three-level topology according to claim 1, characterized in that: The filter circuit (100) comprises a capacitor C1 and a capacitor C2; One end of the capacitor C1 is connected to the positive electrode of the busbar; the other end of the capacitor C1 is connected to one end of the capacitor C2 and the clamping circuit (200) respectively; The other end of the capacitor C2 is connected to the negative electrode of the busbar.

9. A photovoltaic inverter, characterized in that: The photovoltaic inverter comprises a voltage balancing circuit based on a three-level topology as claimed in any one of claims 1 to 8.

10. A photovoltaic inverter system, characterized in that: The photovoltaic inverter system comprises a voltage balancing circuit based on a three-level topology as claimed in any one of claims 1 to 8.

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