Testing machine and multi-channel clock synchronization device thereof

Abstract

The utility model relates to a test machine and a multi-channel clock synchronization device thereof, the device comprises a frequency division module and more than two clock modules, and each clock module is connected with the frequency division module and a corresponding analog channel; and each clock module receives one path of clock signal, performs frequency adjustment on the received clock signal and outputs the clock signal to the corresponding analog channel. By correspondingly arranging the clock module for each analog channel to perform frequency adjustment, the clocks of the analog channels can be adjusted to be the same or different frequencies so as to adapt to different test requirements, and the test convenience is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a testing machine and a multi-channel clock synchronization device thereof. Background Art

[0002] In the manufacturing process of semiconductor devices, it is necessary to test the signal parameters generated by the device to verify whether the device can work normally. For example, for wireless RF devices, it is necessary to perform multi-channel testing on the device to be tested, or collect signals sent by the device to be tested through multiple channels. In this test scenario, there are strict requirements on the phase difference of the signals between channels. The phase difference between channels mainly depends on the phase difference between the working clocks of the two channels. In the traditional test scheme, the same clock module is used to output the clock, which is divided into multiple paths through the clock buffer and output to different channels, resulting in the clock signals between multiple channels must be of the same frequency. In the traditional test scheme, multiple channels must work at the same clock frequency, which has the disadvantage of low test convenience. Utility Model Content

[0003] Based on this, it is necessary to provide a test machine and a multi-channel clock synchronization device thereof that can improve the testing convenience in order to solve the above problems.

[0004] A first aspect of the present application provides a multi-channel clock synchronization device for a test machine, comprising:

[0005] Frequency division module, outputs multiple clock signals;

[0006] There are more than two clock modules, each of which is connected to the frequency division module and the corresponding analog channel; each of the clock modules receives one clock signal, adjusts the frequency of the received clock signal, and outputs it to the corresponding analog channel.

[0007] In one embodiment, the analog channel includes a high-frequency analog channel and a high-precision analog channel, the clock module includes a high-frequency clock module and a high-precision clock module, the high-frequency clock module connects the frequency division module and the corresponding high-precision analog channel, and the high-precision clock module connects the frequency division module and the corresponding high-precision analog channel.

[0008] In one of the embodiments, the multi-channel clock synchronization device further includes a controller, wherein the controller is connected to the frequency division module and each of the clock modules.

[0009] In one embodiment, the frequency division module includes a first buffer, a second buffer and a third buffer, the first buffer is connected to the second buffer, and the second buffer is connected to the corresponding third buffer; the first buffer outputs a single-ended clock signal to the second buffer, the second buffer converts the single-ended clock signal into a differential clock signal, and outputs it to the third buffer and the controller, and the third buffer divides the differential clock signal into multiple clock signals and sends them to the corresponding clock module.

[0010] In one embodiment, the clock module includes a phase-locked loop, a frequency divider and a clock buffer connected in sequence, the phase-locked loop is connected to the frequency divider module, the clock buffer is connected to the corresponding analog channel, and the controller is connected to the phase-locked loop, the frequency divider and the clock buffer; the controller controls the phase-locked loop and the frequency divider to configure the clock frequency, and the clock buffer outputs two clock signals with the same frequency and phase, which are respectively transmitted to the controller and the corresponding analog channel.

[0011] In one embodiment, the controller is a FPGA.

[0012] A second aspect of the present application provides a test machine, comprising an analog channel and the above-mentioned multi-channel clock synchronization device.

[0013] In one embodiment, the analog channel is an arbitrary waveform generator channel or a digitizer channel.

[0014] In one of the embodiments, the analog channel is also connected to a controller in the multi-channel clock synchronization device.

[0015] In one of the embodiments, the test machine further includes a clock generator connected to the frequency division module.

[0016] The above-mentioned test machine and its multi-channel clock synchronization device include a frequency division module and more than two clock modules, each clock module is connected to the frequency division module and the corresponding analog channel; each clock module receives a clock signal, adjusts the frequency of the received clock signal, and then outputs it to the corresponding analog channel. By setting the clock module corresponding to each analog channel to adjust the frequency, the clocks of each analog channel can be adjusted to the same or different frequencies to meet different test requirements, thereby improving the convenience of testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A structural block diagram of a multi-channel clock synchronization device of a test machine in one embodiment;

[0018] Figure 2 FIG. 4 is a structural schematic diagram of a testing machine in one embodiment. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0021] It is understood that the terms "first", "second", etc. used in this application can be used to describe various elements in this article, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have transmission of electrical signals or data with each other.

[0022] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0023] In one embodiment, Figure 1 As shown, a multi-channel clock synchronization device of a test machine is provided, including a clock module 100 and a frequency division module 200, the frequency division module 200 outputs multiple clock signals, the number of clock modules 100 is more than two, each clock module 100 is connected to the frequency division module 200, and the corresponding analog channel 300; each clock module 200 receives a clock signal, adjusts the frequency of the received clock signal, and then outputs it to the corresponding analog channel 300. Among them, the analog channel 300 can be an AWG (Arbitrary Waveform Generator) channel and a DIG (Digitizer) channel.

[0024] Specifically, the analog channel includes a high-frequency (HF) analog channel and a high-precision (HA) analog channel. The specific value ranges of high frequency and high precision are not unique and can be set according to actual needs. The two analog channels can be designed with different structures, or designed with the same structure and configured with different parameters, so that the two have different frequencies and precisions. The analog channel with high frequency is selected as the high-frequency analog channel, and the analog channel with high precision is selected as the high-precision analog channel. Correspondingly, if Figure 2 As shown, the clock module 100 includes a high-frequency clock module 110 and a high-precision clock module 120. The high-frequency clock module 110 is connected to the frequency division module 200 and the corresponding high-frequency analog channel, and the high-precision clock module 120 is connected to the frequency division module 200 and the corresponding high-precision analog channel. Taking the analog channel including both the AWG channel and the DIG channel as an example, the AWG channel may include a high-frequency AWG analog channel (HF AWG) and a high-precision AWG analog channel (HA AWG), and the DIG channel may also include a high-frequency DIG analog channel (HF DIG) and a high-precision DIG analog channel (HA DIG). The high-frequency clock module 110 is respectively set for the high-frequency AWG analog channel and the high-frequency DIG analog channel, and the clock output by the high-frequency clock module 110 is used as the working clock of the DAC (digital-to-analog converter) in the high-frequency AWG analog channel, and as the working clock of the ADC (analog-to-digital converter) in the high-frequency DIG analog channel. A high-precision clock module 120 is provided for the high-precision AWG analog channel and the high-precision DIG analog channel respectively, and the clock output by the high-precision clock module 120 is used as the working clock of the DAC in the high-precision AWG analog channel and as the working clock of the ADC in the high-precision DIG analog channel.

[0025] In addition, the multi-channel clock synchronization device may further include a controller 400, and the controller 400 is connected to the frequency division module 200 and each clock module 100. The controller 400 receives the differential clock signal output by the frequency division module 100 as the working clock, and the clocks of each analog channel 300 can be adjusted to the same or different frequencies by setting each clock module 100 through the controller 400. The controller 400 can be a device such as FPGA (Field-Programmable Gate Array), MCU (MicroControl Unit), CPU (Central Processing Unit), etc. In this embodiment, the controller 400 is FPGA.

[0026] In the multi-channel clock synchronization device of the test machine, each clock module 100 receives a clock signal output by the frequency division module 200, adjusts the frequency of the received clock signal, and then outputs it to the corresponding analog channel 300. By setting the clock module 100 to adjust the frequency for each analog channel 300, the clocks of each analog channel 300 can be adjusted to the same or different frequencies to meet different test requirements, thereby improving the convenience of testing.

[0027] The specific structure of the clock module 100 is not unique. In one embodiment, the clock module 100 includes a phase-locked loop, a frequency divider and a clock buffer connected in sequence, the phase-locked loop is connected to the frequency divider, the clock buffer is connected to the corresponding analog channel, and the controller is connected to the phase-locked loop, the frequency divider and the clock buffer; the controller controls the phase-locked loop and the frequency divider to configure the clock frequency, and the clock buffer outputs two clock signals with the same frequency and phase, which are respectively transmitted to the controller and the corresponding analog channel.

[0028] like Figure 2 As shown, the high-frequency clock module 110 includes a phase-locked loop 112, a frequency divider 114, and a clock buffer 116 connected in sequence, the phase-locked loop 112 is connected to the frequency divider module 200, and the clock buffer 116 is connected to the corresponding high-frequency AWG analog channel or high-frequency DIG analog channel. Specifically, the frequency divider module 200 is connected to the phase-locked loop 112 through an LVCMOS interface, the phase-locked loop 112 is connected to the frequency divider 114 through an LVDS interface, the frequency divider 114 is connected to the clock buffer 116 through an LVPECL interface, and the clock buffer 116 is connected to the corresponding high-frequency AWG analog channel or high-frequency DIG analog channel through an LVDS interface.

[0029] The high-precision clock module 120 includes a phase-locked loop 122, a frequency divider 124, and a clock buffer 126 connected in sequence, the phase-locked loop 122 is connected to the frequency divider module 200, and the clock buffer 126 is connected to the corresponding high-precision AWG analog channel or high-precision DIG analog channel. Specifically, the frequency divider module 200 is connected to the phase-locked loop 122 via an LVCMOS interface, the phase-locked loop 122 is connected to the frequency divider 124 via an LVDS interface, the frequency divider 124 is connected to the clock buffer 126 via an LVPECL interface, and the clock buffer 126 is connected to the corresponding high-precision AWG analog channel or high-precision DIG analog channel via an LVDS interface.

[0030] The controller 400 controls the phase-locked loop and frequency divider in each clock module 100 through a digital interface, and can configure different clock frequencies according to requirements. The controller 400 can also send a synchronization trigger signal to control the phase-locked loop in the multi-channel clock module 100 to output the same-phase clock, thereby improving the test accuracy. The final clock buffer in the clock module 100 outputs two clock signals with the same frequency and phase, one of which is provided to the ADC / DAC of the analog channel 300 as the working clock, and the other is provided to the controller 400 as the synchronization clock for the controller 400 to synchronize the data with the analog channel 300.

[0031] Further, continue to refer to Figure 2 The frequency division module 200 may include a first buffer 210, a second buffer 220 and a third buffer 230, the first buffer 210 is connected to the second buffer 220, and the second buffer 220 is connected to the corresponding third buffer 230; the first buffer 210 outputs a single-ended clock signal to the second buffer 220, the second buffer 220 converts the single-ended clock signal into a differential clock signal, and outputs it to the third buffer 230 and the controller 400, and the third buffer 230 divides the differential clock signal into multiple clock signals and sends them to the corresponding clock module 100.

[0032] Specifically, the number of the second buffers 220 may be one or more, and each second buffer 220 is connected to the first buffer 210. Of the two third buffers 230 corresponding to each second buffer 220, one third buffer 230 is connected to the high-frequency AWG analog channel or the high-frequency DIG analog channel through the corresponding high-frequency clock module 110, and the other third buffer 230 is connected to the high-precision AWG analog channel or the high-precision DIG analog channel through the corresponding high-precision clock module 120. The first buffer 210 can be connected to the clock generator 500 of the test machine, receive the user clock output by the clock generator 500, and the user clock outputs multiple single-ended clock signals to the corresponding second buffer 220 through the first buffer 210. The second buffer 220 converts the single-ended clock signal into three differential clock signals, which are used as the working clocks of the digital circuit of the controller 400, the high-frequency analog channel, and the high-precision analog channel. The two differential clock signals used as the high-frequency analog channel and the high-precision analog channel are output to the corresponding third buffer 230 respectively. The third buffer 230 divides the differential clock signal into multiple clock signals and outputs them to each clock module 100 respectively. The phase-locked loop in the clock module 100 receives the clock signal from the third buffer 230, outputs a frequency-adjustable clock to the frequency divider, and the frequency divider outputs a frequency-adjustable clock to the final clock buffer. The clock buffer outputs two clock signals of the same frequency and phase, which are respectively transmitted to the controller and the corresponding high-frequency analog channel / high-precision analog channel. Through the combination of the phase-locked loop and the frequency divider, a high-performance, high-resolution clock signal can be obtained and output to the final clock buffer, and the clock resolution can reach 1uHz.

[0033] In one embodiment, a test machine is provided, comprising an analog channel and the above-mentioned multi-channel clock synchronization device. The analog channel is an arbitrary waveform generator channel or a digitizer channel. The analog channel is also connected to a controller in the multi-channel clock synchronization device. Figure 2 As shown, the arbitrary waveform generator channel may include a high-frequency AWG analog channel (HFAWG) and a high-precision AWG analog channel (HA AWG), and the digitizer channel may also include a high-frequency DIG analog channel (HF DIG) and a high-precision DIG analog channel (HA DIG).

[0034] Further, the tester also includes a clock generator 500 connected to the frequency division module 200. The clock generator 500 can be connected to the backplane of the tester, receive the input clock of the backplane, output the system clock and the user clock, effectively reduce the jitter of the input clock, improve the phase noise, and provide a stable and high-quality clock source. The clock generator 500 can be set according to actual needs to adjust the frequency of the system clock and the user clock. The system clock output by the clock generator 500 is used to provide a working clock for the digital part of the tester board, and the user clock output by the clock generator 500 is sent to the first buffer 210 of the frequency division module 200. The first buffer 210 outputs a single-ended clock signal to the second buffer 220, and the second buffer 220 converts the single-ended clock signal into a differential clock signal and sends it to the controller 400 and the multi-channel clock module 100. The multi-channel clock modules 100 use a synchronous trigger signal to achieve clock synchronization, and the working clocks can be adjusted independently between the multiple clock modules 100. In this embodiment, the clocks of the tester are all output through the clock conversion from the backplane, which can effectively reduce the measurement error caused by different clock sources.

[0035] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A multi-channel clock synchronization device for a test machine, characterized in that: include: Frequency division module, outputs multiple clock signals; More than two clock modules, each of which is connected to the frequency division module and a corresponding analog channel; Each of the clock modules receives one clock signal, adjusts the frequency of the received clock signal, and then outputs the received clock signal to the corresponding analog channel.

2. The device according to claim 1, characterized in that The analog channel includes a high-frequency analog channel and a high-precision analog channel, the clock module includes a high-frequency clock module and a high-precision clock module, the high-frequency clock module is connected to the frequency division module and the corresponding high-frequency analog channel, and the high-precision clock module is connected to the frequency division module and the corresponding high-precision analog channel.

3. The device according to claim 1 or 2, characterized in that: It also includes a controller, which is connected to the frequency division module and each of the clock modules.

4. The device according to claim 3, characterized in that The frequency division module includes a first buffer, a second buffer and a third buffer, the first buffer is connected to the second buffer, and the second buffer is connected to the corresponding third buffer; the first buffer outputs a single-ended clock signal to the second buffer, the second buffer converts the single-ended clock signal into a differential clock signal, and outputs it to the third buffer and the controller, and the third buffer divides the differential clock signal into multiple clock signals and sends them to the corresponding clock module.

5. The device according to claim 3, characterized in that The clock module comprises a phase-locked loop, a frequency divider and a clock buffer connected in sequence, the phase-locked loop is connected to the frequency divider module, the clock buffer is connected to the corresponding analog channel, and the controller is connected to the phase-locked loop, the frequency divider and the clock buffer; The controller controls the phase-locked loop and the frequency divider to configure the clock frequency, and the clock buffer outputs two clock signals with the same frequency and phase, which are respectively transmitted to the controller and the corresponding analog channel.

6. The device according to claim 3, characterized in that The controller is FPGA.

7. A testing machine, characterized in that: The invention comprises an analog channel and a multi-channel clock synchronization device as claimed in any one of claims 1 to 6.

8. The testing machine according to claim 7, characterized in that: The analog channel is an arbitrary waveform generator channel or a digitizer channel.

9. The testing machine according to claim 7, characterized in that: The analog channel is also connected to a controller in the multi-channel clock synchronization device.

10. The testing machine according to any one of claims 7 to 9, characterized in that: Also included is a clock generator connected to the frequency division module.

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