Three-dimensional memory array and field effect transistor device

Abstract

The embodiment of the utility model provides a field effect transistor capable of selectively switching between a first state and a second state. The field effect transistor comprises a source electrode region, a drain electrode region and a channel region arranged between the source electrode region and the drain electrode region; a gate arranged to selectively receive a bias voltage, the bias voltage switching the field effect transistor between first and second states; the memory structure between the gate and the channel region includes an anti-ferroelectric first portion and a ferroelectric second portion, both portions being polarized in a first direction when the field effect transistor is in a first state; and a depolarization dielectric layer disposed proximate to the memory structure. When the field effect transistor is set to the first state, the depolarization dielectric layer destabilizes polarization of the second portion of the memory structure while maintaining polarization of the first portion. Incorporation of an antiferroelectric material in a memory structure suppresses weak erase issues, particularly achieving well controlled erase states during repeated erases.

Description

Technical Field

[0001] The embodiments of the utility model relate to a three-dimensional memory array and a field effect transistor device, and in particular to a three-dimensional memory array and a field effect transistor device including antiferroelectric memory. Background Art

[0002] The following relates to the semiconductor field and specifically to anti-ferroelectric (AFe) memory or field-effect-transistor (FET) or other similar AFe components, semiconductor devices including AFe components and / or manufacturing methods thereof. Utility Model Content

[0003] The embodiment of the utility model provides a field effect transistor device selectively switched between a first state and a second state, comprising: a source and a drain region, a channel region arranged between the source and the drain region, a gate arranged to selectively receive a bias voltage to selectively switch the field effect transistor device between the first state and the second state, a storage structure arranged between the gate and the channel region, and at least one depolarized dielectric layer arranged close to the storage structure. The storage structure comprises an antiferroelectric first portion and a ferroelectric second portion, and when the field effect transistor device is in the first state, the first portion and the second portion are polarized along a first direction.

[0004] The embodiment of the utility model provides a three-dimensional storage array including a metallization layer and a field effect transistor stack. The metallization layer includes a patterned metal layer separated by an intermetallic dielectric material and an intermediate layer via that passes through the intermetallic dielectric material and interconnects the patterned metal layer, the field effect transistor stack is separated by the intermetallic dielectric material, each of the field effect transistor stack includes a two-dimensional array of field effect transistor devices as described above, and the field effect transistor devices are electrically connected to the metallization layer.

[0005] An embodiment of the utility model provides a three-dimensional storage array including a three-dimensional array of field effect transistor devices as described above, wherein the gate of the field effect transistor includes an electrically conductive word line, the source region includes an electrically conductive source line, and the drain region includes an electrically conductive bit line, wherein the electrically conductive source line and the electrically conductive bit line are perpendicular to the electrically conductive word line.

[0006] The embodiment of the utility model provides a three-dimensional memory array including a plurality of electrically conductive word lines, a plurality of electrically conductive bit lines and electrically conductive source lines perpendicular to the electrically conductive word lines, and an array of memory cells. Each of the memory cells includes an oxide semiconductor channel region electrically connected between one of the electrically conductive source lines and one of the electrically conductive bit lines, a memory film disposed between one of the electrically conductive word lines and the oxide semiconductor channel region, and a depolarizing dielectric layer disposed on at least one side of the memory film. The memory film includes a first antiferroelectric domain and a second ferroelectric domain, and when the memory cell is switched to the first state, the first antiferroelectric domain and the second ferroelectric domain are polarized along a first direction. When the memory cell is set to the first state, the depolarizing dielectric layer generates an electric field, and the electric field weakens the polarization of the second ferroelectric domain of the memory film while maintaining the polarization of the first antiferroelectric domain of the memory film.

[0007] Based on the above, by applying a first bias voltage, the storage film or layer can be selectively polarized and / or switched to achieve a first state (programmed state). By applying a second bias voltage, the storage film or layer can be selectively depolarized and / or switched to achieve a second state (erased state). Incorporating antiferroelectric materials and / or significant antiferroelectric domains in the storage film or layer can potentially suppress the so-called weak erase problem, especially during repeated erasing and writing, and achieve a well-controlled erased state. In the programmed state, the depolarizing dielectric layer is used to generate a depolarizing electric field having a direction substantially opposite to the polarization direction of the dipoles in the storage film (e.g., in the ferroelectric and antiferroelectric domains). In this way, the polarization of the storage film (e.g., in the ferroelectric domain) is somewhat unstable while maintaining the polarization of the antiferroelectric domain, so that, for example, a relatively low bias or switching voltage can be used to more easily and / or reliably achieve switching of the erased state than when the depolarizing dielectric layer is not used or does not exist. In the erased state, the depolarization electric field generated by the depolarized dielectric layer is zero or essentially zero, so that it will not significantly affect the polarization state in the antiferroelectric domains of the storage film, that is, the polarization state in the antiferroelectric domains is essentially zero and / or the dipoles therein have approximately random polarization directions.

[0008] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A Schematically illustrated is a schematic cross-sectional view taken at the channel region of a Fe / AFe-FET according to some embodiments disclosed herein.

[0010] Figures 1B-1F A series of cross-sectional views are provided to illustrate the Figure 1A Fabrication sequence of the Fe / AFe-FET.

[0011] Figure 2 Schematically shows Figure 1A Magnified view of the identification area shown in .

[0012] Figure 3 Schematically illustrated is a schematic cross-sectional view taken at the channel region of a Fe / AFe-FET according to an alternative embodiment disclosed herein.

[0013] Figure 4 Schematically illustrated is a schematic cross-sectional view taken at the channel region of a Fe / AFe-FET according to another alternative embodiment disclosed herein.

[0014] Figure 5 is a table with diagrammatic illustrations of schematic cross-sectional views taken at the source / drain regions of an Fe / AFe-FET according to some embodiments disclosed herein, showing corresponding program (PRG) and erase (ERS) states and corresponding polarizations of the Fe and AFe domain portions of the storage structure in their respective states.

[0015] Figure 6 Shown is a graph of switching current-voltage (IV) curves of corresponding Fe and AFe domains according to some suitable embodiments of Fe / AFe-FETs disclosed herein.

[0016] Figure 7 An integrated circuit (IC) in which a Fe / AFe-FET is embedded and / or incorporated according to some suitable embodiments disclosed herein is schematically illustrated.

[0017] Fig. 8A and Figure 8B Schematically illustrated are a perspective view and a circuit diagram of a memory array according to some embodiments disclosed herein.

[0018] Figures 9A to 9K A method of manufacturing a memory array (eg, Fig. 8A and Figure 8B The method flow of the storage array shown in FIG.

[0019] Description of Reference Numerals

[0020] 52: insulator material / dielectric layer; 54: spacer dielectric material; 54L, 408: isolation material; 72: word line / conductor; 72L, 303: dielectric material; 90: multilayer structure / stack; 98: insulator material; 100: Fe / AFe FET / device; 102: oxide semiconductor layer; 104: storage film or layer; 106: gate; 108, 108b: depolarization dielectric layer; 109a: tungsten gel layer; 109b: high carrier concentration layer; 110: conductive material layer; 120: trench; 122, 126: opening; 124: mask; 128: contact via; 130: metallization layer; 200: integrated circuit / IC; 202: logic device; 204: component; 206: silicon substrate; 208: Fe / AFe FET layer; 210: multi-layer metallization layer; 212: patterned metal layer; 214: intermetallic dielectric material / IMD material; 216: via; 300: memory array; 302: memory cell; 304: transistor; 306: bit line / conductor; 308: source line / conductor; 312: ladder structure; 314: landing point; 406, A1, A2, A3: arrows; +VC: control voltage; A: detail / region; B: detail / illustration; BL0, BL1, BL2, BL3, BL4, BL5: bit line; D: drain region; J: current; S: source region; SL0, SL1, SL2, SL3, SL4, SL5: source line; THK1, THK2, THK3: thickness; V DE : voltage drop; WL0, WL1, WL2: word lines. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0022] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0023] Generally speaking, a Ferroelectric Random-Access Memory (FeRAM) device has a metal / ferroelectric / metal (MFM) layer structure that includes a ferroelectric (Fe) layer disposed between top and bottom electrodes. FeRAM may incorporate a ferroelectric field-effect-transistor (Fe-FET), which is a FET that includes a ferroelectric material sandwiched between the gate electrode and the source-drain conduction region (i.e., the channel) of the device. The electric field polarization in the ferroelectric causes this type of device to generally maintain the state of the transistor (e.g., on or off) in the absence of a sustained electrical bias. A FeRAM device is a type of non-volatile Random-Access Memory (RAM) that is configured to store data values ​​based on a reversible switching process between polarization states that occurs due to ferroelectric properties, i.e., the crystal structure of the ferroelectric layer can change when an electric field is present. For example, in a FeRAM cell, when a first bias voltage (e.g., a negative bias voltage) is applied to generate an electric field applied to the Fe layer, the atoms, dipoles, or other components of the ferroelectric layer may be caused to shift to a first direction, thereby generating a first resistance indicating a first data value (e.g., logic "1"), and when a different second bias voltage (e.g., a positive bias voltage) is applied to generate an electric field applied to the Fe layer, the atoms, dipoles, or other components of the ferroelectric layer may be caused to shift to a second direction (different from the first direction), which generates a second resistance (different from the first resistance) indicating a second data value (e.g., logic "0").

[0024] FeRAM devices have many advantages. FeRAM is highly resistant to power interruptions and / or magnetic interference and is generally a reliable non-volatile storage. FeRAM can exhibit low power consumption, fast write performance, high maximum read / write endurance and / or long data storage time.

[0025] According to some suitable embodiments, a semiconductor memory device is disclosed herein, which uses a memory film including a material having a region or domain that exhibits and / or possesses antiferroelectric (AFe) properties. Suitably, the memory film may also include a region or domain that exhibits and / or possesses ferroelectric (Fe) properties. In some suitable embodiments, the semiconductor memory device may be Fe and / or AFe memory, for example, including a Fe and / or AFe field effect transistor (Fe / AFe-FET) and an oxide semiconductor as a channel material. In practice, the channel region of the field effect transistor (FET) may be disposed between the corresponding source and drain regions of the FET, and the memory film may be arranged close to or near the channel region, for example, between a gate, a gate electrode or other suitable gate structure and a channel or a channel region of the FET.

[0026] In some suitable embodiments, the semiconductor memory device may be a type of non-volatile random access memory (RAM) configured to store data values ​​based on a process of reversible switching between polarization states due to the Fe / AFe characteristics of the memory film. Suitably, the semiconductor memory device disclosed herein has many advantages. For example, it can be significantly resistant to power outages and / or magnetic interference, and is therefore a reliable non-volatile storage. It can also exhibit low power consumption, fast write performance, high maximum read / write endurance and / or long data storage time.

[0027] In some suitable embodiments, the memory layer may be a hafnium-zirconium oxide (HfZrO or HZO) film having a relatively high percentage of Zr, such as in a range between about 50% Zr and about 80% Zr (including the end values). In practice, the memory film or layer may include a crystalline structure and / or crystal grains of different phases and / or otherwise include regions that exhibit or possess Fe behavior (also referred to herein as Fe domains of the memory film) and / or alternative AFe behavior (also referred to herein as AFe domains of the memory film). For example, in an HZO memory film, the orthorhombic phase (O phase) generally exhibits or possesses Fe behavior and may represent Fe domains, while the tetragonal phase (T phase) generally exhibits or possesses AFe behavior and may represent AFe domains. Advantageously, an increase in the Zr percentage of the HZO memory film generally increases the ratio of AFe domains to non-AFe domains, however, the Fe domains generally remain larger than the AFe domains.

[0028] In some suitable embodiments, by applying a first bias voltage (e.g., a positive bias voltage), the memory film or layer can be selectively polarized and / or switched to achieve a first state, nominally referred to herein as a programming (PRG) state. Alternatively, by applying a second bias voltage (e.g., a negative bias voltage), the memory film or layer can be selectively depolarized and / or switched to achieve a second state, nominally referred to herein as an erased (ERS) state. Advantageously, incorporating AFe materials and / or significant AFe domains in the memory film or layer can potentially suppress the so-called weak erase problem, especially during repeated erasing and writing, for example, as opposed to strictly Fe materials and / or Fe domains, and achieve a well-controlled ERS state. For example, the AFe material and / or domain can suppress the weak ERS state problem caused by half-butterfly polarization-voltage (PV) curve bias operation, and achieve better device performance and limited data changes.

[0029] In some suitable embodiments, a depolarizing dielectric layer is disposed adjacent one or both sides of the Fe / AFe storage film. In practice, the use of a depolarizing dielectric layer has the advantage of facilitating the destabilization of the PRG state polarization contribution of the Fe domains of the storage film, which would otherwise be too stable to be effectively and / or efficiently destroyed or depolarized to the ERS state (which may be a relatively low magnitude deviation) using the applied bias intended for switching. Suitably, in the PRG state, the depolarizing dielectric layer is used to generate a depolarizing electric field having a direction substantially opposite to the polarization direction of the dipoles in the storage film (e.g., in the Fe and AFe domains). In this way, the polarization of the storage film (e.g., in the Fe domains) is somewhat destabilized while the polarization of the AFe domains is maintained, such that, for example, switching of the ERS state can be more easily and / or reliably achieved using a relatively low bias or switching voltage than when the depolarizing dielectric layer is not employed or present. In the ERS state, the depolarization electric field generated by the depolarized dielectric layer is zero or essentially zero, thereby not significantly affecting the polarization state in the AFe domain of the storage film, i.e., the polarization state in the AFe domain is zero or essentially zero and / or the dipoles therein have approximately random polarization directions.

[0030] According to some embodiments described herein, Figure 1A 1 shows a schematic cross-sectional view of a Fe / AFe-FET 100 taken at the channel region of the Fe / AFe-FET 100. In practice, the channel region is appropriately disposed between the source region S and the drain region D of the Fe / AFe-FET 100. Figure 1A In one non-limiting illustrative embodiment shown, the source region S and the drain region D may include an electrically conductive material such as tungsten coated with a tungsten paste layer 109a (eg, a titanium nitride (TiN) layer) and a high carrier concentration layer 109b to reduce contact resistance.

[0031] In some suitable embodiments, the channel region may be formed and / or otherwise left in the material of the oxide semiconductor layer 102, such as but not limited to zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, etc. In some suitable embodiments, the oxide semiconductor layer 102 may have a thickness THK1 in a range between about 2 nanometers (nm) and about 20 nm (including end values). According to some suitable embodiments, the oxide semiconductor layer 102 may be suitably formed by, for example, but not limited to, plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other suitable material deposition techniques.

[0032] like Figure 1A As shown, according to some suitable embodiments, the storage film or layer 104 is disposed between the gate electrode or gate electrode 106 of the Fe / AFe-FET 100 and the oxide semiconductor layer 102. In some suitable embodiments, the gate electrode or gate electrode 106 may be formed of and / or include a metal, an alloy or other suitable electrically conductive material. For example (but not limited to), the gate electrode or gate electrode 106 may be a polysilicon material, a silicide material, a metal composite (such as tungsten nitride (WN), titanium nitride (TiN) or tantalum nitride (TaN)), a metal (such as aluminum (Al)), a combination thereof and / or an alloy thereof and / or the like.

[0033] In some suitable embodiments, the memory film or layer 104 is formed of AFe and / or includes an AFe material, for example, including a significant AFe domain portion in addition to the Fe domain portion and / or the non-AFe domain portion. In some suitable embodiments, the AFe domain portion accounts for a range of about 2% to about 14% (including the endpoints) of the memory film or layer 104, and the Fe domain portion accounts for a range of about 88% to about 84% (including the endpoints) of the memory film or layer 104, which is found to provide the best performance through experiments. In practice, the remaining percentage of the memory film or layer 104 can be a non-AFe domain material, for example, having a non-AFe crystalline phase. In some suitable embodiments, the memory film or layer 104 can include and / or be composed of, for example, but not limited to, HZO, hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfCeO), combinations thereof, and the like. Suitably, for example, when the storage film or layer 104 is HZO, zirconium (Zr) may be in the range between about 50% and about 80% (including the endpoint values), which has been found experimentally to provide optimal performance. In some suitable embodiments, the storage film or layer 104 may have a thickness THK2 in the range between about 2 nm and about 20 nm (including the endpoint values). According to some suitable embodiments, the storage film or layer 104 may be suitably formed by, for example, but not limited to, plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD) or other suitable material deposition techniques.

[0034] According to some suitable embodiments, the depolarization dielectric layer 108 may be formed and / or disposed adjacent to or otherwise close to (e.g., in contact with) a first side of the storage film or layer 104, such as near a channel region of the Fe / AFe-FET 100. Figure 1AAs shown, the depolarization dielectric layer 108 is disposed on the channel side of the storage film or layer 104, that is, between the oxide semiconductor layer 102 and the storage film or layer 104. In some suitable embodiments, the depolarization dielectric layer 108 may include and / or be formed of, for example, but not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), combinations thereof, etc. In some suitable embodiments, the depolarization dielectric layer 108 may have a thickness THK3 in the range between about 0.1 nm and about 2 nm (including the end values). (Note that the depolarization dielectric layer 108 may be a discontinuous layer, in which case the thickness is an effective thickness representing the average thickness of the layer). It has been experimentally found that for values ​​of THK3 greater than about 2 nm, the time-zero (or initial state) ferroelectric properties (such as the storage window) are significantly reduced. Without being limited to any particular theory of operation, it is believed that this may be due to a phase change of HZO if the thickness THK3 of the depolarization dielectric layer 108 exceeds about 2 nm. According to some suitable embodiments, the storage film or layer 104 may be suitably formed by, for example but not limited to, plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD) or other suitable material deposition techniques.

[0035] refer to Figures 1B-1F , a series of cross-sectional views showing the Figure 1A 1. The fabrication sequence of the Fe / AFe-FET 100. Figure 1B A gate electrode or gate 106 is shown. As previously described, the gate electrode or gate 106 may include a metal, an alloy, or other suitable electrically conductive material. For example, but not limited to, the gate electrode or gate 106 may be a polysilicon material, a silicide material, a metal composite (e.g., tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN)), a metal (e.g., aluminum (Al)), a combination and / or alloy thereof, and / or the like. In some embodiments, the gate electrode or gate 106 may include a patterned electrically conductive layer formed in a metallization stack as part of a back end-of-line (BEOL) or middle end-of-line (MEOL) process.

[0036] Figure 1CThe storage film or layer 104 is shown disposed on the gate electrode or gate 106. As previously detailed, in some non-limiting illustrative embodiments, the storage film or layer 104 may include a hafnium-zirconium oxide (HfZrO or HZO) film having a relatively high percentage of Zr, such as in a range between about 50% Zr and about 80% Zr (including the end values). Although HZO is described as an exemplary embodiment, it is contemplated that the storage film or layer 104 may include another type of ferroelectric material, such as SrBi2Ta2O9, PbZrxTi 1-x O3 or BaTiO3.

[0037] Figure 1D It is shown that a depolarizing dielectric layer 108b is further formed on the storage film or layer 104. In the illustrative example, the depolarizing dielectric layer 108b is disposed on at least a portion of the storage film or layer 104. As previously described, the depolarizing dielectric layer 108 may be, for example, Al2O3, HfO2, ZrO2, or other layers having a thickness in the range of 0.1 nm to 2 nm, and may be a discontinuous layer in some embodiments. As previously described, the deposition may be performed using PVD, PECVD, ALD, PEALD, or another suitable material deposition technique. In the illustrative example, the depolarizing dielectric layer 108b is formed as a blanket layer, which will be patterned together with the oxide semiconductor layer 102 (see below). Figure 1E ).

[0038] Figure 1E The oxide semiconductor layer 102 is shown disposed on the depolarization dielectric layer 108 and patterned by photolithography. As previously mentioned, the oxide semiconductor material of the oxide semiconductor layer 102 may include ZnO, InWO, InGaZnO, InZnO, ITO, combinations thereof, etc., and may be formed by deposition techniques such as PVD, PECVD, ALD, PEALD, etc. Figure 1D and Figure 1E In an illustrative method, the two layers (108 and 102) are suitably deposited as blanket layers, followed by a photolithographic process to pattern the depolarization dielectric layer 108 and the oxide semiconductor layer 102, such as Figure 1E This is merely an illustrative example, and other methods may be used, such as patterning by photolithography to define the openings in which the layers are deposited.

[0039] Figure 1F The final Fe / AFe-FET 100 provided by forming the source region S and the drain region D is shown. In the illustrative example where the source region S and the drain region D contain tungsten (W), it is necessary to form a high carrier concentration layer 109b and a tungsten paste layer 109a for reducing contact resistance. Appropriate photolithography processing can be performed to define the areas of the source region S and the drain region D.

[0040] In addition to the manufacturing steps outlined above as non-limiting illustrative examples, the process for forming the Fe / AFe-FET 100 may include a thermal annealing step to produce ferroelectric crystallization of the storage film or layer 104. Taking HZO as an example, the ferroelectric phase of HZO is an orthorhombic phase, which can provide a ferroelectric response due to its non-centrosymmetric crystal structure. However, the deposited storage film or layer 104 may be amorphous or may have a mixed phase, such as a mixture of a tetragonal phase and / or a monoclinic phase and / or an orthorhombic phase. Characterization techniques such as X-ray diffraction (XRD) and / or electron backscatter diffraction (EBSD) can be used to evaluate the phase separation of the storage film or layer 104. If an insufficient portion of the deposited storage film or layer 104 is in the ferroelectric phase, ferroelectric phase crystallization can be spontaneously obtained by annealing at an appropriately high temperature for a sufficient time interval (in some cases, for example, about 550°C for about 5 minutes may be sufficient). Such thermal annealing can generally be performed at any time after the formation of the storage film or layer 104, and the timing of the annealing in the overall process flow is selected based on factors such as the sensitivity and convenience of the subsequently formed layers or structures to annealing. Figure 7 In a three-dimensional array structure of Fe / AFe FET 100, it may be beneficial to perform a single ferroelectric phase crystallization annealing after fabricating the entire three-dimensional array structure).

[0041] According to some embodiments disclosed herein, Figure 3 and Figure 4 Shows Figure 1A Some alternative configurations of the Fe / AFe-FET 100 shown in FIG. Figure 3 As shown, the depolarization dielectric layer 108 may be formed and / or disposed adjacent to or otherwise close to (eg, in contact with) the second side of the storage film or layer 104. More specifically, as shown in FIG. Figure 3 As shown, the depolarization dielectric layer 108 is disposed on the gate side of the storage film or layer 104, that is, between the gate electrode or gate 106 and the storage film or layer 104. Figure 4 As shown, the depolarization dielectric layer 108 may be formed and / or disposed adjacent to, in contact with, or otherwise close to both sides of the storage film or layer 104. More specifically, as shown in FIG. Figure 4 As shown, the first depolarization dielectric layer 108 is arranged on the channel side of the storage film or layer 104, that is, between the oxide semiconductor layer 102 and the storage film or layer 104, and the second depolarization dielectric layer 108 is arranged on the gate side of the storage film or layer 104, that is, between the gate electrode or gate 106 and the storage film or layer 104.

[0042] Now pay attention Figure 2 , showing Figure 1AAn enlarged and / or magnified view of the region A identified in FIG. Figure 2 As shown, the storage film or layer 104 may have a crystalline structure, for example, including grains or portions representing AFe domains, etc. and grains or portions representing Fe domains, etc. Suitably, in an embodiment where the storage film or layer 104 is HZO, the AFe domains may be represented by T-phase grains or portions and / or T-phase crystalline structures, and the Fe domains may be represented by O-phase grains or portions and / or O-phase crystalline structures.

[0043] Figure 2 Illustration B of FIG. 1 shows a table of the operating states (i.e., PRG states and ERS states) in the AFe domain and the Fe domain of the storage film or layer 104, respectively. As can be seen from the PRG column of the table, the depolarized dielectric layer 108 generates an electric field in a direction (e.g., represented by arrow A1 shown in the depolarized dielectric layer 108), which is generally opposite to the polarization direction and / or arrangement of the dipoles in the Fe and AFe domains (e.g., represented by arrow A2 shown in the storage film or layer 104). As can be seen from the ERS column of the table, the depolarized dielectric layer 108 does not generate a significant electric field or no electric field (e.g., represented by the lack of arrows in the depolarized dielectric layer 108). Therefore, in the AFe domain, the polarization is zero or zero or substantially zero, that is, the dipoles are substantially random or randomly arranged (e.g., represented by arrows A3 pointing in multiple different directions shown in the storage film or layer 104).

[0044] Figure 5 Shows Figure 2 Another version of the table shown in illustration B of Figure 5, a schematic cross-sectional view of the source and / or drain regions of the Fe / AFe-FET 100 is shown. As shown, according to some suitable embodiments, the metal or other suitable conductive material layer 110 may represent a terminal for providing electrical access to the source / drain of the Fe / AFe-FET 100. In some suitable embodiments, as shown in the PRG state column of the table, a first bias (+VG) may be applied, for example, through the gate electrode or gate 106. Alternatively, as shown in the ERS state column of the table, a second bias (-VG) may be applied, for example, through the gate electrode or gate 106. Similarly, it can be seen from the PRG column of the table that the depolarization dielectric layer 108 generates an electric field in a direction (e.g., represented by arrows A1 shown in the depolarization dielectric layer 108), which is generally opposite to the polarization direction and / or alignment of the dipoles in the Fe and AFe domains (e.g., represented by arrows A2 shown in the storage film or layer 104). As can be seen from the ERS column of the table, the depolarized dielectric layer 108 generates no significant electric field or no electric field (e.g., as shown by the lack of arrows in the depolarized dielectric layer 108). Therefore, in the AFe domain, the polarization is zero or zero or substantially zero, that is, the dipoles are substantially random or randomly arranged (e.g., as shown by arrows A3 pointing in multiple different directions shown in the storage film or layer 104).

[0045] Back to Figure 1A In some suitable embodiments, the thickness THK3 of the depolarization dielectric layer 108 may be in the range between about 0.1 nm and about 2 nm (including the end values), wherein in some cases, the thickness THK3 may be the effective thickness of the discontinuous layer. In practice, the magnitude of the electric field generated by the depolarization dielectric layer 108 will be equal to the voltage drop (V DE ) divided by THK3, that is, V DE / THK3.

[0046] Figure 6 The switching current IV curves of the Fe and AFe domains of the storage film or layer 104 are shown. Figure 6 , the voltage V is plotted along the x-axis of the graph in volts (V), and the current J is plotted along the y-axis of the graph. As shown, a control voltage +VC for each of the Fe and AFe domains is shown. In a non-limiting illustrative example, +VC is approximately 1.0-1.4V for the Fe domain and approximately 1.8-2.2V for the AFe domain. According to some suitable embodiments, the thickness THK3 of the depolarization dielectric layer 108 is appropriately optimized and / or otherwise selected so that under the PRG bias of +VG, for the AFe domain, the voltage drop V across the depolarization dielectric layer 108 is DELess than +VC, and for the Fe domain, greater than but close enough to +VC, for example, about 1.1-1.5 V. Advantageously, in this way, the depolarization dielectric layer 108 of appropriate thickness THK3 has the potential to control the depolarization effect occurring in the Fe domain (e.g., destabilize the polarization of the Fe domain) while maintaining the PRG state in the AFe domain.

[0047] Reference now Figure 7 In some suitable embodiments, the Fe / AFe-FET 100 can be easily embedded and / or incorporated into an integrated circuit (IC) 200 or a chip as a memory device. Figure 7 In an illustrative example, the IC 200 may suitably include one or more logic devices 202, such as, but not limited to, static random access memory (SRAM), and / or one or more other devices or components 204, such as, but not limited to, interface devices, input / output components, analog components, etc. In a non-limiting illustrative example, the one or more logic devices 202 and / or other devices or components 204 may be formed in and / or on the silicon substrate 206 during front-end processing on the silicon substrate 206.

[0048] like Figure 7 As further shown, the IC 200 may also include a three-dimensional (3D) memory array having a plurality of stacked memory cells including the Fe / AFe FET devices 100. In some suitable embodiments, each Fe / AFe FET layer 208 includes a two-dimensional array of Fe / AFe FET devices 100 (where Figure 7 Only one dimension is visible in the side view of the IC 200). The Fe / AFe FET layer 208 is integrated or embedded in a multi-layer metallization layer 210 fabricated during middle of the line (MEOL) and / or back end of the line (BEOL) processing. The multi-layer metallization layer 210 includes patterned metal layers 212 separated by intermetallic dielectric (IMD) materials 214. Interlayer vias 216 pass through the IMD materials 214 to provide electrical interconnection between the patterned metal layers 212. Depending on the design of the IC 200, the patterned metal layers 212 appropriately define or form electrical traces that, together with the connecting vias 216, provide electrical connections between the logic device 202, the other devices 204, and the Fe / AFe FET device 100. A 3D memory array including Fe / AFe FET devices 100 may advantageously provide high density embedded memory for IC 200 with reduced manufacturing complexity compared to some other embedded memory designs, such as those whose cells include FeRAM capacitors driven by separate transistors. Figure 7Detail A shows an enlarged cross-sectional view of a Fe / AFe FET device 100, corresponding to the previous reference Figure 1A As shown in detail A, the inclusion of a depolarizing dielectric layer 108 in the 3D embedded storage Fe / AFe FET device 100 provides the 3D embedded storage Fe / AFe FET device 100 with the advantages described above, such as switching from a PRG state to an ERS state and / or a lower bias or switching voltage than when the depolarizing dielectric layer is not used. Suitably, the patterned metal layer 212 may include word and / or bit lines for reading and writing the Fe / AFe FET device 100 of the 3D embedded storage array. As a non-limiting illustration, the word line may be connected to the gate 106 of the Fe / AFe FET 100, and the bit line may be connected to the source or drain of the Fe / AFe FET 100.

[0049] Fig. 8A and 8B Memory array 300 is shown according to some other suitable embodiments. Fig. 8A A portion of the memory array 300 is shown in a three-dimensional stereogram. Figure 8B FIG. 3 shows a circuit diagram of a memory array 300. As shown, the memory array 300 includes a plurality of memory cells 302, which may be arranged in a grid of columns and rows. Each memory cell 302 includes a Fe / AFe FET and Figure 1A The layer structure of the planar Fe / AFe FET, but for Fig. 8A and 8B The Fe / AFe FET of the embodiment is implemented in a complex three-dimensional (3D) array, wherein the word line 72 is electrically connected to or forms the gate electrode of the Fe / AFe FET, the bit line 306 is electrically connected to or forms the drain region of the Fe / AFe FET, and the source line 308 is electrically connected to or forms the source region of the Fe / AFe FET. To provide addressability of individual memory cells 302, the word lines (or more generally, conductive lines) 72 are separated from each other by intervening insulator material 52, and the bit lines 306 and source lines 308 are separated from each other by insulator material 98. The Fe / AFe FET cell is fabricated as a multi-layer structure 90 that is in electrical contact with the bit lines 306, source lines 308, and word lines 72. Fig. 8ADetail B of FIG. 3 provides an enlarged view of a portion of the memory array 300, with the enlarged view illustrating the multilayer structure, each multilayer structure 90 includes a memory film or layer 104 including a ferroelectric material having Fe and AFe domains, a depolarizing dielectric layer 108 disposed on the memory film or layer 104 (e.g., in contact), and an oxide semiconductor layer 102 forming a channel of the memory cell 302. As previously described, the memory film or layer 104 may include, for example, HZO or another type of ferroelectric material, such as SrBi2Ta2O9, PbZr x Ti 1-x O3 or BaTiO3. The depolarization dielectric layer 108 may include, for example, Al2O3, HfO2, ZrO2, or a combination thereof. The oxide semiconductor layer 102 may include, for example, ZnO, InWO, InGaZnO, InZnO, ITO, or a combination thereof. Fig. 8A An exemplary multilayer structure 90 of the Fe / AFe unit of the embodiment has Figure 1A The layer sequence of the planar Fe / AFe FET 100 of the embodiment is corresponding to that of the gate electrode (corresponding to Fig. 8A Starting from the word line 72 in the gate, a ferroelectric memory film or layer 104 is disposed on the gate / word line 72; a depolarization dielectric layer 108 is disposed on the ferroelectric memory film or layer 104, and an oxide semiconductor layer 102 is disposed on the depolarization dielectric layer 108. However, it should be understood that the exemplary stack 90 can be composed of Figure 2 (wherein a depolarizing dielectric layer 108 is interposed between the gate / word line 72 and the ferroelectric memory film or layer 104) or Figure 4 The ferroelectric memory film or layer 104 is replaced by one of the alternative stack designs (in which two depolarizing dielectric layers 108 are disposed on each side of the ferroelectric memory film or layer 104). As in the previously described embodiments, the inclusion of a depolarizing dielectric layer or layers provides advantages, such as improved switching from a PRG state to an ERS state and / or reduced bias or switching voltage compared to when no depolarizing dielectric layer is employed. The memory cells 302 are arranged in a two-dimensional (2D) array, which in turn is vertically stacked to provide a 3D memory array, thereby increasing device density. The memory array 300 can be formed during BEOL processing of a semiconductor die. For example, the memory array 300 can be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0050] In some suitable embodiments, the memory array 300 is a flash memory array, such as a NOR flash memory array, etc. Fig. 8AAs best seen in detail B of , each memory cell 302 includes a transistor 304 (e.g., Fe / AFe-FET 100) having a memory structure or stack 90 (e.g., including a memory film or layer 104 accompanied by a depolarizing dielectric layer 108 and an oxide semiconductor layer 102). The memory film or layer 104 serves as a gate dielectric that separates a gate electrode (corresponding to a word line 72) from a transistor channel corresponding to the oxide semiconductor layer 102. In each Fe / AFE FET transistor 304, the gate is implemented as a corresponding word line (e.g., conductive line) 72, the source region is implemented as a corresponding bit line (e.g., conductive line) 306, and the drain region is implemented as a source line (e.g., conductive line) 308, which in some embodiments electrically couples the drain region to ground. As shown, the memory cells 302 in the same horizontal column of the memory array 300 may share a common word line 72, and the memory cells 302 in the same vertical column of the memory array 300 may share a common source line 308 and a common bit line 306.

[0051] As shown, the memory array 300 includes a plurality of vertically stacked conductive lines 72 (e.g., Figure 8B The conductive lines 72 are shown in the circuit diagram of FIG. 7 as word lines WL0, WL1, and WL2) and a dielectric layer 52 disposed between adjacent conductive lines 72. In some suitable embodiments, the conductive lines 72 extend in a direction parallel to the main surface of the underlying substrate ( Fig. 8A and 8B In order to allow electrical contact with word line 72, as shown in FIG. Fig. 8A As shown in the main figure, portions of the array may be processed, such as by etching, to expose the ends of the continuous wires 72 in the stepped structure 312 so that the lower wires 72 are longer than the endpoints of the upper wires 72 and extend laterally beyond the endpoints of the upper wires 72. Fig. 8A Also schematically shown are landing sites 314 and contact vias ( Fig. 8A ), to contact the corresponding ends of the word lines 72 along the stepped structure 312. For example, in Fig. 8A , a plurality of stacks or conductors 72 are shown, wherein the topmost conductor 72 is the shortest and the bottommost conductor 72 is the longest. The respective lengths of the conductors 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductor 72 may be accessible from above the memory array 300, and a conductive contact may be made to contact the exposed portion of each conductor 72.

[0052] According to some suitable embodiments, the memory array 300 further includes a plurality of conductive lines 306 (e.g., Figure 8B , as shown in the circuit diagram of the bit lines BL0, BL1, BL2, BL3, BL4 and BL5) and a plurality of conductive lines 308 (eg, in Figure 8B308 as source lines SL0, SL1, SL2, SL3, SL4, and SL5 in the circuit diagram of FIG. 30). Appropriately, the wire 306 and the wire 308 may each extend in a direction perpendicular to the wire 72. In some suitable embodiments, the insulator material 98 is disposed between the wires 306 and the wires 308 and isolates adjacent wires 306 and wires 308. In practice, pairs of wires 306 and wires 308 and intersecting wires 72 may define the boundaries of each memory cell 302, and the dielectric material 303 may be disposed between adjacent pairs of wires 306 and wires 308 and isolate them. In some suitable embodiments, the wire 308 may be electrically coupled to ground. Although Fig. 8A A particular placement of wire 306 relative to wire 308 is shown, but it should be understood that the placement of wire 306 and wire 308 may be reversed.

[0053] The multilayer stack 90 of the memory array 300 includes an oxide semiconductor (OS) layer 102. The oxide semiconductor layer 102 provides a channel region for the transistor 304 of the memory cell 302. For example, when an appropriate voltage (i.e., higher than the corresponding threshold voltage (Vth) of the corresponding transistor 304) is applied through the corresponding conductive line 72, the region of the oxide semiconductor layer 102 intersecting the conductive line 72 can allow current to flow from the conductive line 306 to the conductive line 308 (e.g., in the direction indicated by the arrow 406, i.e., the channel direction). Along the channel direction (arrow 406), adjacent transistors 304 are electrically isolated from each other by the isolation material 408.

[0054] like Fig. 8A As shown in detail B of FIG. 1 , in the illustrated embodiment, a ferroelectric memory layer or film 104 and a depolarization dielectric layer 108 are disposed between the conductive line 72 and the oxide semiconductor (OS) layer 102, and the memory layer or film 104 (and the accompanying depolarization dielectric layer 108) provide a gate dielectric for the transistor 304. Because the memory structure or stack 90 includes the memory film or layer 104 as described herein, the memory array 300 may be referred to as a Fe / AFe random access memory (Fe / AFe-RAM) array.

[0055] In some suitable embodiments, the memory film or layer 104 may be polarized in one of two different directions. In practice, the polarization direction may be changed by applying an appropriate voltage difference across the memory structure or stack 90 and generating an appropriate electric field. Suitably, the polarization may be relatively localized (e.g., typically included within each boundary of the memory cell 302) and a continuous region of the memory structure or stack 90 may extend across a plurality of memory cells 302. Depending on the polarization direction of a particular region of the memory film or layer 104, the threshold voltage of the corresponding transistor 304 varies and may store a value (e.g., 0 or 1). For example, when a region of the memory film or layer 104 has a first electrical polarization direction, the corresponding transistor 304 may have a relatively low threshold voltage, and when a region of the memory film or layer 104 has a second electrical polarization direction, the corresponding transistor 304 may have a relatively high threshold voltage. Suitably, the difference between the two threshold voltages may be referred to as a threshold voltage shift. Advantageously, a larger threshold voltage shift makes it easier (e.g., less error-prone) to read the value stored in the corresponding memory cell 302.

[0056] According to some suitable embodiments, in order to perform a write operation on the memory cell 302, a write voltage is applied to a portion of the memory structure or stack 90 corresponding to the memory cell 302. As appropriate, the write voltage may be applied, for example, by applying an appropriate voltage to the corresponding conductive line 72 (e.g., a corresponding word line) and the corresponding conductive line 306 and conductive line 308 (e.g., a corresponding bit and source line). By applying the write voltage across a portion of the memory film or layer 104, the polarization direction of a region of the memory film or layer 104 may be changed. As a result, the corresponding threshold voltage of the corresponding transistor 304 may be switched from a low threshold voltage to a high threshold voltage, or vice versa, and the value may be stored in the memory cell 302. Since the conductive line 72 intersects the conductive line 306 and the conductive line 308, individual memory cells 302 may be selected for a write operation.

[0057] According to some suitable embodiments, to perform a read operation on a memory cell 302, a read voltage (e.g., a voltage between a lower threshold voltage and an upper threshold voltage) is applied to a corresponding conductive line 72 (e.g., a corresponding word line). Depending on the polarization direction of the corresponding region of the memory film or layer 104, the transistor 304 of the memory cell 302 may or may not be turned on. Thus, the corresponding conductive line 306 may or may not be discharged through the corresponding conductive line 308 (e.g., a corresponding grounded source line), and the value stored in the memory cell 302 may be determined. Since the conductive line 72 intersects the conductive line 306 and the conductive line 308, the read operation may select an individual memory cell 302.

[0058] According to some suitable embodiments, Figures 9A-9KMethods and / or processes for manufacturing and / or fabricating a memory array, such as memory array 300, are illustrated by a series of schematic perspective views of a memory array in fabrication.

[0059] Suitably, the process may be as follows Fig. 9A The channel stack shown starts with alternating layers of isolation material 54L and metal or dielectric material 72L (isolation material 54L such as a suitable oxide, silicon nitride (SiN) or other suitable isolation material, which will eventually serve as dielectric layer 52), (metal or dielectric material 72L such as a suitable oxide or SiN or other suitable dielectric material, which is different from the above isolation material and will eventually serve as conductive line 72). Suitably, the aforementioned alternating layers may include and / or be referred to as an epitaxial (EPI) stack.

[0060] Next, Fig. 9B As shown, according to some suitable embodiments, trenches 120 are etched in the EPI stack of the aforementioned alternating layers (54L, 72L) to form word lines 72 and spacer dielectric material 54. Fig. 9C As shown, for example, a memory structure (104, 108) including a memory film or layer 104 and a depolarization dielectric layer 108 is deposited and / or otherwise formed in the trench 120 described above. In practice, the steps may include, for example, sequential deposition and / or formation of both the memory film or layer 104 and the depolarization dielectric layer 108. Depending on the order of deposition of the memory film or layer 104 and the depolarization dielectric layer 108, the memory structure (104, 108) may have Figure 1A (by depositing a storage film or layer 104 followed by a depolarizing dielectric layer 108) or may have Figure 3 configuration (by depositing a depolarizing dielectric layer 108 followed by deposition of a storage film or layer 104) or may have Figure 4 configuration (by depositing a first depolarizing dielectric layer 108, followed by depositing a storage film or layer 104, and then depositing a second depolarizing dielectric layer 108).

[0061] Next, if Fig.9D As shown, an oxide semiconductor layer 102 is deposited and / or formed in trench 120, such as adjacent to, covering, contacting and / or otherwise close to the memory structure (104, 108). Fig.9E As shown, the remaining portion of the trench is filled with an insulator material 98, such as but not limited to oxide or SiN. Fig.9F As shown, the filler insulator material 98 and the oxide semiconductor layer 102 are etched to form an opening 122. Figure 9GAs shown, the opening 122 is filled with a suitable isolation material 408, such as oxide or SiN, which will eventually be used to isolate adjacent transistors 304 along the channel direction (arrow 406), as shown in FIG. Fig. 8A discussed.

[0062] refer to Figure 9H , an appropriate mask 124 and / or a self-aligned process may be used to etch the opening 126 to accommodate the bit line 306 and the source line 308 . Fig.9I Subsequently, a bit line 306 and a source line 308 are formed by filling the opening 126. That is, the opening 126 is filled to form the bit line 306 and the source line 308. In some embodiments, the bit line and / or source line structure (306, 308) is formed of a suitable metal or other suitable electrically conductive material, such as but not limited to tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), combinations thereof and / or alloys thereof, etc. Figure 9J The step structure 312 is formed, for example, by appropriate etching and / or other material removal processes. Figure 9K , forming a contact through hole 128 to contact the landing point 314 of the step structure 312 (see Fig. 8A ), thereby providing electrical connection to the word line 72, and further metallization layers 130 are formed during BEOL processing to electrically connect to the corresponding word line 72, source line 308 and bit line 306.

[0063] In addition to the above reference Figures 9A-9K In addition to the fabrication steps outlined, the process for forming the memory array 300 may include a thermal annealing step to produce a ferroelectric crystallization of the memory film or layer 104, such as converting a suitable portion of the HZO into a ferroelectric orthorhombic phase as an example, as previously described with reference to Figures 1B-1F Annealing can usually be performed at Fig. 9C It is performed at some stage in the process after the stage shown, that is, after the memory structures (104, 108) are formed.

[0064] Some further illustrative embodiments are described next.

[0065] In some embodiments, a field effect transistor (FET) device is selectively switchable between a first state and a second state, comprising: a source and a drain region; a channel region disposed between the source and the drain regions; a gate disposed to selectively receive a bias voltage to selectively switch the FET between the first state and the second state; a storage structure disposed between the gate and the channel region, the storage structure comprising an antiferroelectric first portion and a ferroelectric second portion, the first and second portions being polarized in a first direction when the FET is in the first state; and at least one depolarizing dielectric layer disposed proximate the storage structure. In some embodiments, when the FET is set to the first state, the at least one depolarizing dielectric layer is used to destabilize the polarization of at least the second portion of the storage structure while maintaining the polarization of the first portion of the storage structure.

[0066] In some further embodiments, at least one depolarizing dielectric layer is used to destabilize the polarization of at least a second portion of the memory structure by generating an electric field in a direction opposite to the first direction.

[0067] In further embodiments, at least a first portion of the memory structure is generally non-polarized when the FET is set to the second state.

[0068] In some embodiments, when the FET is set to the second state, the at least one depolarizing dielectric layer is not operated to polarize the first portion of the memory structure.

[0069] In yet another embodiment, the memory structure includes a hafnium zirconium oxide (HZO) film having a zirconium (Zr) percentage in a range between 50% and 80%, inclusive.

[0070] In some further embodiments, the first portion includes a tetragonal phase (T phase) crystalline portion of the HZO film and the second portion includes an orthorhombic phase (O phase) crystalline portion of the HZO film.

[0071] In some embodiments, the T-phase crystal portion is in the range of 2% to 14% inclusive of the HZO film, and the O-phase crystal portion is in the range of 84% to 88% inclusive of the HZO film.

[0072] In yet another embodiment, the memory structure includes at least a portion of an antiferroelectric film having a thickness in a range between 2 nanometers and 20 nanometers, inclusive.

[0073] In some embodiments, at least one depolarization dielectric layer includes at least one of aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), and zirconium oxide (ZrO 2 ).

[0074] In some further embodiments, at least one depolarization dielectric layer has a thickness in a range between 0.1 nanometers and 2 nanometers, inclusive.

[0075] In yet another embodiment, an oxide semiconductor (OS) layer serves as a channel region.

[0076] In yet another embodiment, at least one depolarizing dielectric layer is disposed between the channel region and the memory structure.

[0077] In some further embodiments, at least one depolarization dielectric layer is disposed between the storage structure and the gate.

[0078] In some additional embodiments, the at least one depolarization dielectric layer includes two depolarization dielectric layers, each depolarization dielectric layer being disposed on opposite sides of the storage structure.

[0079] In some embodiments, a three-dimensional (3D) memory array includes a plurality of electrically conductive word lines, a plurality of electrically conductive bit lines and electrically conductive source lines, and a memory cell array. The electrically conductive bit lines and the electrically conductive source lines are perpendicular to the electrically conductive word lines. Each memory cell includes: a channel region electrically connected between one of the electrically conductive source lines and one of the electrically conductive bit lines, a memory film disposed between one of the electrically conductive word lines and the channel region, the memory film including a first antiferroelectric domain and a second ferroelectric domain, when the memory cell is switched to a first state, the first antiferroelectric domain and the second ferroelectric domain are polarized along a first direction, and a depolarizing dielectric layer disposed on at least one side of the memory film. When the memory cell is set to the first state, the depolarizing dielectric layer generates an electric field, the electric field weakens the polarization of the ferroelectric domain of the memory film, while maintaining the polarization of the antiferroelectric domain of the memory film.

[0080] In some embodiments, the magnitude of the electric field is related to the voltage drop (V) across the depolarizing dielectric layer resulting from the applied bias voltage divided by the thickness of the depolarizing dielectric layer. DE ), and the thickness of the depolarizing dielectric layer is determined so that V DE It falls between a first control voltage associated with the first antiferroelectric domain of the storage film and a second control voltage associated with the second ferroelectric domain, and the first control voltage is greater than the second control voltage.

[0081] In some further embodiments, V DE The second control voltage is closer than the first control voltage.

[0082] In another embodiment, the thickness of the depolarization dielectric layer is in a range between 0.1 nanometers and 2 nanometers, inclusive.

[0083] In yet a further embodiment, a method of manufacturing a field effect transistor (FET) includes: forming a source region; forming a drain region; forming a channel region between the source region and the drain region; forming a gate, the gate being arranged to selectively receive a bias voltage, the bias voltage selectively switching the FET between a first programming state and a second erased state; forming an antiferroelectric / ferroelectric layer between the gate and the channel region, the antiferroelectric / ferroelectric layer including an antiferroelectric portion and a ferroelectric portion, both portions being polarized in a first direction when the FET is switched to a programming state; and forming a depolarizing dielectric layer arranged on at least one side of the antiferroelectric / ferroelectric layer. Suitably, when the FET is set to a programming state by selectively applying a bias voltage of a first magnitude to the gate, the depolarizing dielectric layer is used to destroy the polarization of the ferroelectric portion without destroying the polarization of the antiferroelectric portion.

[0084] In yet another embodiment, the antiferroelectric portion is generally non-polarized when the FET is set to an erased state by selectively applying a bias voltage of a second magnitude to the gate.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A field effect transistor device, characterized in that: The field effect transistor device is selectively switchable between a first state and a second state, the field effect transistor device comprising: a source region and a drain region; A channel region, disposed between the source region and the drain region; a gate arranged to selectively receive a bias voltage to selectively switch the field effect transistor device between the first state and the second state; a memory structure disposed between the gate and the channel region, the memory structure comprising an antiferroelectric first portion and a ferroelectric second portion, the first portion and the second portion being polarized along a first direction when the field effect transistor device is in the first state; and At least one depolarization dielectric layer is disposed adjacent to the storage structure.

2. The field effect transistor device according to claim 1, characterized in that Wherein when the field effect transistor device is set to the first state, the at least one depolarization dielectric layer operates to destabilize the polarization of at least the second portion of the memory structure while maintaining the polarization of the first portion of the memory structure.

3. The field effect transistor device according to claim 2, characterized in that wherein the at least one depolarizing dielectric layer operates to destabilize the polarization of at least the second portion of the memory structure by generating an electric field in a direction opposite to the first direction.

4. The field effect transistor device according to claim 2, characterized in that: Wherein when the field effect transistor device is set to the second state, at least the first portion of the memory structure is generally unpolarized.

5. The field effect transistor device according to claim 1, characterized in that The channel region includes an oxide semiconductor layer.

6. The field effect transistor device according to claim 1, characterized in that The at least one depolarization dielectric layer is disposed between the channel region and the storage structure or between the storage structure and the gate.

7. The field effect transistor device according to claim 1, characterized in that The at least one depolarization dielectric layer includes two depolarization dielectric layers, and each of the two depolarization dielectric layers is disposed on one side of the storage structure.

8. A three-dimensional storage array, characterized in that: include: a metallization layer including patterned metal layers separated by intermetallic dielectric materials and interlayer vias passing through the intermetallic dielectric materials and interconnecting the patterned metal layers; as well as Field effect transistor stacks are separated by the intermetallic dielectric material, each of the field effect transistor stacks includes a two-dimensional array of field effect transistor devices as claimed in claim 1, the field effect transistor devices are electrically connected to the metallization layer.

9. A three-dimensional storage array, characterized in that: include: A three-dimensional array of field effect transistor devices as claimed in claim 1; wherein the gate of the field effect transistor comprises an electrically conductive word line, the source region comprises an electrically conductive source line, and the drain region comprises an electrically conductive bit line; The electrically conductive source line and the electrically conductive bit line are perpendicular to the electrically conductive word line.

10. A three-dimensional storage array, characterized in that: include: a plurality of electrically conductive word lines; a plurality of electrically conductive bit lines and electrically conductive source lines, perpendicular to the electrically conductive word lines; as well as An array of memory cells, each of the memory cells comprising: an oxide semiconductor channel region electrically connected between one of the electrically conductive source lines and one of the electrically conductive bit lines; a memory film disposed between one of the electrically conductive word lines and the oxide semiconductor channel region, the memory film comprising a first antiferroelectric domain and a second ferroelectric domain, wherein the first antiferroelectric domain and the second ferroelectric domain are polarized along a first direction when the memory cell is switched to a first state; and a depolarizing dielectric layer disposed on at least one side of the storage film; When the memory cell is set to the first state, the depolarization dielectric layer generates an electric field, which weakens the polarization of the second ferroelectric domain of the memory film while maintaining the polarization of the first antiferroelectric domain of the memory film.

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