Driving circuit board for jet printing head of poultry egg ink-jet printer

Abstract

The utility model discloses a printing head driving circuit board of a poultry egg ink-jet printer, which comprises an FPGA (field programmable gate array) master control circuit, a communication circuit, a printing head driving circuit, a sampling circuit and a power supply circuit connected with the above circuits, the FPGA master control circuit is connected with the communication circuit, the printing head driving circuit and the sampling circuit, the power supply circuit is connected with an input power supply, and the sampling circuit is connected with the FPGA master control circuit. And the FPGA main control circuit comprises a plurality of FPGA chips. According to the utility model, the FPGA is used as a main control core, multi-thread operation can be carried out, the differential chip is used for communication, the reliability is strong, the working efficiency is high, and the use effect is good.

Description

Technical Field

[0001] The utility model belongs to the technical field of inkjet printer equipment, in particular to a printing head driving circuit board of a poultry and egg inkjet printer. Background Art

[0002] Eggs are rich in nutrition and cheap, and are a popular daily food. With the improvement of food safety laws and regulations, corresponding coding requirements and standards have been introduced for poultry and egg foods to improve food traceability, which has created a need for coding on the surface of eggs. To achieve egg coding, it is necessary to use a printer and place the eggs under the nozzle for coding. The existing printer printing driver board has a high manufacturing cost, complex operation, and low work efficiency. Summary of the invention

[0003] In order to solve the above problems, the purpose of the utility model is to provide a small-sized and low-cost driving circuit board for the printing head of a poultry and egg inkjet printer.

[0004] In order to achieve the above-mentioned invention object, the utility model adopts the following technical solutions:

[0005] A printing head driving circuit board for a poultry and egg inkjet printer comprises an FPGA main control circuit, a communication circuit, a printing head driving circuit, a sampling circuit, and a power supply circuit connected to the above circuits. The FPGA main control circuit is connected to the communication circuit, the printing head driving circuit, and the sampling circuit, and the power supply circuit is connected to an input power supply. The FPGA main control circuit comprises a plurality of FPGA chips; the printing head driving circuit comprises a plurality of driving chips U4, a plurality of level converters U5, and a contact strip P1 connected to the printing head, the contact strip P1 comprises a plurality of contacts, two input ends of the driving chip U4 are connected to the FPGA main control circuit, an output end is connected to two contacts on the contact strip, a power supply end is connected to a printing head driving power supply, and a ground end is grounded; an input end of the level converter U5 is connected to the FPGA main control circuit, an input end is connected to the contact strip, a power input end and a mode selection end are connected to the input power supply and are grounded via a capacitor C9, and a power output end is connected to the printing head driving power supply and is grounded via a capacitor C10.

[0006] Furthermore, the contact GND1 of the above-mentioned contact strip P1 is connected via the drain of the N-channel field effect transistor M1 and grounded via the capacitor C12, the source of the N-channel field effect transistor M1 is grounded, and a resistor R9 is connected between the source and the gate, and a resistor R10 is connected between the source and the drain, the gate is connected to the collector of the transistor Q1, and connected to the print head drive power supply via the resistor R8, the emitter of the transistor Q1 is grounded, the base is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the output end of the power supply circuit via the resistor R6, and is connected to the FPGA main control circuit.

[0007] Furthermore, the contact GND1 of the contact strip P1 is connected to the FPGA main control circuit via an amplifier circuit, and the amplifier circuit includes a dual operational amplifier U6, a first non-inverting input terminal of the dual operational amplifier U6 is connected to the contact GND1 of the contact strip P1 via a resistor R15, a first inverting input terminal is connected to the first output terminal via a resistor R13, and is grounded via a resistor R14; the first inverting input terminal is connected to the second non-inverting input terminal, the second inverting input terminal is connected to the positive power supply terminal via a resistor R11, and is grounded via a resistor R12, the positive power supply terminal is grounded via a capacitor C13, the negative power supply terminal is grounded, and the second output terminal is connected to the FPGA main control circuit.

[0008] Furthermore, the above-mentioned print head driving circuit also includes multiple bidirectional bus converters U7, the B port of each bidirectional bus converter U7 is connected to the FPGA main control circuit, the power supply end of the B port is connected to the output end of the power supply circuit, and is grounded through capacitor C15; the A port is connected to the input end of the logic chip U8 and the logic chip U9, the power supply end of the A port is connected to the input power supply, and is grounded through capacitor C14, and the output enable end, control end, and ground end are all grounded; the output end of the logic chip U8 and the logic chip U9 is connected to the contact strip P1.

[0009] Furthermore, the above-mentioned communication circuit includes a dual-channel differential line driver U1, a dual-way inverter U2, and a communication interface J1. The first differential input signal terminal, the second differential input signal terminal, and the second differential output signal terminal of the dual-channel differential line driver U1 are connected to the communication interface J1, a resistor R1 is connected between the first differential input signal terminal, and a resistor R2 is connected between the second differential input terminal. The LVTTL signal input terminal and the LVTTL signal output terminal are connected to the FPGA main control circuit, the power supply terminal is connected to the output terminal of the power supply circuit, the ground terminal is grounded, and the capacitors C1 and C2 are connected in parallel between the two; the input terminal of the dual-way inverter U2 is connected to the communication interface J1, and the input terminal and the input terminal are connected to the output terminal of the power supply circuit via resistors R3 and R4 respectively, the output terminal is connected to the FPGA main control circuit, the power supply terminal is connected to the output terminal of the power supply circuit, and the ground terminal is grounded; the print head drive power supply is connected to the communication interface J1 via a self-resetting fuse F1, and the input power supply is connected to the communication interface J1.

[0010] Furthermore, the above-mentioned power supply circuit includes a voltage stabilizer U3, the input power supply is connected to the input end of the voltage stabilizer U3, the output end is connected to the FPGA main control circuit, the communication circuit, the print head drive circuit, and the sampling circuit, the ground end is grounded, and capacitors C3 and C4 are connected in parallel between the input end and the ground end. The input end is grounded through a series resistor R5 and a light-emitting diode LED1, and capacitors C5 to C9 are connected in parallel between the output end and the ground end.

[0011] Furthermore, the above-mentioned sampling circuit includes a single-chip microcomputer U10, a thermistor NTC1, and a storage chip U11 built into the ink cartridge. One end of the thermistor NTC1 is connected to the single-chip microcomputer U10, and is connected to the output end of the power supply circuit through a resistor R18, and the other end is grounded. The capacitor C18 is connected in parallel with the thermistor NTC1; the clock signal end and the serial data end of the storage chip U11 are connected to the single-chip microcomputer U10, and are connected to the output end of the power supply circuit through resistors R19 and R20 respectively, the power end is connected to the output end of the power supply circuit, and the ground end is grounded; the single-chip microcomputer is connected to the FPGA main control circuit.

[0012] Due to the adoption of the above-mentioned technical solution, the utility model has the following advantages:

[0013] The egg inkjet printer print head driving circuit board has a simple circuit, low manufacturing cost, low power consumption, high precision, and small size. It adopts FPGA as the main control core, can perform multi-threaded operations, and adopts differential chips for communication. It has strong reliability, high work efficiency, good use effect, is suitable for long-term work, and has good promotion and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a structural block diagram of a driving circuit board of a printing head of a poultry and egg inkjet printer of the utility model;

[0015] Figure 2 yes Figure 1 The communication circuit schematic diagram in ;

[0016] Figure 3 yes Figure 1 The power supply circuit and communication circuit schematic diagram;

[0017] Figure 4 yes Figure 1 The schematic diagram of the print head driving circuit in FIG.

[0018] Figure 5 yes Figure 1 Schematic diagram of sampling circuit in ;

[0019] Figure 6 yes Figure 1 Schematic diagram of an embodiment of the FPGA master control circuit in FIG. DETAILED DESCRIPTION

[0020] The technical solution of the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0021] like Figures 1 to 6As shown, a printing head driving circuit board of a poultry and egg inkjet printer comprises an FPGA main control circuit, a communication circuit, a printing head driving circuit, a sampling circuit, and a power supply circuit connected to the above circuits, the FPGA main control circuit is connected to the communication circuit, the printing head driving circuit, and the sampling circuit, the power supply circuit is connected to a 5V input power supply, the FPGA main control circuit comprises a plurality of FPGA chips; the printing head driving circuit comprises a plurality of driving chips U4, a plurality of level converters U5, and a contact strip P1 connected to the printing head, the contact strip comprises a plurality of contacts, two input ends (pins INA, INB) of the driving chip U4 are connected to the FPGA main control circuit, the output end (pins OUTA, OUTB) is connected to two contacts on the contact strip P1, the power supply end (pin VDD) is connected to a 12V printing head driving power supply, and the ground end (pin GND) is grounded; the input end (pins AIN, BIN, CIN, DIN, EIN, FIN) of the level converter U5 is connected to the FPGA main control circuit The input terminal (pins AOUT, BOUT, COUT, DOUT, EOUT, FOUT) is connected to the contact strip P1, the power input terminal (pin VCC) and the mode selection terminal (pin SELECT) are connected to the input power supply 5V and grounded through the capacitor C9, the power output terminal (pin VDD) is connected to the print head drive power supply 12V and grounded through the capacitor C10; the contact GND1 of the contact strip P1 is connected to the FPGA main control circuit through the amplifier circuit; the contact strip P1 Point GND1 is connected via the drain of the N-channel field effect transistor M1 and grounded via capacitor C12, the source of the N-channel field effect transistor M1 is grounded, and a resistor R9 is connected between the source and the gate, and a resistor R10 is connected between the source and the drain, the gate is connected to the collector of the transistor Q1, and connected to a 12V print head drive power supply via resistor R8, the emitter of the transistor Q1 is grounded, the base is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the output end of the power supply circuit via resistor R6, and is connected to the FPGA main control circuit.

[0022] The amplification circuit includes a dual operational amplifier U6, a first non-inverting input terminal of the dual operational amplifier U6 is connected to the contact GND1 of the contact strip P1 via a resistor R15, a first inverting input terminal is connected to the first output terminal via a resistor R13, and is grounded via a resistor R14; the first inverting input terminal is connected to the second non-inverting input terminal, the second inverting input terminal is connected to the positive power supply terminal via a resistor R11, and is grounded via a resistor R12, the positive power supply terminal is grounded via a capacitor C13, the negative power supply terminal is grounded, and the second output terminal is connected to the FPGA main control circuit.

[0023] Preferably, the model of the FPGA chip is EF2L45BG256B, the multiple driver chips use dual-channel driver chip EG4427 and gate driver IX4427MTR; the model of the level converter is CD4504BM; the model of the N-channel field effect transistor M1 is FDS6682; the model of the transistor Q1 is S8050; and the model of the dual operational amplifier U6 is MC33502.

[0024] The above-mentioned print head driving circuit also includes multiple bidirectional bus converters U7, the B port (pins B1~B8) of each bidirectional bus converter U7 is connected to the FPGA main control circuit, the power supply end (pin VCCB) of the B port is connected to the output end of the power supply circuit, and is grounded through capacitor C15; the A port (pins A1~A8) is connected to the input end of the logic chip U8 and the logic chip U9, the power supply end (pin VCCA) of the A port is connected to the input power supply 5V, and is grounded through capacitor C14, and the output enable end (OE), control end (DIR), and ground end (GND) are all grounded; the output end of the logic chip U8 and the logic chip U9 is connected to the contact strip P1.

[0025] Preferably, the model of the bidirectional bus converter U7 is SN74LVC4245APW; the model of the logic chip U8 and the logic chip U9 are both F5474.

[0026] The communication circuit includes a dual-channel differential line driver U1, a dual-way inverter U2, and a communication interface J1. The first differential input signal terminal (pins Rin1+, Rin1-), the second differential input signal terminal (Rin2+, Rin2-), and the second differential output signal terminal (pins Dout2+, Dout2-) of the dual-channel differential line driver U1 are connected to the communication interface J1. A resistor R1 is connected between the first differential input pair (pins Rin1+, Rin1-), a resistor R2 is connected between the second differential input pair (Rin2+, Rin2-), and the LVTTL signal input terminal (pins Din1, Din2) and the LVTTL signal output terminal (pins Rout1, Rout2) are connected to the FPGA. The main control circuit is connected, the power supply end (pin VCC) is connected to the output end of the power supply circuit, the ground end (pin GND) is grounded, and the capacitors C1 and C2 are connected in parallel between the two; the input end (pins 1A, 2A) of the dual inverter U2 is connected to the communication interface J1, and the input end (pin 1A) and the input end (pin 2A) are connected to the output end of the power supply circuit via resistors R3 and R4 respectively, the output end (pins 1Y, 2Y) is connected to the FPGA main control circuit, the power supply end (pin VCC) is connected to the output end of the power supply circuit, and the ground end (pin GND) is grounded; the print head drive power supply 12V is connected to the communication interface J1 via the self-recovery fuse F1, and the input power supply 5V is connected to the communication interface J1; the communication interface J1 adopts an FFC connector.

[0027] Preferably, the model of the dual-channel differential line driver is SN65LVDS049PW; the model of the dual-path inverter is SN74LVC2G04DBVR.

[0028] The power supply circuit includes a voltage stabilizer U3, an input power supply 5V is connected to the input end (pin Vi) of the voltage stabilizer U3, an output end (pin Vo) is connected to the FPGA main control circuit, the communication circuit, the print head drive circuit, and the sampling circuit, and is used to provide a 3.3V voltage, a ground end (pin A) is grounded, capacitors C3 and C4 are connected in parallel between the input end (pin Vi) and the ground end (pin A), the input end (pin Vi) is grounded via a series resistor R5 and a light-emitting diode LED1, and capacitors C5 to C9 are connected in parallel between the output end (pin Vo) and the ground end (pin A).

[0029] The sampling circuit includes a single-chip computer U10, a thermistor NTC1, and a memory chip U11 built into the ink cartridge. One end of the thermistor NTC1 is connected to the single-chip computer U10, and is connected to the output end of the power supply circuit via a resistor R18, and the other end is grounded. The capacitor C18 is connected in parallel with the thermistor NTC1; the clock signal end (pin SC) and the serial data end (pin SD) of the memory chip U11 are connected to the single-chip computer U10, and are connected to the output end of the power supply circuit via resistors R19 and R20 respectively, the power supply end (pin V) is connected to the output end of the power supply circuit, and the ground end (pin G) is grounded; the single-chip computer is connected to the FPGA main control circuit; the thermistor transmits the ambient temperature information to the single-chip computer, the memory chip is used to store the serial number, production date, remaining ink volume and other information of the ink cartridge, and the single-chip computer reads the contents of the memory chip through the corresponding communication protocol.

[0030] Preferably, the model of the single chip microcomputer is STM8S003F3P6; the model of the memory chip U11 is AT24C16.

[0031] The FPGA main control circuit includes multiple FPGA chips, for example, a first FPGA chip U12 connected to the communication circuit, a second FPGA chip U13 connected to the print head driving circuit and the sampling circuit, and a third FPGA chip U14.

[0032] Preferably, the model of the FPGA chip is EF2L45BG256B.

[0033] The utility model discloses a printing head driving circuit board of a poultry and egg inkjet printer. The FPGA main control circuit can realize multi-threading and multi-tasking real-time operation, and can accurately count each printed ink drop. The pin configuration is highly flexible, and the communication programming with the host is convenient. The communication circuit has strong anti-interference ability, can effectively suppress electromagnetic interference, and has accurate timing positioning. The utility model inkjet printer adopts a thermal foaming nozzle, including 208 nozzles. The printing head driving circuit can control each nozzle hole for precise inkjet, and can also detect the quality of each nozzle hole of the printing head.

[0034] The utility model discloses a printing head driving circuit board of a poultry and egg inkjet printer, which adopts a gold-plated contact to connect the printing head through a probe of a probe seat, so as to drive the printing head to spray ink.

[0035] The above description is only a preferred embodiment of the present invention, and not a limitation of the present invention. Without departing from the spirit and scope of the present invention, all equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of patent protection of the present invention.

Claims

1. A printing head driving circuit board for a poultry and egg inkjet printer, characterized in that: It includes an FPGA main control circuit, a communication circuit, a print head driving circuit, a sampling circuit, and a power supply circuit connected to the above circuits. The FPGA main control circuit is connected to the communication circuit, the print head driving circuit, and the sampling circuit, and the power supply circuit is connected to the input power supply. The FPGA main control circuit includes multiple FPGA chips; the print head driving circuit includes multiple driving chips U4, multiple level converters U5, and a contact strip P1 connected to the print head. The contact strip P1 includes multiple contacts. The two input ends of the driving chip U4 are connected to the FPGA main control circuit, the output end is connected to the two contacts on the contact strip, the power end is connected to the print head driving power supply, and the ground end is grounded; the input end of the level converter U5 is connected to the FPGA main control circuit, the input end is connected to the contact strip, the power input end and the mode selection end are connected to the input power supply, and are grounded through capacitor C9, and the power output end is connected to the print head driving power supply, and is grounded through capacitor C10.

2. The egg inkjet printer print head driving circuit board according to claim 1, characterized in that: The contact GND1 of the contact strip P1 is connected via the drain of the N-channel field effect transistor M1 and grounded via the capacitor C12. The source of the N-channel field effect transistor M1 is grounded, and a resistor R9 is connected between the source and the gate, and a resistor R10 is connected between the source and the drain. The gate is connected to the collector of the transistor Q1 and connected to the print head drive power supply via the resistor R8. The emitter of the transistor Q1 is grounded, and the base is connected to one end of the resistor R7. The other end of the resistor R7 is connected to the output end of the power supply circuit via the resistor R6, and is connected to the FPGA main control circuit.

3. The egg inkjet printer print head driving circuit board according to claim 1 or 2, characterized in that: The contact GND1 of the contact strip P1 is connected to the FPGA main control circuit via an amplifier circuit, and the amplifier circuit includes a dual operational amplifier U6, a first non-inverting input terminal of the dual operational amplifier U6 is connected to the contact GND1 of the contact strip P1 via a resistor R15, a first inverting input terminal is connected to the first output terminal via a resistor R13, and is grounded via a resistor R14; the first inverting input terminal is connected to the second non-inverting input terminal, the second inverting input terminal is connected to the positive power supply terminal via a resistor R11, and is grounded via a resistor R12, the positive power supply terminal is grounded via a capacitor C13, the negative power supply terminal is grounded, and the second output terminal is connected to the FPGA main control circuit.

4. The egg inkjet printer print head driving circuit board according to claim 1, characterized in that: The print head drive circuit also includes multiple bidirectional bus converters U7, the B port of each bidirectional bus converter U7 is connected to the FPGA main control circuit, the power supply end of the B port is connected to the output end of the power supply circuit and is grounded through capacitor C15; the A port is connected to the input end of the logic chip U8 and the logic chip U9, the power supply end of the A port is connected to the input power supply and is grounded through capacitor C14, and the output enable end, control end and ground end are all grounded; the output end of the logic chip U8 and the logic chip U9 is connected to the contact strip P1.

5. The egg inkjet printer print head driving circuit board according to claim 1, characterized in that: The communication circuit includes a dual-channel differential line driver U1, a dual-way inverter U2, and a communication interface J1. The first differential input signal terminal, the second differential input signal terminal, and the second differential output signal terminal of the dual-channel differential line driver U1 are connected to the communication interface J1, a resistor R1 is connected between the first differential input signal terminal, and a resistor R2 is connected between the second differential input terminal. The LVTTL signal input terminal and the LVTTL signal output terminal are connected to the FPGA main control circuit, the power supply terminal is connected to the output terminal of the power supply circuit, the ground terminal is grounded, and the capacitors C1 and C2 are connected in parallel between the two; the input terminal of the dual-way inverter U2 is connected to the communication interface J1, and the input terminal and the input terminal are connected to the output terminal of the power supply circuit via resistors R3 and R4 respectively, the output terminal is connected to the FPGA main control circuit, the power supply terminal is connected to the output terminal of the power supply circuit, and the ground terminal is grounded; the printing head driving power supply is connected to the communication interface J1 via a self-resetting fuse, and the input power supply is connected to the communication interface J1.

6. The egg inkjet printer print head driving circuit board according to claim 1, characterized in that: The power supply circuit includes a voltage stabilizer U3, an input power supply is connected to the input end of the voltage stabilizer U3, an output end is connected to the FPGA main control circuit, a communication circuit, a print head drive circuit, and a sampling circuit, a ground end is grounded, a capacitor C3 and a capacitor C4 are connected in parallel between the input end and the ground end, the input end is grounded via a series resistor R5 and a light-emitting diode LED1, and capacitors C5 to C9 are connected in parallel between the output end and the ground end.

7. The egg inkjet printer print head drive circuit board according to claim 1, characterized in that: The sampling circuit includes a single-chip microcomputer U10, a thermistor NTC1, and a memory chip U11 built into the ink cartridge. One end of the thermistor NTC1 is connected to the single-chip microcomputer U10 and is connected to the output end of the power circuit via a resistor R18, and the other end is grounded. The capacitor C18 is connected in parallel with the thermistor NTC1; the clock signal end and the serial data end of the memory chip U11 are connected to the single-chip microcomputer U10 and are connected to the output end of the power circuit via resistors R19 and R20 respectively, the power end is connected to the output end of the power circuit, and the ground end is grounded; the single-chip microcomputer is connected to the FPGA main control circuit.

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