Display card IIC level conversion circuit

Abstract

The utility model relates to a graphics card IIC level conversion circuit, which comprises a graphics card, a master control MCU, a field effect transistor Q1 and a field effect transistor Q2, the field effect transistor Q1 accesses SCL port signals of the graphics card, the field effect transistor Q1 outputs signals to an SCL port of the master control MCU, the field effect transistor Q2 accesses SDA port signals of the graphics card, and the field effect transistor Q1 outputs signals to the SCL port of the master control MCU. The field effect transistor Q2 outputs a signal to an SDA port of the master control MCU, and 1.8 V voltage is connected to a grid electrode of the field effect transistor Q1 and a grid electrode of the field effect transistor Q2. The level conversion circuit is low in cost, the level conversion effect between the display card and the MCU is good, and the conversion efficiency is better.

Description

Technical Field

[0001] The utility model relates to the technical field of graphics card PCB, in particular to a graphics card IIC level conversion circuit. Background Art

[0002] The graphics card and MCU are usually connected through a serial communication bus, and level conversion is involved in the communication process. The existing PCB uses level conversion IC, which increases material costs and has a poor conversion effect. It is easy to cause damage to electronic components due to voltage problems, affecting the communication between the two. Summary of the invention

[0003] The utility model provides a graphics card IIC level conversion circuit, aiming to solve the problems of high cost and poor conversion effect of the level conversion circuit on the existing PCB board.

[0004] The utility model provides a graphics card IIC level conversion circuit, comprising a graphics card, a main control MCU, a field effect tube Q1 and a field effect tube Q2, wherein the field effect tube Q1 is connected to the SCL port signal of the graphics card, and the field effect tube Q1 outputs a signal to the SCL port of the main control MCU, the field effect tube Q2 is connected to the SDA port signal of the graphics card, and the field effect tube Q2 outputs a signal to the SDA port of the main control MCU, and the gate of the field effect tube Q1 and the gate of the field effect tube Q2 are both connected to a 1.8V voltage.

[0005] As a further improvement of the present invention, it also includes a resistor R1, one end of which is connected to the SDA port of the graphics card, the other end of which is connected to the source of the field effect transistor Q2, and the drain of the field effect transistor Q2 is connected to the SDA port of the main control MCU.

[0006] As a further improvement of the present invention, it also includes a resistor R2, one end of which is connected to the SCL port of the graphics card, the other end of which is connected to the source of the field effect transistor Q1, and the drain of the field effect transistor Q1 is connected to the SCL port of the main control MCU.

[0007] As a further improvement of the present invention, a resistor R3 is further included, one end of the resistor R3 is connected to the drain of the field effect transistor Q1, and the other end of the resistor R3 is connected to a 3.3V voltage.

[0008] As a further improvement of the present invention, a resistor R4 is further included, one end of the resistor R4 is connected to the drain of the field effect tube Q2, and the other end of the resistor R4 is connected to a 3.3V voltage.

[0009] As a further improvement of the present invention, when the graphics card sends data 1 to the main control MCU, the SCL port of the graphics card and the SDA port of the graphics card are both at a high level, the field effect transistor Q1 and the field effect transistor Q2 are not turned on, and the levels of the SDA port and the SCL port of the main control MCU remain at a high level.

[0010] As a further improvement of the present invention, when the graphics card sends data 0 to the main control MCU, the SCL port and the SDA port of the graphics card are both at a low level, the field effect transistor Q1 and the field effect transistor Q2 are turned on, and the levels of the SDA port and the SCL port of the main control MCU are converted to a low level.

[0011] As a further improvement of the present invention, when the main control MCU sends data 1 to the graphics card, the levels of the SDA port and the SCL port of the main control MCU are high, the field effect transistor Q1 and the field effect transistor Q2 are not turned on, and the levels of the SCL port and the SDA port of the graphics card remain high.

[0012] As a further improvement of the present invention, when the main control MCU sends data 0 to the graphics card, the levels of the SDA port and the SCL port of the main control MCU are low, the field effect transistor Q1 and the field effect transistor Q2 are turned on, and the levels of the SCL port and the SDA port of the graphics card are changed to low.

[0013] The beneficial effects of the utility model are as follows: the level conversion circuit of the scheme has low cost, and the level conversion effect between the graphics card and the MCU is good, and the conversion efficiency is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a connection relationship diagram between the modules of the utility model;

[0015] Figure 2 It is a specific circuit connection diagram of the level conversion circuit of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0017] like Figure 1-2As shown, the utility model provides a graphics card IIC level conversion circuit, including a graphics card, a main control MCU, a field effect tube Q1 and a field effect tube Q2, the field effect tube Q1 is connected to the SCL port signal of the graphics card, the field effect tube Q1 outputs a signal to the SCL port of the main control MCU, the field effect tube Q2 is connected to the SDA port signal of the graphics card, the field effect tube Q2 outputs a signal to the SDA port of the main control MCU, and the gate of the field effect tube Q1 and the gate of the field effect tube Q2 are both connected to a 1.8V voltage.

[0018] As an embodiment of the utility model, it also includes a resistor R1, one end of the resistor R1 is connected to the SDA port of the graphics card, the other end of the resistor R1 is connected to the source of the field effect transistor Q2, and the drain of the field effect transistor Q2 is connected to the SDA port of the main control MCU.

[0019] As another embodiment of the utility model, it also includes a resistor R2, one end of the resistor R2 is connected to the SCL port of the graphics card, the other end of the resistor R2 is connected to the source of the field effect transistor Q1, and the drain of the field effect transistor Q1 is connected to the SCL port of the main control MCU.

[0020] As another embodiment of the present invention, a resistor R3 is further included, one end of the resistor R3 is connected to the drain of the field effect transistor Q1, and the other end of the resistor R3 is connected to a 3.3V voltage.

[0021] As another embodiment of the present invention, a resistor R4 is further included, one end of the resistor R4 is connected to the drain of the field effect transistor Q2, and the other end of the resistor R4 is connected to a 3.3V voltage.

[0022] As another embodiment of the utility model, when the graphics card sends data 1 to the main control MCU, the SCL port of the graphics card and the SDA port of the graphics card are both at a high level, the field effect transistor Q1 and the field effect transistor Q2 are not conducting, and the levels of the SDA port and the SCL port of the main control MCU remain at a high level.

[0023] As another embodiment of the present utility model, when the graphics card sends data 0 to the main control MCU, the SCL port of the graphics card and the SDA port of the graphics card are both at a low level, the field effect transistor Q1 and the field effect transistor Q2 are turned on, and the levels of the SDA port and the SCL port of the main control MCU are converted to a low level.

[0024] As another embodiment of the utility model, when the main control MCU sends data 1 to the graphics card, the levels of the SDA port and the SCL port of the main control MCU are high, the field effect transistor Q1 and the field effect transistor Q2 are not turned on, and the levels of the SCL port and the SDA port of the graphics card remain high.

[0025] As another embodiment of the utility model, when the main control MCU sends data 0 to the graphics card, the levels of the SDA port and the SCL port of the main control MCU are low, the field effect transistor Q1 and the field effect transistor Q2 are turned on, and the levels of the SCL port and the SDA port of the graphics card are converted to low.

[0026] The utility model provides a graphics card IIC level conversion circuit. Figure 2 In the circuit, the 1V8_MISC terminal is based on the level of the graphics card shown, and cannot be higher than 1.8V, otherwise the circuit will be damaged, so this circuit is needed for level conversion. I2CB_SDA_Q and I2CB_SCL_Q are signals on the graphics card side. The graphics card side is operated by the host and sends and receives data to the slave. I2CB_SDA_Q* and I2CB_SCL_Q* are signals on the MCU side, which can only be operated by the slave to receive and send host data. The difference between the master and the slave is actually a triggering function. The host actively triggers, and the slave can only passively respond to the trigger. In the circuit of this scheme, the graphics card and the master MCU can be used as both a host and a slave.

[0027] The working principle of this circuit is:

[0028] When there is no data to be sent on the bus, neither side actively pulls the bus down, so the field effect transistor Q1 and the field effect transistor Q2 are not turned on. Because of the existence of their respective pull-up resistors, the left side is a high level of 1.8V and the right side is a high level of 3.3V.

[0029] When the graphics card needs to send data 1 to the main control MCU, that is, I2CB_SDA_Q / I2CB_SCL_Q is at a high level of 1.8V, Vgs of the field effect transistors Q1 and Q2 is 0, and they are not conducting. Because of the pull-up resistor, the levels of I2CB_SDA_Q* and I2CB_SCL_Q* of the main control MCU remain at 3.3V. This means that the graphics card normally sends data 1 to the main control MCU. Vgs is the voltage between the gate and the source.

[0030] When the graphics card needs to send data 0 to the main control MCU, that is, I2CB_SDA_Q / I2CB_SCL_Q is low level 0V, Vgs=1.8V, the field effect transistors Q1 and Q2 are turned on, the voltage of the main control MCU is the same as the graphics card level, and I2CB_SDA_Q* / I2CB_SCL_Q* is low level 0V. It can be regarded that the graphics card normally sends data 0 to the main control MCU.

[0031] When the master MCU needs to send data 1 to the graphics card, that is, I2CB_SDA_Q* / I2CB_SCL_Q* is at a high level of 3.3V, the graphics card I2CB_SDA_Q / I2CB_SCL_Q does not actively pull down the bus, so the field effect transistors Q1 and Q2 are not turned on, and the graphics card maintains a pull-up level of 1.8V. This means that the master MCU sends data 1 to the graphics card normally.

[0032] When the master MCU needs to send data 0 to the graphics card, that is, when I2CB_SDA_Q* / I2CB_SCL_Q* is at a low level of 0V, the S pole of the MOS tube is pulled down, Vgs is close to 1.8V, and the field effect tubes Q1 and Q2 are turned on, further causing the graphics card and the master MCU to have the same level of 0V. This means that the master MCU normally sends data 0 to the graphics card.

[0033] There are two points to note in this circuit: one is the access method of the MOS tube. The source of the field effect tube Q1 and the field effect tube Q2 should be connected to the low power supply side and cannot be connected in reverse; the other is the selection of the MOS tube. The MOS tube conduction voltage threshold needs to be smaller than the low power supply voltage.

[0034] The gate threshold voltage is to make the MOS conduct, and Vgsth is the voltage required between the gate and the source. In other words, if Vgs is a voltage above the threshold, the MOS tube is turned on. In this circuit, the field effect tube Q1 and the field effect tube Q2 are PJT7828, and the Vgsth of PJT7828 is 1V, which is less than 1.8V, so this selection meets the requirements.

[0035] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A graphics card IIC level conversion circuit, characterized in that: It includes a graphics card, a main control MCU, a field effect tube Q1 and a field effect tube Q2, the field effect tube Q1 is connected to the SCL port signal of the graphics card, the field effect tube Q1 outputs a signal to the SCL port of the main control MCU, the field effect tube Q2 is connected to the SDA port signal of the graphics card, the field effect tube Q2 outputs a signal to the SDA port of the main control MCU, and the gate of the field effect tube Q1 and the gate of the field effect tube Q2 are both connected to a 1.8V voltage.

2. A graphics card IIC level conversion circuit according to claim 1, characterized in that: It also includes a resistor R1, one end of which is connected to the SDA port of the graphics card, the other end of which is connected to the source of the field effect transistor Q2, and the drain of the field effect transistor Q2 is connected to the SDA port of the main control MCU.

3. A graphics card IIC level conversion circuit according to claim 1, characterized in that: It also includes a resistor R2, one end of which is connected to the SCL port of the graphics card, the other end of which is connected to the source of the field effect transistor Q1, and the drain of the field effect transistor Q1 is connected to the SCL port of the main control MCU.

4. A graphics card IIC level conversion circuit according to claim 1, characterized in that: It also includes a resistor R3, one end of which is connected to the drain of the field effect transistor Q1, and the other end of which is connected to a 3.3V voltage.

5. The graphics card IIC level conversion circuit according to claim 1, characterized in that: It also includes a resistor R4, one end of which is connected to the drain of the field effect tube Q2, and the other end of which is connected to a 3.3V voltage.

6. A graphics card IIC level conversion circuit according to claim 1, characterized in that: When the graphics card sends data 1 to the main control MCU, the SCL port and the SDA port of the graphics card are both at a high level, the field effect transistor Q1 and the field effect transistor Q2 are not turned on, and the levels of the SDA port and the SCL port of the main control MCU remain at a high level.

7. A graphics card IIC level conversion circuit according to claim 1, characterized in that: When the graphics card sends data 0 to the main control MCU, the SCL port and the SDA port of the graphics card are both at low levels, the field effect transistor Q1 and the field effect transistor Q2 are turned on, and the levels of the SDA port and the SCL port of the main control MCU are converted to low levels.

8. The graphics card IIC level conversion circuit according to claim 1, characterized in that: When the master MCU sends data 1 to the graphics card, the levels of the SDA port and the SCL port of the master MCU are high, the field effect transistor Q1 and the field effect transistor Q2 are not turned on, and the levels of the SCL port and the SDA port of the graphics card remain high.

9. The graphics card IIC level conversion circuit according to claim 1, characterized in that: When the master MCU sends data 0 to the graphics card, the levels of the SDA port and the SCL port of the master MCU are low, the field effect transistor Q1 and the field effect transistor Q2 are turned on, and the levels of the SCL port and the SDA port of the graphics card are changed to low.

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