High-precision digital display angle measuring instrument

Abstract

The utility model relates to the technical field of angle measurement, in particular to a high-precision digital display angle measuring instrument. Comprising a control chip; the inductor is used for acquiring an angle signal and is connected with the control chip through the level conversion circuit to transmit the angle signal; the communication circuit is connected with the control chip and transmits an angle signal to an external terminal; the battery management circuit is connected with the control chip through a buck-boost circuit and outputs a first power supply voltage and a second power supply voltage; and the switch control circuit is connected with the battery management circuit. According to the utility model, hardware which is simple and high in integration level is adopted to reduce the size and the cost, a communication circuit is utilized to improve the transmission distance of data, and the device has the advantages of simple structure, simplicity and convenience in operation, high measurement precision and strong anti-interference capability.

Description

Technical Field

[0001] The utility model relates to the technical field of angle measurement, in particular to a high-precision digital display angle measuring instrument. Background Art

[0002] Angle measurement technology is widely used in many fields such as mechanical manufacturing, construction engineering, electronics and electrical, aerospace, etc. In these applications, the accuracy and reliability of angle measurement directly affect product quality and engineering accuracy. At present, angle measurement technology mainly includes three categories: mechanical measurement, electrical measurement and optical measurement.

[0003] Mechanical angle measuring instruments include protractors, indexing plates, optical indexing plates, etc. Their disadvantages are low accuracy, usually around 0.1 degrees, and they are easily affected by mechanical wear and external environment, resulting in unstable measurement results.

[0004] The electrical angle measuring instrument realizes angle measurement through electrical components such as potentiometers, rotary transformers, induction synchronizers, etc. Its disadvantage is that the operation is relatively complicated and it is not suitable for fast and frequent measurement applications.

[0005] Optical angle measuring instruments use optical components such as photoelectric encoders and laser interferometers to measure angles. Their disadvantages are complex structure, high cost, and high environmental requirements. Factors such as light, temperature, and humidity may affect the measurement results. Utility Model Content

[0006] The purpose of this utility model is to provide a high-precision digital angle measuring instrument to solve the above technical problems;

[0007] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0008] A high-precision digital angle measuring instrument, comprising:

[0009] Control chip;

[0010] A sensor, which obtains an angle signal, wherein the sensor is connected to the control chip through a level conversion circuit to transmit the angle signal;

[0011] A communication circuit, connected to the control chip, transmitting the angle signal to an external terminal;

[0012] A battery management circuit is connected to the control chip via a buck-boost circuit to output a first power supply voltage and a second power supply voltage;

[0013] The switch control circuit is connected to the battery management circuit.

[0014] Preferably, the sensor adopts a 3D-MEMS-based sensing chip, and two acceleration sensing elements are arranged in the sensor, and the measuring axes of the two acceleration sensing elements are parallel to the installation plane and orthogonal to each other.

[0015] Preferably, the buck-boost circuit adopts a single-ended start-up flyback topology structure, and the buck-boost circuit is connected to a switch control signal output by the switch control circuit.

[0016] Preferably, the control chip, the sensor, the communication circuit, the battery management circuit and the switch control circuit are all arranged in an outer shell, the outer surface of the outer shell is embedded with a magnet, the outer shell can be magnetically attracted to an external measuring device through the magnet, and the outer side of the outer shell is provided with an impact-resistant layer and a wear-resistant layer.

[0017] Preferably, it also includes a display driving circuit and a power collection circuit, the control chip is connected to the display screen through the display driving circuit to output the angle signal, and the power collection circuit is connected to the display screen to output a remaining power signal.

[0018] Preferably, the communication circuit includes a communication circuit and a LoRa wireless communication circuit, the communication circuit is connected to the control chip via an interface, and the interface is provided with an isolation chip and an electrostatic protection circuit;

[0019] The communication circuit comprises:

[0020] An isolation chip connected to the control chip;

[0021] a converter chip, wherein the converter chip is connected to the isolation chip, and the converter chip outputs a third power supply voltage based on the second power supply voltage;

[0022] A transceiver chip connected to the isolation chip;

[0023] The LoRa wireless communication circuit is provided with a LoRa chip, and the LoRa chip is connected to the control chip.

[0024] Preferably, the level conversion circuit comprises a level conversion chip, a first level receiving pin of the level conversion chip is connected to a first level output pin of the control chip, a first transmission end pin of the level conversion chip is connected to a first serial transmission pin of the control chip, a first logic pin of the level conversion chip is connected to a level conversion control pin of the control chip, a second logic pin of the level conversion chip is grounded, a first power pin of the level conversion chip is connected to the first power supply voltage, a second power pin of the level conversion chip is connected to the second power supply voltage, and a ground pin of the level conversion chip is grounded;

[0025] The level conversion circuit further includes:

[0026] A first capacitor, wherein a first end of the first capacitor is connected to a first power pin of the level conversion chip, and a second end of the first capacitor is connected to a second logic pin of the level conversion chip;

[0027] A second capacitor, a first end of the second capacitor is connected to a second power pin of the level conversion chip, and a second end of the second capacitor is grounded;

[0028] A sensing chip, wherein a transmission end pin of the sensing chip is connected to a second transmission end pin of the level conversion chip, an output pin of the sensing chip is connected to a first receiving pin of the level conversion chip, a power supply pin of the sensing chip is connected to the first power supply voltage, and a ground pin of the sensing chip is grounded;

[0029] The sensor further includes a third capacitor, a first end of the third capacitor is connected to a power pin of the sensor chip, and a second end of the third capacitor is grounded.

[0030] Preferably, the battery management circuit comprises:

[0031] A battery management chip, wherein a temperature monitoring pin of the battery management chip is connected to a thermistor voltage, and an analog ground pin of the battery management chip is grounded;

[0032] a first diode, wherein an anode of the first diode is connected to a charging voltage;

[0033] a second diode, wherein an anode of the second diode is connected to an input voltage (IN), and a cathode of the second diode is connected to a cathode of the first diode;

[0034] a twentieth resistor, wherein a first end of the twentieth resistor is connected to the cathode of the second diode, and a second end of the twentieth resistor is connected to the first power pin of the battery management chip;

[0035] a ninth capacitor, wherein a first end of the ninth capacitor is connected to the second end of the 20th resistor, and a second end of the ninth capacitor is grounded;

[0036] a twenty-first resistor, a first end of the twenty-first resistor being connected to the input voltage;

[0037] a tenth capacitor, a first end of the tenth capacitor being connected to the second end of the twenty-first resistor, and a second end of the tenth capacitor being grounded;

[0038] A first MOS transistor, wherein a drain of the first MOS transistor is connected to the input voltage;

[0039] a twenty-second resistor, wherein a first end of the twenty-second resistor is connected to the gate of the first MOS tube, and a second end of the twenty-second resistor is connected to the first driving pin of the battery management chip;

[0040] a twenty-third resistor, wherein a first end of the twenty-third resistor is connected to the source of the first MOS tube, and a second end of the twenty-third resistor is connected to the current detection pin of the battery management chip;

[0041] a second MOS transistor, wherein a source of the second MOS transistor is connected to a source of the first MOS transistor, a gate of the second MOS transistor is connected to a first end of a twenty-second resistor, and a drain of the second MOS transistor is connected to a first positive input pin of the battery management chip;

[0042] a twenty-fourth resistor, wherein a first end of the twenty-fourth resistor is connected to the drain of the second MOS tube, a second end of the twenty-fourth resistor is connected to the second power pin, the third power pin and the first negative input pin of the battery management chip, and a power supply voltage is output from the second end of the twenty-fourth resistor;

[0043] an eleventh capacitor, a first end of the eleventh capacitor being connected to the first end of the twenty-fourth resistor, and a second end of the eleventh capacitor being connected to the second end of the twenty-fourth resistor;

[0044] a twelfth capacitor, wherein a first end of the twelfth capacitor is connected to a second power pin of the battery management chip, and a second end of the twelfth capacitor is grounded;

[0045] A twenty-fifth resistor, a first end of the twenty-fifth resistor being connected to a reference voltage;

[0046] an indicator light, wherein a positive electrode of the indicator light is connected to a first end of the twenty-fifth resistor, and a negative electrode of the indicator light is connected to a status indication pin of the battery management chip;

[0047] a twenty-sixth resistor, a first end of the twenty-sixth resistor being connected to the first end of the twenty-fifth resistor, and a second end of the twenty-sixth resistor being connected to the temperature monitoring pin of the battery management chip;

[0048] a twenty-seventh resistor, a first end of the twenty-seventh resistor being connected to the second end of the twenty-sixth resistor, and a second end of the twenty-seventh resistor being grounded;

[0049] A thirteenth capacitor, a first end of the thirteenth capacitor is connected to the termination control pin of the battery management chip, and a first end of the thirteenth capacitor is grounded;

[0050] A fourteenth capacitor, a first end of the fourteenth capacitor is connected to the first switch pin and the second switch pin of the battery management chip, and a second end of the fourteenth capacitor is connected to the temperature compensation pin of the battery management chip;

[0051] a third diode, wherein a cathode of the third diode is connected to the first end of the fourteenth capacitor, and an anode of the third diode is grounded;

[0052] a first inductor, wherein a first end of the first inductor is connected to a cathode of the third diode, and a second end of the first inductor is connected to a second positive input pin of the battery management chip;

[0053] a twenty-eighth resistor, wherein a first end of the twenty-eighth resistor is connected to the second end of the first inductor, a second end of the twenty-eighth resistor is connected to the second negative input pin of the battery management chip, and the charging voltage is outputted from the second end of the twenty-eighth resistor;

[0054] a fifteenth capacitor, a first end of the fifteenth capacitor being connected to the first end of the twenty-eighth resistor, and a second end of the fifteenth capacitor being connected to the second end of the twenty-eighth resistor;

[0055] a sixteenth capacitor, a first end of the sixteenth capacitor being connected to the second end of the twenty-eighth resistor, and a second end of the sixteenth capacitor being grounded;

[0056] a seventeenth capacitor, a first end of the seventeenth capacitor being connected to the second end of the twenty-eighth resistor, and a second end of the seventeenth capacitor being grounded;

[0057] a third MOS transistor, wherein a drain of the third MOS transistor is connected to the second end of the twenty-eighth resistor, and a source of the third MOS transistor is connected to the power supply voltage;

[0058] an eighteenth capacitor, a first end of the eighteenth capacitor being connected to the second end of the eleventh capacitor, and a second end of the eighteenth capacitor being grounded;

[0059] A nineteenth capacitor, wherein a first end of the nineteenth capacitor is connected to an output voltage pin of the battery management chip, and a second end of the nineteenth capacitor is connected to a first power ground pin and a second power ground pin of the battery management chip and then grounded;

[0060] a twenty-ninth resistor, wherein a first end of the twenty-ninth resistor is connected to the second driving pin of the battery management chip, and a second end of the twenty-ninth resistor is connected to the gate of the third MOS tube;

[0061] a twentieth capacitor, wherein a first end of the twentieth capacitor is connected to the second end of the first inductor, and a second end of the twentieth capacitor is grounded;

[0062] a 30th resistor, a first end of the 30th resistor being connected to the first setting pin of the battery management chip, and a second end of the 30th resistor being connected to the reference voltage;

[0063] a thirty-first resistor, a first end of the thirty-first resistor being connected to the second end of the thirtieth resistor, and a second end of the thirty-first resistor being grounded;

[0064] a thirty-second resistor, a first end of the thirty-second resistor being connected to the battery voltage, and a second end of the thirty-second resistor being connected to the protection pin of the battery management chip;

[0065] a thirty-third resistor, a first end of the thirty-third resistor being connected to the second end of the thirty-second resistor, and a second end of the thirty-third resistor being grounded;

[0066] a thirty-fourth resistor, a first end of the thirty-fourth resistor being connected to the drain of the third MOS tube, and a second end of the thirty-fourth resistor being connected to the feedback pin of the battery management chip;

[0067] a thirty-fifth resistor, a first end of the thirty-fifth resistor being connected to the second end of the thirty-fourth resistor, and a second end of the thirty-fifth resistor being grounded;

[0068] A thirty-sixth resistor, a first end of the thirty-sixth resistor is connected to the fourth power pin of the battery management chip and then connected to the reference voltage, and a second end of the thirty-sixth resistor is connected to the second setting pin of the battery management chip;

[0069] a thirty-seventh resistor, a first end of the thirty-seventh resistor being connected to the second end of the thirty-sixth resistor, and a second end of the thirty-seventh resistor being grounded;

[0070] A twenty-first capacitor, wherein a first end of the twenty-first capacitor is connected to the first end of the thirty-sixth resistor, and a second end of the twenty-first capacitor is grounded.

[0071] Preferably, the switch control circuit comprises:

[0072] a switch control chip, wherein a power pin of the switch control chip is connected to the power supply voltage, an interrupt output pin of the switch control chip is connected to an interrupt control pin of the control chip, and an enable output pin of the switch control chip is connected to a forty-fourth resistor and then connected to a drive control pin of the control chip;

[0073] a 42nd resistor, wherein a first end of the 42nd resistor is connected to a power pin of the switch control chip, and a second end of the 42nd resistor is connected to a monitoring input pin of the switch control chip;

[0074] a forty-third resistor, a first end of the forty-third resistor being connected to the second end of the forty-second resistor, and a second end of the forty-third resistor being grounded;

[0075] a twenty-ninth capacitor, wherein a first end of the twenty-ninth capacitor is connected to the first end of the forty-second resistor, and a second end of the twenty-ninth capacitor is grounded;

[0076] a 30th capacitor, a first end of the 30th capacitor being connected to the timer pin of the switch control chip, and a second end of the 30th capacitor being grounded;

[0077] a fourth MOS tube, wherein a drain of the fourth MOS tube is connected to the first end of the twenty-ninth capacitor, a gate of the fourth MOS tube is connected to the enable pin of the switch control chip, and a source of the fourth MOS tube generates the switch control signal;

[0078] a forty-fifth resistor, wherein a first end of the forty-fifth resistor is connected to the gate of the fourth MOS tube, and a second end of the forty-fifth resistor is connected to the ground pin of the switch control chip and then grounded;

[0079] a forty-sixth resistor, wherein a first end of the forty-sixth resistor is connected to the second supply voltage, and a second end of the forty-sixth resistor is connected to an enable output pin of the switch control chip;

[0080] a forty-seventh resistor, wherein a first end of the forty-seventh resistor is connected to the second power supply voltage, and a second end of the forty-seventh resistor is connected to an interrupt output pin of the switch control chip;

[0081] A first connector, wherein a first pin of the first connector is grounded, a second pin of the first connector is connected to a holding pin of the control chip, a third pin of the first connector is connected to a second reset control pin of the control chip, and a fourth pin of the first connector is connected to a button input pin of the switch control chip to receive a system switch signal (Y);

[0082] a first protection diode, wherein a first end of the first protection diode is connected to the fourth pin of the first connector, and a second end of the first protection diode is connected to the first pin of the first connector;

[0083] a thirty-first capacitor, a first end of the thirty-first capacitor being connected to the first end of the first protection diode, and a second end of the thirty-first capacitor being connected to the second end of the first protection diode;

[0084] a second protection diode, wherein a first end of the second protection diode is connected to the third pin of the first connector, and a second end of the first protection diode is connected to the first pin of the first connector;

[0085] a thirty-second capacitor, a first end of the thirty-second capacitor being connected to the first end of the second protection diode, and a second end of the thirty-second capacitor being connected to the second end of the second protection diode;

[0086] a third protection diode, wherein a first end of the third protection diode is connected to the second pin of the first connector, and a second end of the third protection diode is connected to the first pin of the first connector;

[0087] a thirty-third capacitor, a first end of the thirty-third capacitor being connected to the first end of the third protection diode, and a second end of the thirty-third capacitor being connected to the second end of the third protection diode;

[0088] a forty-eighth resistor, wherein a first end of the forty-eighth resistor is connected to the second supply voltage, and a second end of the forty-eighth resistor is connected to a first end of the thirty-first capacitor;

[0089] a forty-ninth resistor, wherein a first end of the forty-ninth resistor is connected to the first end of the forty-eighth resistor, and a second end of the forty-ninth resistor is connected to the first end of the thirty-second capacitor;

[0090] A fiftieth resistor, a first end of the fiftieth resistor is connected to a first end of the forty-eighth resistor, and a second end of the fiftieth resistor is connected to a first end of the thirty-third capacitor.

[0091] Preferably, it also includes,

[0092] a fourth inductor, wherein a first end of the fourth inductor is connected to the second supply voltage, a second end of the fourth inductor is connected to an analog power pin of the control chip, and a power pin of the control chip is connected to the second supply voltage;

[0093] a fifth inductor, wherein a first end of the fifth inductor is connected to an analog ground pin of the control chip, and a second end of the fifth inductor is connected to a ground pin of the control chip and then grounded;

[0094] a thirty-seventh capacitor, a first end of the thirty-seventh capacitor being connected to an analog power pin of the control chip, and a second end of the thirty-seventh capacitor being connected to an analog ground pin of the control chip;

[0095] A crystal oscillator, wherein a first crystal pin of the crystal oscillator is connected to a first crystal oscillator pin of the control chip, a second crystal pin of the crystal oscillator is connected to a second crystal oscillator pin of the control chip, and a ground pin of the crystal oscillator is grounded;

[0096] a fifty-third resistor, wherein a first end of the fifty-third resistor is connected to a first crystal pin of the crystal oscillator, and a second end of the fifty-third resistor is connected to a second crystal pin of the crystal oscillator;

[0097] a thirty-eighth capacitor, a first end of the thirty-eighth capacitor being connected to the first crystal pin of the crystal oscillator, and a second end of the thirty-eighth capacitor being connected to the ground pin of the crystal oscillator;

[0098] a thirty-ninth capacitor, wherein a first end of the thirty-ninth capacitor is connected to the second crystal pin of the crystal oscillator, and a second end of the thirty-ninth capacitor is connected to the ground pin of the crystal oscillator;

[0099] a fifty-fourth resistor, a first end of the fifty-fourth resistor being connected to the start pin of the control chip, and a second end of the fifty-fourth resistor being grounded;

[0100] a third connector, wherein a first pin of the third connector is grounded, a second pin of the third connector is connected to a second clock signal pin of the control chip, a third pin of the third connector is connected to a data transmission pin of the control chip, and a fourth pin of the third connector is connected to the second power supply voltage;

[0101] a fortieth capacitor, wherein a first end of the fortieth capacitor is connected to the fourth pin of the third connector, and a second end of the fortieth capacitor is grounded;

[0102] a fifty-fifth resistor, wherein a first end of the fifty-fifth resistor is connected to the second supply voltage, and a second end of the fifty-fifth resistor is connected to a reset pin of the control chip;

[0103] a forty-first capacitor, a first end of the forty-first capacitor being connected to the second end of the fifty-fifth resistor, and a second end of the forty-first capacitor being grounded;

[0104] a forty-fifth capacitor, a first end of the forty-fifth capacitor being connected to the second supply voltage, and a second end of the forty-fifth capacitor being grounded;

[0105] a forty-sixth capacitor, wherein a first end of the forty-sixth capacitor is connected to the first end of the forty-fifth capacitor, and a second end of the forty-sixth capacitor is connected to the second end of the forty-fifth capacitor;

[0106] a forty-seventh capacitor, wherein a first end of the forty-seventh capacitor is connected to the first end of the forty-fifth capacitor, and a second end of the forty-seventh capacitor is connected to the second end of the forty-fifth capacitor;

[0107] Also included is an interface circuit, the interface circuit comprising,

[0108] A USB connector, wherein a first transmission pin of the USB connector is connected to a second transmission pin of the transceiver chip, and the second transmission pin of the USB connector is connected to a first transmission pin of the transceiver chip;

[0109] a 42nd capacitor, wherein a first end of the 42nd capacitor is connected to a power pin of the USB connector, and a second end of the 42nd capacitor is grounded;

[0110] a forty-third capacitor, wherein a first end of the forty-third capacitor is connected to the first end of the forty-second capacitor, and a second end of the forty-third capacitor is connected to the second end of the forty-second capacitor;

[0111] a 44th capacitor, wherein a first end of the 44th capacitor is connected to the first end of the 42nd capacitor, and a second end of the 44th capacitor is connected to the second end of the 42nd capacitor;

[0112] a fifth MOS tube, wherein the drain of the fifth MOS tube is connected to the power pin of the USB connector, and the source of the fifth MOS tube is connected to the battery management circuit;

[0113] a fifty-sixth resistor, wherein a first end of the fifty-sixth resistor is connected to the gate of the fifth MOS tube, and a second end of the fifty-sixth resistor is grounded;

[0114] a fifty-seventh resistor, wherein a first end of the fifty-seventh resistor is connected to the gate of the fifth MOS transistor, and a second end of the fifty-seventh resistor is connected to the source of the fifth MOS transistor;

[0115] A fourth connector, wherein a first pin of the fourth connector is connected to a source of the fifth MOS tube, and a second pin of the fourth connector is connected to a second end of the fifty-sixth resistor.

[0116] The beneficial effects of the utility model are as follows: due to the adoption of the above technical scheme, the utility model adopts simple and highly integrated hardware to reduce the volume and reduce the cost, utilizes the communication circuit to increase the data transmission distance, and has the advantages of simple structure, easy operation, high measurement accuracy and strong anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0117] Figure 1 This is a hardware framework diagram of a high-precision digital display angle measuring instrument in an embodiment of the utility model;

[0118] Figure 2 This is a connection diagram of the control chip in the embodiment of the utility model;

[0119] Figure 3 This is a connection diagram of a level conversion chip in an embodiment of the utility model;

[0120] Figure 4 This is a schematic diagram of the connection of the sensing chip in the embodiment of the utility model;

[0121] Figure 5A schematic diagram of a RS485 communication circuit in an embodiment of the present utility model;

[0122] Figure 6 A schematic diagram of a RS485 communication circuit in an embodiment of the present utility model;

[0123] Figure 7 This is a circuit diagram of a LoRa wireless communication circuit in an embodiment of the present utility model;

[0124] Figure 8 This is a circuit diagram of a battery management circuit in an embodiment of the utility model;

[0125] Fig. 9 This is a circuit diagram of a buck-boost circuit in an embodiment of the utility model;

[0126] Fig.10 This is a circuit diagram of a switch control circuit in an embodiment of the utility model;

[0127] Fig.11 This is a circuit diagram of a switch control circuit in an embodiment of the utility model;

[0128] Fig.12 This is a circuit diagram of the power collection circuit in the embodiment of the utility model;

[0129] Fig.13 It is a circuit diagram of a display driving circuit in an embodiment of the utility model;

[0130] Fig.14 This is a circuit diagram of an interface circuit in an embodiment of the utility model;

[0131] Fig.15 This is a schematic diagram of the connection of the crystal oscillator in the embodiment of the utility model;

[0132] Fig.16 This is a connection diagram of the fifty-fourth resistor in the embodiment of the utility model;

[0133] Fig.17 This is a connection diagram of the third connector in the embodiment of the utility model;

[0134] Fig.18 This is a connection diagram of the forty-fifth capacitor in the embodiment of the utility model. DETAILED DESCRIPTION

[0135] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0136] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0137] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0138] A high-precision digital angle measuring instrument, such as Figures 1 to 18 As shown, including,

[0139] Control chip U1;

[0140] Sensor 2 obtains the angle signal, and the sensor 2 is connected to the control chip U1 through the level conversion circuit 3 to transmit the angle signal;

[0141] Communication circuit 4, connected to control chip U1, transmits angle signal to external terminal;

[0142] The battery management circuit 5 is connected to the control chip U1 via a buck-boost circuit 51 to output a first power supply voltage V1 and a second power supply voltage V2;

[0143] The switch control circuit 6 is connected to the battery management circuit 5 .

[0144] Specifically, the control chip U1 of the utility model adopts the F1 series chip of the 32-bit MCU control chip U1STM32, which reduces the overall power consumption and improves the computing power and stability of digital signals; the sensor 2 adopts the SCA100T-D02 chip based on 3D-MEMS technology.

[0145] The 32-bit STM32F103C8T6 is used as the control chip U1, which has strong data processing capabilities, low power consumption, and can ensure stable operation of the system. The SCA100T-D02 chip communicates with the control chip U1 through SPI. The communication signal is converted by the level conversion chip U2 of the level conversion circuit 3. The level conversion chip U2 uses the SN74LVC4245A chip to solve the problem of mismatch in communication signal levels.

[0146] In the current context of environmental protection and sustainable development, green environmental protection and low energy consumption design have become important considerations in product design. In the design process, the utility model fully considers the environmental protection and energy consumption control of materials, and reduces energy consumption and environmental burden by optimizing circuit design and selecting low-power components, actively responding to the call for green environmental protection.

[0147] The high-precision digital angle measuring instrument of the utility model is applied to many industries such as manufacturing, construction engineering, aerospace, precision instruments and equipment, etc. It adopts a high-resolution angle sensor to provide sub-second accuracy to ensure the accuracy of angle measurement. The measuring range is ±90°, the resolution is 0.001°, there are two measuring axes, X and Y, and the data bandwidth can reach up to 18Hz.

[0148] The utility model has a built-in automatic calibration function, which can be calibrated regularly or on demand to ensure the long-term accuracy and stability of the measurement.

[0149] It also integrates real-time data analysis functions, which can provide instant feedback of measurement results and error analysis, improving measurement efficiency and reliability. It is equipped with dedicated application software, providing rich functions such as data recording, analysis, report generation, etc., to enhance user experience. It adopts waterproof and dustproof structure design, can work normally in harsh environments, and extend the service life of the instrument.

[0150] In a preferred embodiment, the sensor 2 adopts a 3D-MEMS-based sensor chip U3 . Two acceleration sensing elements are arranged in the sensor 2 . The measuring axes of the two acceleration sensing elements are parallel to the installation plane and orthogonal to each other.

[0151] In a preferred embodiment, the buck-boost circuit 51 adopts a single-ended start-up flyback topology structure, and the buck-boost circuit 51 is connected to the switch control signal TURN output by the switch control circuit 6 .

[0152] In a preferred embodiment, the buck-boost circuit 51 includes:

[0153] a fourth diode D4, wherein an anode of the fourth diode D4 is connected to a supply voltage V0;

[0154] A buck-boost chip U9, a power pin U9_5 of the buck-boost chip U9 is connected to the cathode of the fourth diode D4, and a ground pin U9_2 of the buck-boost chip U9 is grounded;

[0155] A twenty-second capacitor C22, a first end of the twenty-second capacitor C22 is connected to the cathode of the fourth diode D4, and a second end of the twenty-second capacitor C22 is connected to the ground pin U9_2 of the buck-boost chip U9;

[0156] A twenty-third capacitor C23, a first end of the twenty-third capacitor C23 is connected to the first end of the twenty-second capacitor C22, and a second end of the twenty-third capacitor C23 is connected to the second end of the twenty-second capacitor C22;

[0157] A thirty-eighth resistor R38, wherein a first end of the thirty-eighth resistor R38 is connected to a switch control signal TURN, and a second end of the thirty-eighth resistor R38 is connected to an enable pin U9_4 of the buck-boost chip U9;

[0158] A thirty-ninth resistor R39, a first end of the thirty-ninth resistor R39 is connected to the first end of the thirty-eighth resistor R38, and a second end of the thirty-ninth resistor R39 is connected to the second end of the twenty-second capacitor C22;

[0159] A second inductor L2, wherein a first end of the second inductor L2 is connected to a cathode of a fourth diode D4, and a second end of the second inductor L2 is connected to a switch pin U9_1 of a buck-boost chip U9;

[0160] A twenty-fourth capacitor C24, a first end of the twenty-fourth capacitor C24 is connected to the second end of the second inductor L2;

[0161] a third inductor L3, wherein a first end of the third inductor L3 is connected to a second end of the twenty-fourth capacitor C24, and a second end of the third inductor L3 is grounded;

[0162] a fifth diode D5, wherein an anode of the fifth diode D5 is connected to the second end of the twenty-fourth capacitor C24, and a cathode of the fifth diode D5 outputs the first supply voltage V1;

[0163] a 40th resistor R40, wherein a first end of the 40th resistor R40 is connected to the cathode of the fifth diode D5, and a second end of the 40th resistor R40 is connected to the feedback pin U9_3 of the buck-boost chip U9;

[0164] a forty-first resistor R41, a first end of the forty-first resistor R41 is connected to the second end of the fortieth resistor R40, and a second end of the forty-first resistor R41 is grounded;

[0165] a twenty-fifth capacitor C25, wherein a first end of the twenty-fifth capacitor C25 is connected to the cathode of the fifth diode D5, and a second end of the twenty-fifth capacitor C25 is connected to the second end of the forty-first resistor R41;

[0166] A twenty-sixth capacitor C26, a first end of the twenty-sixth capacitor C26 is connected to the first end of the twenty-fifth capacitor C25, and a second end of the twenty-sixth capacitor C26 is connected to the second end of the twenty-fifth capacitor C25;

[0167] A twenty-seventh capacitor C27, a first end of the twenty-seventh capacitor C27 is connected to the first end of the twenty-fifth capacitor C25, and a second end of the twenty-seventh capacitor C27 is connected to the second end of the twenty-fifth capacitor C25;

[0168] A voltage stabilizing chip U10, wherein a voltage input pin U10_3 of the voltage stabilizing chip U10 is connected to the cathode of the fifth diode D5, a voltage output pin U10_2 of the voltage stabilizing chip U10 outputs a second power supply voltage V2, and a ground pin U10_1 of the voltage stabilizing chip U10 is grounded;

[0169] The twenty-eighth capacitor C28 has a first end connected to the voltage output pin U10_2 of the voltage regulator chip U10 , and a second end of the twenty-eighth capacitor C28 is grounded.

[0170] The battery management circuit 5 of the utility model is connected to a buck-boost circuit 51 of a single-ended start-up flyback topology (Sepic) structure. The battery management circuit 5 is powered by a lithium battery, which is suitable for application scenarios requiring high portability and mobility, especially field measurement and outdoor use. Its advantages are portability, long battery life, fast charging and good environmental adaptability.

[0171] This utility model adopts a lightweight and compact design, which is easy to carry and operate, and is suitable for various working environments. It provides a variety of adapters and accessories to adapt to different measurement scenarios and requirements, and improve the applicability of the instrument. It uses a high-capacity lithium battery to provide long-term endurance, and supports fast charging and battery management functions. The circuit design is optimized to reduce power consumption, extend battery life, and improve ease of use. It has a built-in storage function, which can store a large amount of measurement data and support fast call and viewing of data.

[0172] The battery management circuit 5 uses the Sepic topology buck-boost circuit 51 of SX1308 to provide power for the entire angle measuring instrument. It has a wide voltage input of 2V to 24V, an output of up to 28V, a current of up to 2A, and a small ripple, meeting the power supply requirements of the system.

[0173] In a preferred embodiment, the control chip U1, the sensor 2, the communication circuit 4, the battery management circuit 5 and the switch control circuit 6 are all arranged in an outer shell, and a magnet is embedded in the outer surface of the outer shell. The outer shell can be magnetically attracted to an external measuring device through the magnet, and an impact-resistant layer and a wear-resistant layer are provided on the outer side of the outer shell.

[0174] The control chip U1, sensor 2, communication circuit 4, battery management circuit 5 and switch control circuit 6 are all arranged in the outer shell, and the outer surface of the outer shell is embedded with a magnet. The outer surface of the structure is embedded with a magnet, which can be magnetically attracted to the measuring device. The use of impact-resistant and wear-resistant materials improves the durability and reliability of the instrument and adapts to various working environments.

[0175] The utility model only consumes 1W of power when working, and has a uA-level standby current. It has the characteristics of small detection angle, high sensitivity, high detection accuracy, strong environmental adaptability, small size, stable performance, easy integration, high cost performance, all-solid-state electronic devices, long service life, and long data communication distance. The high-precision digital angle measuring instrument has achieved higher measurement accuracy, more convenient operation experience and a wider range of application scenarios through innovations in sensor technology, display and human-machine interface, wireless communication, intelligence, portability, power management, data processing, application software and security, greatly improving the user's work efficiency and measurement quality.

[0176] In a preferred embodiment, it also includes a display driving circuit 7 and a power collection circuit. The control chip U1 is connected to the display screen 8 through the display driving circuit 7 to output an angle signal, and the power collection circuit is connected to the display screen 8 to output a remaining power signal.

[0177] The display driving circuit 7 includes:

[0178] A second connector J2 connected to the display screen 8, the first pin J2_1 and the seventh pin of the second connector J2 are grounded, the second pin J2_2 of the second connector J2 is connected to the second power supply voltage V2, the third pin J2_3 of the second connector J2 is connected to the first clock signal pin U1_19 of the control chip U1, the fourth pin J2_4 of the second connector J2 is connected to the display data pin U1_20 of the control chip U1, the fifth pin J2_5 of the second connector J2 is connected to the reset pin U1_39 of the control chip U1, and the sixth pin J2_6 of the second connector J2 is connected to the data selection pin U1_40 of the control chip U1;

[0179] A thirty-fourth capacitor C34, a first end of the thirty-fourth capacitor C34 is connected to the first pin J2_1 of the second connector J2, and a second end of the thirty-fourth capacitor C34 is connected to the second pin J2_2 of the second connector J2;

[0180] The power collection circuit includes:

[0181] A thirty-fifth capacitor C35, a first end of the thirty-fifth capacitor C35 is connected to the analog-to-digital conversion pin U1_11 of the control chip U1, and a second end of the thirty-fifth capacitor C35 is grounded;

[0182] a fifty-first resistor R51, a first end of the fifty-first resistor R51 is connected to the charging voltage Vbat, and a second end of the fifty-first resistor R51 is connected to a first end of the thirty-fifth capacitor C35;

[0183] a fifty-second resistor R52, wherein a first end of the fifty-second resistor R52 is connected to the first end of the fifty-first resistor R51, and a second end of the fifty-second resistor R52 is grounded;

[0184] A thirty-sixth capacitor C36, a first end of the thirty-sixth capacitor C36 is connected to the first end of the fifty-second resistor R52, and a second end of the thirty-sixth capacitor C36 is grounded.

[0185] Specifically, the second connector J2 uses a SHL25-1X7 connector, and the thirty-fourth capacitor C34 uses a 0.1uF / 25V capacitor.

[0186] The thirty-fifth capacitor C35 is a capacitor with a specification of 0.1uF / 25V, the fifty-first resistor R51 has a resistance of 360K ohms, with a deviation within 1%, the fifty-second resistor R52 has a resistance of 130K ohms, with a deviation within 1%, and the thirty-sixth capacitor C36 is a capacitor with a specification of 0.1uF / 25V.

[0187] The introduction of display screen 8 in high-precision digital angle measuring instruments has significant advantages over traditional display technology, including higher accuracy and readability, real-time data update, multi-function display, user-friendliness, data storage and transmission, energy saving and low power consumption, portability and durability, flexible design, safety and protection, etc. These advantages enable digital display measuring instruments to provide excellent performance and user experience in various application scenarios, significantly improving the market competitiveness and practicality of the equipment.

[0188] Specifically, the display screen 8 uses OLED. After the sensor 2 collects data and processes it through the algorithm in the control chip U1, the final XY axis angle signal can be displayed in real time on the 1.3-inch OLED. At the same time, the OLED displays the power information of the lithium battery in real time.

[0189] Specifically, a high-resolution OLED display 8 is introduced to provide clear, easy-to-read angle readings with good contrast and viewing angle. It supports LoRa wireless communication to achieve wireless connection with mobile devices or computers, facilitating data transmission and remote monitoring, and integrates with the cloud platform to achieve real-time synchronization and storage of data, facilitating data management and analysis.

[0190] In a preferred embodiment, the communication circuit 4 includes an RS485 communication circuit 41 and a LoRa wireless communication circuit 42, the RS485 communication circuit 41 is connected to the control chip U1 through an RS485 interface, and an isolation chip U4 and an electrostatic protection circuit are provided on the RS485 interface;

[0191] The RS485 communication circuit 41 includes:

[0192] Isolation chip U4, connected to control chip U1;

[0193] A converter chip U5, the converter chip U5 is connected to the isolation chip U4, and the converter chip U5 outputs a third power supply voltage V3 based on the second power supply voltage V2;

[0194] RS485 transceiver chip U6, connected to the isolation chip;

[0195] The LoRa wireless communication circuit 42 is provided with a LoRa chip U7, and the LoRa chip U7 is connected to the control chip.

[0196] Through the RS485 communication circuit 41 and the LoRa wireless communication circuit 42, real-time transmission and automatic recording of measurement data are realized, which is convenient for users to perform data analysis and remote monitoring, and improves work efficiency and accuracy of data management.

[0197] With the development trend of Industry 4.0 and intelligent manufacturing, intelligent and automated equipment are increasingly used in modern production and scientific research. This utility model promotes the development of angle measuring instruments towards intelligence by introducing intelligent sensors, microcontroller chip U1 and data processing algorithms, realizes automated measurement and intelligent analysis, further improves production efficiency and measurement accuracy, and meets the needs of modern industrial development.

[0198] In a preferred embodiment, the RS485 communication circuit 41 is connected to the control chip U1 via an RS485 interface, and an isolation chip U4 and an electrostatic protection circuit are provided on the RS485 interface.

[0199] Specifically, the RS485 communication circuit 41 is used to increase the data transmission distance, meet the communication distance requirements of several hundred meters, and even reach a distance of thousands of meters, and an electrostatic protection (ESD) circuit is added. In addition, the LoRa wireless communication circuit 42 can also be used to transmit data, which can be up to tens of kilometers of wireless data transmission.

[0200] Many high-precision angle measuring instruments often require professional operation due to their complex structure and cumbersome operation, which to a certain extent limits their application in on-site rapid measurement. The angle measuring instrument of the present application integrates the control chip U1 and the sensor 2, without the need for external complex accessories or equipment. The sensor 2 adopts an acceleration sensor chip based on 3D-MEMS, which makes the measuring instrument have high precision and reliability. The utility model realizes the communication function through the RS485 communication circuit 41 and the LoRa wireless communication circuit 42, so that the measuring instrument can easily transmit and communicate data with the external terminal, which is convenient for users to obtain and process measurement data; the humanized design and simplified operation process make the measuring instrument easier to use. Even non-professionals can easily complete angle measurement, thereby improving work efficiency and expanding the application range of the instrument.

[0201] Specifically, the angle signal can also be transmitted to customers via RS485 or LoRa wirelessly. LoRa technology can achieve long-distance transmission of tens of kilometers. The RS485 interface uses the ISOW7841DWE isolation chip U4 to isolate data communication, and the SRV05 chip is used to prevent static electricity from interfering with circuits and communications, achieving reliability and stability in data transmission.

[0202] In a preferred embodiment, the RS485 communication circuit 41 includes:

[0203] The isolation chip U4, the first receiving pin U4_3 of the isolation chip U4 is connected to the first sending pin U1_30 of the control chip U1, the first sending pin U4_6 of the isolation chip U4 is connected to the first receiving pin U1_31 of the control chip U1, and the first power pin U4_1 of the isolation chip U4 is connected to the second power supply voltage V2;

[0204] A fourth capacitor C4, wherein a first end of the fourth capacitor C4 is connected to a first power pin U4_1 of the isolation chip U4, and a second end of the fourth capacitor C4 is connected to a first ground pin U4_2 of the isolation chip U4 and then grounded;

[0205] A fifth capacitor C5, wherein a first end of the fifth capacitor C5 is connected to a second power pin U4_16 of the isolation chip U4, and a second end of the fifth capacitor C5 is connected to a second ground pin U4_15 of the isolation chip U4 and then connected to a digital ground;

[0206] A first resistor R1, wherein a first end of the first resistor R1 is connected to a setting pin U4_10 of the isolation chip U4, and a second end of the first resistor R1 is connected to a third ground pin U4_9 of the isolation chip U4 and then to a digital ground;

[0207] The converter chip U5 has a positive input terminal U5_1 connected to a first power supply pin U4_1 of the isolation chip U4, a negative input terminal U5_2 of the converter chip U5 is grounded, a positive output terminal U5_6 of the converter chip U5 is connected to a second power supply pin U4_16 of the isolation chip U4 to output a third power supply voltage V3, and a negative output terminal U5_4 of the converter chip U5 is connected to a power ground;

[0208] A first transistor Q1, a base of the first transistor Q1 is connected to a second resistor R2 and then connected to a second sending pin U4_11 of the isolation chip U4, and an emitter of the first transistor Q1 is grounded;

[0209] a third resistor R3, wherein a first end of the third resistor R3 is connected to the base of the first transistor Q1, and a second end of the third resistor R3 is connected to the emitter of the first transistor Q1;

[0210] a fourth resistor R4, wherein a first end of the fourth resistor R4 is connected to the collector of the first transistor Q1, and a second end of the fourth resistor R4 is connected to the third power supply voltage V3;

[0211] RS485 transceiver chip U6, a receiving pin U6_1 of the RS485 transceiver chip U6 is connected to a fifth resistor R5 and then to the second end of the fourth resistor R4, an enable control pin of the RS485 transceiver chip U6 is connected to the collector of the first transistor Q1, a drive input pin U6_4 of the RS485 transceiver chip U6 is connected to a sixth resistor R6 and then to ground, a ground pin of the RS485 transceiver chip U6 is connected to a power ground, and a power pin U6_8 of the RS485 transceiver chip U6 is connected to a third power supply voltage V3;

[0212] A sixth capacitor C6, a first end of the sixth capacitor C6 is connected to a power pin U6_8 of the RS485 transceiver chip U6, and a second end of the sixth capacitor C6 is connected to a power ground;

[0213] A seventh resistor R7, wherein a first end of the seventh resistor R7 is connected to a second end of the sixth capacitor C6, and a second end of the seventh resistor R7 is connected to a first transmission pin U6_7 of the RS485 transceiver chip U6;

[0214] An eighth resistor R8, a first end of the eighth resistor R8 is connected to the second transmission pin U6_6 of the RS485 transceiver chip U6, and a second end of the eighth resistor R8 is connected to the third power supply voltage V3;

[0215] a ninth resistor R9, wherein a first end of the ninth resistor R9 is connected to a second end of the seventh resistor R7, and a second end of the ninth resistor R9 is connected to a first end of the eighth resistor R8;

[0216] TVS diode TVS1, the first transmission pin of TVS diode TVS1 is connected to the first transmission pin U6_7 of RS485 transceiver chip U6, the second transmission pin of TVS diode TVS1 is connected to the second transmission pin U6_6 of RS485 transceiver chip U6, and the ground pin of TVS diode TVS1 is connected to the power ground.

[0217] Specifically, the isolation chip U4 adopts the ISOW7841DWE model chip, and the ground pins of the isolation chip U4 adopt the second pin U4_2, the eighth pin U4_8, the ninth pin U4_9 and the fifteenth pin U4_15 of the ISOW7841DWE chip, among which the second pin U4_2 and the eighth pin U4_8 of the ISOW7841DWE chip are grounded, and the ninth pin U4_9 and the fifteenth pin U4_15 of the ISOW7841DWE chip are connected to the digital ground.

[0218] Specifically, the fourth capacitor C4 is a capacitor with a specification of 0.1uF / 25V, the fifth capacitor C5 is a capacitor with a specification of 0.1uF / 25V, and the first resistor R1 is a 0 ohm resistor.

[0219] Specifically, the converter chip U5 uses a DC-DC converter chip U5 of model B0303-1W, which is used to convert the second power supply voltage V2 into the third power supply voltage V3 while maintaining isolation.

[0220] The resistance value of the second resistor R2 is 1K ohm, the resistance value of the third resistor R3 is 10K ohm, the resistance value of the fourth resistor R4 is 10K ohm, the resistance value of the fifth resistor R5 is 10K ohm, and the resistance value of the sixth resistor R6 is 10K ohm.

[0221] The first transistor Q1 adopts an NPN high-frequency low-power transistor of the MMBT3904 model.

[0222] The RS485 transceiver chip U6 adopts the low-power RS485 transceiver chip U6 of the SIT3088ETK model. The enable control pin of the RS485 transceiver chip U6 adopts the third pin U6_3 and the fourth pin U6_4 of the SIT3088ETK; the ground pin of the RS485 transceiver chip U6 adopts the fifth pin U6_5 and the ninth pin U6_9 of the SIT3088ETK chip, among which the ninth pin U6_9 of the SIT3088ETK chip is its extension pin.

[0223] The sixth capacitor C6 is a 0.1uF / 25V capacitor.

[0224] The resistance value of the seventh resistor R7 is 10K ohms, the resistance value of the eighth resistor R8 is 10K ohms, and the resistance value of the ninth resistor R9 is 20K ohms.

[0225] TVS diode TVS1 uses CDSOT23-SM712 TVS diode TVS1, which is a three-pin package and is used for voltage transient suppression.

[0226] In a preferred embodiment, the LoRa wireless communication circuit 42 includes:

[0227] LoRa chip U7, the reset pin U7_1 of LoRa chip U7 is connected to the first reset control pin U1_14 of control chip U1, the sending pin U7_23 of LoRa chip U7 is connected to the tenth resistor R10 and then connected to the second receiving pin U1_13 of control chip U1, the receiving pin U7_22 of LoRa chip U7 is connected to the eleventh resistor R11 and then connected to the second sending pin U1_12 of control chip U1, the first function mode pin U7_21 of LoRa chip U7 is connected to the twelfth resistor R12 is connected to the first mode control pin U1_32 of the control chip U1, the second function mode pin U7_20 of the LoRa chip U7 is connected to a thirteenth resistor R13 and then connected to the second mode control pin U1_33 of the control chip U1, the auxiliary pin U7_24 of the LoRa chip U7 is connected to a fourteenth resistor R14 and then connected to the auxiliary control pin U1_29 of the control chip U1, the ground pin of the LoRa chip U7 is grounded, and the power pin U7_25 of the LoRa chip U7 is connected to the second supply voltage V2;

[0228] A seventh capacitor C7, a first end of the seventh capacitor C7 is connected to one of the ground pins of the LoRa chip U7, and a second end of the seventh capacitor C7 is connected to a power pin U7_25 of the LoRa chip U7;

[0229] An eighth capacitor C8, a first end of the eighth capacitor C8 is connected to a reset pin U7_1 of the LoRa chip U7, and a second end of the eighth capacitor C8 is grounded;

[0230] A fifteenth resistor R15, a first end of the fifteenth resistor R15 is connected to a reset pin U7_1 of the LoRa chip U7, and a second end of the fifteenth resistor R15 is connected to a second power supply voltage V2;

[0231] A sixteenth resistor R16, a first end of the sixteenth resistor R16 is connected to the second power supply voltage V2, and a second end of the sixteenth resistor R16 is connected to the sending pin U7_23 of the LoRa chip U7;

[0232] A seventeenth resistor R17, a first end of the seventeenth resistor R17 is connected to a first end of the sixteenth resistor R16, and a second end of the seventeenth resistor R17 is connected to a receiving pin U7_22 of the LoRa chip U7;

[0233] An eighteenth resistor R18, a first end of the eighteenth resistor R18 is connected to the first function mode pin U7_21 of the LoRa chip U7, and a second end of the eighteenth resistor R18 is grounded;

[0234] The nineteenth resistor R19, the first end of the nineteenth resistor R19 is connected to the second functional mode pin U7_20 of the LoRa chip U7, and the second end of the nineteenth resistor R19 is connected to the second end of the eighteenth resistor R18.

[0235] Specifically, the LoRa chip U7 adopts the E22-400T22S chip. The first functional mode pin U7_21 of the LoRa chip U7 and the second functional mode pin U7_20 of the LoRa chip U7 perform high and low level combinations to determine the working mode of the LoRa chip U7. The two mode control pins of the control chip U1 are used to switch the control mode. Generally speaking, the mode switching is only effective when the auxiliary pin U7_24 of the LoRa chip U7 outputs 1, otherwise the switching will be delayed.

[0236] The ground pins of the LoRa chip U7 use the second pin U7_2, the eighth pin U7_8, the eleventh pin U7_11, the thirteenth pin U7_13, the fourteenth pin U7_14, the fifteenth pin U7_15, the sixteenth pin U7_16, the nineteenth pin U7_19, and the twenty-sixth pin U7_26 of the E22-400T22S chip.

[0237] The seventh capacitor C7 is a capacitor with a specification of 0.1uF / 25V, and the eighth capacitor C8 is a capacitor with a specification of 10uF / 25V.

[0238] A first end of the sixth capacitor C6 is connected to the twenty-sixth pin U7_26 of the LoRa chip U7, and a second end of the sixth capacitor C6 is connected to the power pin U7_25 of the LoRa chip U7.

[0239] The eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14 are all 0 ohm resistors; the resistance value of the fifteenth resistor R15 is 10K ohms, the resistance value of the sixteenth resistor R16 is 10K ohms, the resistance value of the seventeenth resistor R17 is 10K ohms, the resistance value of the eighteenth resistor R18 is 10K ohms, and the resistance value of the nineteenth resistor R19 is 10K ohms.

[0240] In a preferred embodiment, the level conversion circuit 3 includes a level conversion chip U2, a first level receiving pin of the level conversion chip U2 is connected to a first level output pin of the control chip U1, a first transmission end pin of the level conversion chip U2 is connected to a first serial transmission pin of the control chip U1, a first logic pin of the level conversion chip U2 is connected to a level conversion control pin U1_46 of the control chip U1, a second logic pin of the level conversion chip U2 is grounded, a first power pin of the level conversion chip U2 is connected to a first power supply voltage V1, a second power pin of the level conversion chip U2 is connected to a second power supply voltage V2, and a ground pin of the level conversion chip U2 is grounded;

[0241] The level conversion circuit 3 also includes,

[0242] A first capacitor C1, wherein a first end of the first capacitor C1 is connected to a first power pin of the level conversion chip U2, and a second end of the first capacitor C1 is connected to a second logic pin of the level conversion chip U2;

[0243] A second capacitor C2, a first end of the second capacitor C2 is connected to a second power pin of the level conversion chip U2, and a second end of the second capacitor C2 is grounded;

[0244] A sensing chip U3, wherein a transmission end pin of the sensing chip U3 is connected to a second transmission end pin of the level conversion chip U2, an output pin of the sensing chip U3 is connected to a first receiving pin of the level conversion chip U2, a power pin of the sensing chip U3 is connected to a first power supply voltage V1, and a ground pin of the sensing chip U3 is grounded;

[0245] The sensor 2 further includes a third capacitor C3 , a first end of the third capacitor C3 is connected to a power pin of the sensor chip U3 , and a second end of the third capacitor C3 is grounded.

[0246] The control chip U1 adopts the STM32F103C8T6 chip, and the first serial transmission pin of the control chip U1 adopts four I / O ports of the STM32F103C8T6 chip. The utility model is the twenty-fifth pin U1_25, the twenty-sixth pin U1_26, the twenty-seventh pin U1_27 and the twenty-eighth pin U1_28 of the STM32F103C8T6 chip. The twenty-fifth pin U1_25 of the control chip U1 is the pin (SPI SS) for selecting the slave device. When the SPI SS is pulled low, it indicates that the corresponding slave device is selected for communication. The twenty-sixth pin U1_26 is the clock signal pin (SPI CLK) of the SPI, which is used to synchronize the data transmission between the master device and the slave device. The twenty-seventh pin U1_27 is the data line (SPI MISO) from the slave device to the master device. In SPI communication, the slave device sends data to the master device through the SPI MISO pin. The master device receives the data sent by the slave device through the SPI MOSI. The twenty-eighth pin U1_28 is the data line (SPI MOSI) from the master device to the slave device. In SPI communication, the master device sends data to the slave device through the SPI MOSI pin. The slave device receives the data sent by the master device through the SPI MISO. The level conversion chip U2 uses the SN74LVC4245 chip, and the first transmission end pin of the level conversion chip U2 uses the 18th pin U2_18, the 19th pin U2_19, the 20th pin U2_20 and the 21st pin U2_21 of the SN74LVC4245 chip.

[0247] The first level receiving pin of the level conversion chip U2 is connected to the first level output pin of the control chip U1, wherein the first level output pin of the control chip U1 respectively adopts the 42nd pin U1_42 and the 43rd pin U1_43 of the STM32F103C8T6 chip to output a 5V voltage, and the first level receiving pin of the level conversion chip U2 adopts the 17th pin U2_17 and the 16th pin U2_16 of the SN74LVC4245 chip to receive the 5V voltage.

[0248] The first logic pin of the level conversion chip U2 uses the second pin U2_2 of the SN74LVC4245 chip, that is, the DIR pin, and the second logic pin of the level conversion chip U2 uses the twenty-second pin U2_22 of the SN74LVC4245 chip, that is, the OE non-pin. The logic is:

[0249] When OE and DIR are both low, the signal transmission direction is from the control chip U1 to the sensor 2;

[0250] When OE is not low and DIR is high, the signal transmission direction is from sensor 2 to control chip U1;

[0251] When OE is not high and DIR is empty, the SN74LVC4245 chip is in isolation state.

[0252] The first power pin of the level conversion chip U2 adopts the twenty-fourth pin U2_24 and the twenty-third pin U2_23 of the SN74LVC4245 chip, and the second power pin of the level conversion chip U2 adopts the first pin U2_1 of the SN74LVC4245 chip.

[0253] The ground pins of the level conversion chip U2 use the eleventh pin U2_11, the twelfth pin U2_12 and the thirteenth pin U2_13 of the SN74LVC4245 chip.

[0254] Specifically, the first capacitor C1 is a capacitor with a specification of 0.1uF / 16V, and the second capacitor C2 is a capacitor with a specification of 0.1uF / 16V.

[0255] Specifically, the sensing chip U3 adopts the SCA100T-D02 chip based on 3D-MEMS technology, and the transmission end pins of the sensing chip U3 adopt the first pin U3_1, the third pin U3_3, the fourth pin U3_4 and the seventh pin U3_7 of the SCA100T-D02 chip, wherein the first pin U3_1 of the SCA100T-D02 chip is a clock input pin, which is used for the clock signal in serial communication, the third pin U3_3 is the master device input and slave device output pin of the sensor 2, which is used for the sensing chip U3 to send data to the level conversion chip U2 in SPI communication, the fourth pin U3_4 is the master device output and slave device input pin, which is used for the level conversion chip U2 to send data to the sensing chip U3 in SPI communication, and the seventh pin U3_7 is a chip select pin, which, when pulled low, indicates that the sensing chip U3 is selected for data transmission.

[0256] The second transmission end pins of the level conversion chip U2 adopt the third pin U2_3, the fourth pin U2_4, the fifth pin U2_5 and the sixth pin U2_6 of the SN74LVC4245 chip.

[0257] The output pins of the sensing chip U3 use the fifth pin U3_5 and the eleventh pin U3_11 of the SCA100T-D02 chip to output the angle signal measured by the sensing chip U3. The first receiving pin of the level conversion chip U2 uses the eighth pin U2_8 and the seventh pin U2_7 of the SN74LVC4245 chip, wherein the fifth pin U3_5 of the SCA100T-D02 chip is connected to the eighth pin U2_8 of the SN74LVC4245 chip, and the eleventh pin U3_11 of the SCA100T-D02 chip is connected to the seventh pin U2_7 of the SN74LVC4245 chip.

[0258] The power pin of the sensing chip U3 uses the twelfth pin U3_12 of the SCA100T-D02 chip, and the ground pin of the sensing chip U3 uses the sixth pin U3_6 of the SCA100T-D02 chip.

[0259] The third capacitor C3 is a 0.1uF / 16V capacitor.

[0260] Specifically, the sensor uses the SCA100T-D02 chip based on 3D-MEMS technology, the sensor 2 is connected to the control chip U1 through the SPI interface, and the level conversion circuit 3 is connected to the SPI interface. The measurement axes of the two sensing elements inside the sensor 2 are parallel to the installation plane and orthogonal to each other, with low temperature drift, high resolution, low noise and robust design, which solves the problem that other sensors cannot accurately identify in the environment and improves the anti-interference ability.

[0261] By optimizing the specific Kalman recognition algorithm, the sensitivity and accuracy are improved, with a resolution of up to 0.001°. A simple and highly integrated hardware system is used to reduce the size and cost, which is also conducive to reducing the installation cost of the equipment. The system's responsiveness, reliability and stability are improved by optimizing the logic control algorithm of the control chip U1.

[0262] In a preferred embodiment, the battery management circuit 5 includes:

[0263] The battery management chip U8, the temperature monitoring pin U8_10 of the battery management chip U8 is connected to the thermistor voltage TS, and the analog ground pin U8_25 of the battery management chip U8 is grounded;

[0264] A first diode D1, wherein an anode of the first diode D1 is connected to a charging voltage Vbat;

[0265] a second diode D2, wherein an anode of the second diode D2 is connected to an input voltage VIN, and a cathode of the second diode D2 is connected to a cathode of the first diode D1;

[0266] A twentieth resistor R20, a first end of the twentieth resistor R20 is connected to the cathode of the second diode D2, and a second end of the twentieth resistor R20 is connected to the first power pin U8_4 of the battery management chip U8;

[0267] a ninth capacitor C9, wherein a first end of the ninth capacitor C9 is connected to a second end of the twentieth resistor R20, and a second end of the ninth capacitor C9 is grounded;

[0268] A twenty-first resistor R21, a first end of the twenty-first resistor R21 is connected to the input voltage;

[0269] a tenth capacitor C10, wherein a first end of the tenth capacitor C10 is connected to a second end of the twenty-first resistor R21, and a second end of the tenth capacitor C10 is grounded;

[0270] A first MOS tube M1, wherein a drain of the first MOS tube M1 is connected to an input voltage;

[0271] A twenty-second resistor R22, wherein a first end of the twenty-second resistor R22 is connected to the gate of the first MOS transistor M1, and a second end of the twenty-second resistor R22 is connected to a first driving pin U8_8 of the battery management chip U8;

[0272] A twenty-third resistor R23, a first end of the twenty-third resistor R23 is connected to the source of the first MOS tube M1, and a second end of the twenty-third resistor R23 is connected to the current detection pin U8_7 of the battery management chip U8;

[0273] A second MOS tube M2, wherein the source of the second MOS tube M2 is connected to the source of the first MOS tube M1, the gate of the second MOS tube M2 is connected to the first end of the twenty-second resistor R22, and the drain of the second MOS tube M2 is connected to the first positive input pin U8_6 of the battery management chip U8;

[0274] A twenty-fourth resistor R24, a first end of the twenty-fourth resistor R24 ​​is connected to the drain of the second MOS tube M2, a second end of the twenty-fourth resistor R24 ​​is connected to the second power pin U8_2U8_2, the third power pin U8_3 and the first negative input pin U8_5 of the battery management chip U8, and a power supply voltage V0 is output from the second end of the twenty-fourth resistor R24;

[0275] an eleventh capacitor C11, a first end of the eleventh capacitor C11 is connected to a first end of the twenty-fourth resistor R24, and a second end of the eleventh capacitor C11 is connected to a second end of the twenty-fourth resistor R24;

[0276] A twelfth capacitor C12, a first end of the twelfth capacitor C12 is connected to a second power pin U8_2 of the battery management chip U8, and a second end of the twelfth capacitor C12 is grounded;

[0277] A twenty-fifth resistor R25, a first end of the twenty-fifth resistor R25 is connected to a reference voltage VREF;

[0278] Indicator light LED1, the positive electrode of the indicator light LED1 is connected to the first end of the twenty-fifth resistor R25, and the negative electrode of the indicator light LED1 is connected to the status indication pin U8_9 of the battery management chip U8;

[0279] A twenty-sixth resistor R26, wherein a first end of the twenty-sixth resistor R26 is connected to a first end of the twenty-fifth resistor R25, and a second end of the twenty-sixth resistor R26 is connected to a temperature monitoring pin U8_10 of the battery management chip U8;

[0280] A twenty-seventh resistor R27, a first end of the twenty-seventh resistor R27 is connected to the second end of the twenty-sixth resistor R26, and a second end of the twenty-seventh resistor R27 is grounded;

[0281] A thirteenth capacitor C13, a first end of the thirteenth capacitor C13 is connected to the termination control pin U8_11 of the battery management chip U8, and a first end of the thirteenth capacitor C13 is grounded;

[0282] A fourteenth capacitor C14, a first end of the fourteenth capacitor C14 is connected to the first switch pin U8_1 and the second switch pin U8_24 of the battery management chip U8, and a second end of the fourteenth capacitor C14 is connected to the temperature compensation pin U8_21 of the battery management chip U8;

[0283] a third diode D3, wherein a cathode of the third diode D3 is connected to a first end of the fourteenth capacitor C14, and an anode of the third diode D3 is grounded;

[0284] A first inductor L1, wherein a first end of the first inductor L1 is connected to a cathode of a third diode D3, and a second end of the first inductor L1 is connected to a second positive input pin U8_16 of a battery management chip U8;

[0285] A twenty-eighth resistor R28, wherein a first end of the twenty-eighth resistor R28 is connected to the second end of the first inductor L1, a second end of the twenty-eighth resistor R28 is connected to the second negative input pin U8_15 of the battery management chip U8, and a charging voltage Vbat is output from the second end of the twenty-eighth resistor R28;

[0286] a fifteenth capacitor C15, wherein a first end of the fifteenth capacitor C15 is connected to a first end of a twenty-eighth resistor R28, and a second end of the fifteenth capacitor C15 is connected to a second end of the twenty-eighth resistor R28;

[0287] A sixteenth capacitor C16, a first end of the sixteenth capacitor C16 is connected to the second end of the twenty-eighth resistor R28, and a second end of the sixteenth capacitor C16 is grounded;

[0288] A seventeenth capacitor C17, a first end of the seventeenth capacitor C17 is connected to the second end of the twenty-eighth resistor R28, and a second end of the seventeenth capacitor C17 is grounded;

[0289] a third MOS tube M3, wherein a drain of the third MOS tube M3 is connected to the second end of the twenty-eighth resistor R28, and a source of the third MOS tube M3 is connected to the power supply voltage V0;

[0290] an eighteenth capacitor C18, a first end of the eighteenth capacitor C18 is connected to the second end of the eleventh capacitor C11, and a second end of the eighteenth capacitor C18 is grounded;

[0291] A nineteenth capacitor C19, wherein a first end of the nineteenth capacitor C19 is connected to an output voltage pin U8_20 of the battery management chip U8, and a second end of the nineteenth capacitor C19 is connected to a first power ground pin U8_22 and a second power ground pin U8_23 of the battery management chip U8 and then grounded;

[0292] a twenty-ninth resistor R29, wherein a first end of the twenty-ninth resistor R29 is connected to a second driving pin of the battery management chip U8, and a second end of the twenty-ninth resistor R29 is connected to a gate of the third MOS tube M3;

[0293] A twentieth capacitor C20, a first end of the twentieth capacitor C20 is connected to the second end of the first inductor L1, and a second end of the twentieth capacitor C20 is grounded;

[0294] a 30th resistor R30, wherein a first end of the 30th resistor R30 is connected to a first setting pin U8_17 of the battery management chip U8, and a second end of the 30th resistor R30 is connected to a reference voltage VREF;

[0295] A thirty-first resistor R31, a first end of the thirty-first resistor R31 is connected to the second end of the thirtieth resistor R30, and a second end of the thirty-first resistor R31 is grounded;

[0296] A thirty-second resistor R32, a first end of the thirty-second resistor R32 is connected to the battery voltage, and a second end of the thirty-second resistor R32 is connected to the protection pin U8_18 of the battery management chip U8;

[0297] A thirty-third resistor R33, a first end of the thirty-third resistor R33 is connected to the second end of the thirty-second resistor R32, and a second end of the thirty-third resistor R33 is grounded;

[0298] A thirty-fourth resistor R34, a first end of the thirty-fourth resistor R34 is connected to the drain of the third MOS tube M3, and a second end of the thirty-fourth resistor R34 is connected to the feedback pin U8_14 of the battery management chip U8;

[0299] A thirty-fifth resistor R35, a first end of the thirty-fifth resistor R35 is connected to the second end of the thirty-fourth resistor R34, and a second end of the thirty-fifth resistor R35 is grounded;

[0300] A thirty-sixth resistor R36, wherein a first end of the thirty-sixth resistor R36 is connected to a fourth power pin U8_12 of the battery management chip U8 and then to a reference voltage VREF, and a second end of the thirty-sixth resistor R36 is connected to a second setting pin U8_13 of the battery management chip U8;

[0301] A thirty-seventh resistor R37, a first end of the thirty-seventh resistor R37 is connected to the second end of the thirty-sixth resistor R36, and a second end of the thirty-seventh resistor R37 is grounded;

[0302] A twenty-first capacitor C21, a first end of the twenty-first capacitor C21 is connected to the first end of the thirty-sixth resistor R36, and a second end of the twenty-first capacitor C21 is grounded.

[0303] Specifically, the battery management chip U8 adopts the BQ24172RGYR chip model for battery management and charging control.

[0304] The first diode D1 and the second diode D2 are SS34 type diodes, the resistance of the twentieth resistor R20 is 10 ohms, the resistance of the twenty-first resistor R21 is 2 ohms, the capacitance of the ninth capacitor C9 is 1uF, and the capacitance of the tenth capacitor C10 is 2.2uF.

[0305] The first MOS tube M1 and the second MOS tube M2 are FQD13N10TM MOS tubes, the resistance of the twenty-second resistor R22 is 4.02K ohms, the resistance of the twenty-third resistor R23 is 4.02K ohms, the resistance of the twenty-fourth resistor R24 ​​is 10M ohms, the capacitance of the eleventh capacitor C11 is 0.1uF, the capacitance of the eighteenth capacitor C18 is 0.1uF, the capacitance of the twelfth capacitor C12 is 10uF, the resistance of the twenty-fifth resistor R25 is 1.5K ohms, the resistance of the twenty-sixth resistor R26 is 5.23K ohms, the resistance of the twenty-seventh resistor R27 is 30.1K ohms, the indicator light LED1 is an LED lamp, and the capacitance of the thirteenth capacitor C13 is 1uF.

[0306] Specifically, the capacitance of the fourteenth capacitor C14 is 0.0047uF, the third diode D3 adopts the SS34 model diode, the resistance of the twenty-eighth resistor R28 is 10M ohms, the resistance of the twenty-ninth resistor R29 is 1K ohms, the resistance of the thirtieth resistor R30 is 100K ohms, the resistance of the thirty-first resistor R31 is 32.4K ohms, the resistance of the thirty-second resistor R32 is 499K ohms, the resistance of the thirty-third resistor R33 is 49.9K ohms, the resistance of the thirty-fourth resistor R34 is 499K ohms, and the resistance of the thirty-fifth resistor R35 is 100K ohms. The resistance of the thirty-sixth resistor R36 is 100K ohms, the resistance of the thirty-seventh resistor R37 is 32.4K ohms, the third MOS tube M3 adopts the MOS tube model of FQD13N10TM, the capacitance of the fifteenth capacitor C15 is 0.1uF, the capacitance of the sixteenth capacitor C16 is 22uF, the capacitance of the seventeenth capacitor C17 is 10uF, the capacitance of the nineteenth capacitor C19 is 1uF, the capacitance of the twentieth capacitor C20 is 0.1uF, the capacitance of the twenty-first capacitor C21 is 1uF, and the first inductor L1 adopts the inductor model of MWSC0630H2R2MT.

[0307] Specifically, the fourth diode D4 and the fifth diode D5 use B340A model diodes, the buck-boost chip U9 uses SX1308 model chip, the first supply voltage V1 in the utility model is 5V, the second supply voltage V2 is 3.3V, the power ground V_GND is 3.3V power ground, the twenty-second capacitor C22 uses a 22uF / 25V capacitor, the twenty-third capacitor C23 uses a 0.1uF / 25V capacitor, the twenty-fourth capacitor C24 uses a 10uF / 50V capacitor, the twenty-fifth capacitor C25 uses a 0.1uF / 25V capacitor, the twenty-sixth capacitor C26 uses a 22uF / 25V capacitor, the twenty-seventh capacitor C27 uses a 22uF / 25V capacitor, and the twenty-eighth capacitor C28 uses a 10uF / 25V capacitor.

[0308] The second inductor L2 and the third inductor L3 use SWPA4030S330MT model inductors, both of which have an inductance of 33uH, and the voltage regulator chip U10 uses the AMS1117-3V3 model chip.

[0309] In a preferred embodiment, the switch control circuit 6 includes:

[0310] The switch control chip U11, the power pin U11_6 of the switch control chip U11 is connected to the power supply voltage V0, the interrupt output pin U11_8 of the switch control chip U11 is connected to the interrupt control pin U1_22 of the control chip U1, and the enable output pin U11_2 of the switch control chip U11 is connected to a forty-fourth resistor R44 and then connected to the drive control pin U1_21 of the control chip U1;

[0311] A forty-second resistor R42, wherein a first end of the forty-second resistor R42 is connected to a power pin U11_6 of the switch control chip U11, and a second end of the forty-second resistor R42 is connected to a monitoring input pin U11_1 of the switch control chip U11;

[0312] a forty-third resistor R43, wherein a first end of the forty-third resistor R43 is connected to a second end of the forty-second resistor R42, and a second end of the forty-third resistor R43 is grounded;

[0313] A twenty-ninth capacitor C29, a first end of the twenty-ninth capacitor C29 is connected to the first end of the forty-second resistor R42, and a second end of the twenty-ninth capacitor C29 is grounded;

[0314] A 30th capacitor C30, a first end of the 30th capacitor C30 is connected to the timer pin U11_3 of the switch control chip U11, and a second end of the 30th capacitor C30 is grounded;

[0315] A fourth MOS tube M4, a drain of the fourth MOS tube M4 is connected to the first end of the twenty-ninth capacitor C29, a gate of the fourth MOS tube M4 is connected to the enable pin U11_7 of the switch control chip U11, and a source of the fourth MOS tube M4 generates a switch control signal TURN;

[0316] a forty-fifth resistor R45, wherein a first end of the forty-fifth resistor R45 is connected to the gate of the fourth MOS transistor M4, and a second end of the forty-fifth resistor R45 is connected to a ground pin U11_4 of the switch control chip U11 and then grounded;

[0317] a forty-sixth resistor R46, wherein a first end of the forty-sixth resistor R46 is connected to the second power supply voltage V2, and a second end of the forty-sixth resistor R46 is connected to the enable output pin U11_2 of the switch control chip U11;

[0318] a forty-seventh resistor R47, wherein a first end of the forty-seventh resistor R47 is connected to the second power supply voltage V2, and a second end of the forty-seventh resistor R47 is connected to the interrupt output pin U11_8 of the switch control chip U11;

[0319] A first connector J1, wherein a first pin J1_1 of the first connector J1 is grounded, a second pin J1_2 of the first connector J1 is connected to a holding pin U1_41 of the control chip U1, a third pin J1_3 of the first connector J1 is connected to a second reset control pin U1_10 of the control chip U1, and a fourth pin J1_4 of the first connector J1 is connected to a button input pin U11_5 of the switch control chip U11 to receive a system switch signal SYS;

[0320] A first protection diode ESD1, wherein a first end of the first protection diode ESD1 is connected to a fourth pin J1_4 of the first connector J1, and a second end of the first protection diode ESD1 is connected to a first pin J1_1 of the first connector J1;

[0321] A thirty-first capacitor C31, a first end of the thirty-first capacitor C31 is connected to the first end of the first protection diode ESD1, and a second end of the thirty-first capacitor C31 is connected to the second end of the first protection diode ESD1;

[0322] A second protection diode ESD2, wherein a first end of the second protection diode ESD2 is connected to a third pin J1_3 of the first connector J1, and a second end of the first protection diode ESD1 is connected to a first pin J1_1 of the first connector J1;

[0323] A thirty-second capacitor C32, wherein a first end of the thirty-second capacitor C32 is connected to a first end of the second protection diode ESD2, and a second end of the thirty-second capacitor C32 is connected to a second end of the second protection diode ESD2;

[0324] A third protection diode ESD3, a first end of the third protection diode ESD3 is connected to the second pin J1_2 of the first connector J1, and a second end of the third protection diode ESD3 is connected to the first pin J1_1 of the first connector J1;

[0325] A thirty-third capacitor C33, a first end of the thirty-third capacitor C33 is connected to the first end of the third protection diode ESD3, and a second end of the thirty-third capacitor C33 is connected to the second end of the third protection diode ESD3;

[0326] a forty-eighth resistor R48, wherein a first end of the forty-eighth resistor R48 is connected to the second power supply voltage V2, and a second end of the forty-eighth resistor R48 is connected to a first end of a thirty-first capacitor C31;

[0327] a forty-ninth resistor R49, wherein a first end of the forty-ninth resistor R49 is connected to a first end of the forty-eighth resistor R48, and a second end of the forty-ninth resistor R49 is connected to a first end of the thirty-second capacitor C32;

[0328] The fiftieth resistor R50, a first end of the fiftieth resistor R50 is connected to the first end of the forty-eighth resistor R48, and a second end of the fiftieth resistor R50 is connected to the first end of the thirty-third capacitor C33.

[0329] Specifically, the switch control chip U11 adopts the LTC2955ITS8 model chip, the resistance of the forty-second resistor R42 is 0 ohm, the resistance of the forty-third resistor R43 is 100K ohms, the twenty-ninth capacitor C29 adopts a capacitor with a specification of 0.1uF / 25V, the thirtieth capacitor C30 adopts a capacitor with a specification of 0.33uF / 25V, and the charging and discharging time constant of the thirtieth capacitor C30 is 5.2S / uF.

[0330] The fourth MOS tube M4 is a SI2318 MOS tube, the forty-fourth resistor R44 has a resistance of 0 ohm, the forty-fifth resistor R45 has a resistance of 10K ohm, the forty-sixth resistor R46 has a resistance of 100K ohm, and the forty-seventh resistor R47 has a resistance of 100K ohm.

[0331] The first connector J1 uses a FPCL0-4P model connector, the first protection diode ESD1, the second protection diode ESD2 and the third protection diode ESD3 are all ESD diodes, the thirty-first capacitor C31, the thirty-second capacitor C32 and the thirty-third capacitor C33 all use 1uF / 25V capacitors, the forty-eighth resistor R48, the forty-ninth resistor R49 and the fiftieth resistor R50 have resistance values ​​of 100K ohms.

[0332] The switch control circuit 6 is provided with a switch control chip U11 for controlling the on and off of the battery management circuit 5. Specifically, the switch control circuit 6 uses the LTC2955 switch control chip U11 to control the on and off of the power system, which can be turned on by a short press and turned off by a long press for 2 seconds.

[0333] In a preferred embodiment, it also includes:

[0334] A fourth inductor L4, a first end of the fourth inductor L4 is connected to the second power supply voltage V2, a second end of the fourth inductor L4 is connected to an analog power pin U1_9 of the control chip U1, and a power pin of the control chip U1 is connected to the second power supply voltage V2;

[0335] A fifth inductor L5, wherein a first end of the fifth inductor L5 is connected to an analog ground pin U1_8 of the control chip U1, and a second end of the fifth inductor L5 is connected to a ground pin of the control chip U1 and then grounded;

[0336] A thirty-seventh capacitor C37, a first end of the thirty-seventh capacitor C37 is connected to an analog power pin U1_9 of the control chip U1, and a second end of the thirty-seventh capacitor C37 is connected to an analog ground pin U1_8 of the control chip U1;

[0337] Crystal oscillator X1, a first crystal pin of the crystal oscillator X1 is connected to a first crystal oscillator pin U1_5 of the control chip U1, a second crystal pin of the crystal oscillator X1 is connected to a second crystal oscillator pin U1_6 of the control chip U1, and a ground pin of the crystal oscillator X1 is grounded;

[0338] a fifty-third resistor R53, wherein a first end of the fifty-third resistor R53 is connected to a first crystal pin of the crystal oscillator X1, and a second end of the fifty-third resistor R53 is connected to a second crystal pin of the crystal oscillator X1;

[0339] a thirty-eighth capacitor C38, a first end of the thirty-eighth capacitor C38 is connected to the first crystal pin of the crystal oscillator X1, and a second end of the thirty-eighth capacitor C38 is connected to the ground pin of the crystal oscillator X1;

[0340] A thirty-ninth capacitor C39, a first end of the thirty-ninth capacitor C39 is connected to the second crystal pin of the crystal oscillator X1, and a second end of the thirty-ninth capacitor C39 is connected to the ground pin of the crystal oscillator X1;

[0341] a fifty-fourth resistor R54, wherein a first end of the fifty-fourth resistor R54 is connected to an enable pin U1_44 of the control chip U1, and a second end of the fifty-fourth resistor R54 is grounded;

[0342] A third connector J3, wherein a first pin J3_1 of the third connector J3 is grounded, a second pin J3_2 of the third connector J3 is connected to a second clock signal pin U1_37 of the control chip U1, a third pin J3_3 of the third connector J3 is connected to a data transmission pin U1_34 of the control chip U1, and a fourth pin J3_4 of the third connector J3 is connected to a second power supply voltage V2;

[0343] a fortieth capacitor C40, wherein a first end of the fortieth capacitor C40 is connected to a fourth pin J3_4 of the third connector J3, and a second end of the fortieth capacitor C40 is grounded;

[0344] A fifty-fifth resistor R55, wherein a first end of the fifty-fifth resistor R55 is connected to the second power supply voltage V2, and a second end of the fifty-fifth resistor R55 is connected to a reset pin U1_7 of the control chip U1;

[0345] a forty-first capacitor C41, a first end of the forty-first capacitor C41 is connected to the second end of the fifty-fifth resistor R55, and a second end of the forty-first capacitor C41 is grounded;

[0346] a forty-fifth capacitor C45, wherein a first end of the forty-fifth capacitor C45 is connected to the second power supply voltage V2, and a second end of the forty-fifth capacitor C45 is grounded;

[0347] a forty-sixth capacitor C46, ​​wherein a first end of the forty-sixth capacitor C46 is connected to a first end of the forty-fifth capacitor C45, and a second end of the forty-sixth capacitor C46 is connected to a second end of the forty-fifth capacitor C45;

[0348] a forty-seventh capacitor C47, wherein a first end of the forty-seventh capacitor C47 is connected to a first end of the forty-fifth capacitor C45, and a second end of the forty-seventh capacitor C47 is connected to a second end of the forty-fifth capacitor C45;

[0349] Also includes an interface circuit, the interface circuit includes,

[0350] USB connector USB1, the first transmission pin of USB connector USB1 is connected to the second transmission pin U6_6 of RS485 transceiver chip U6, and the second transmission pin of USB connector USB1 is connected to the first transmission pin U6_7 of RS485 transceiver chip U6;

[0351] a forty-second capacitor C42, wherein a first end of the forty-second capacitor C42 is connected to a power pin of the USB connector USB1, and a second end of the forty-second capacitor C42 is grounded;

[0352] a forty-third capacitor C43, wherein a first end of the forty-third capacitor C43 is connected to a first end of the forty-second capacitor C42, and a second end of the forty-third capacitor C43 is connected to a second end of the forty-second capacitor C42;

[0353] a forty-fourth capacitor C44, wherein a first end of the forty-fourth capacitor C44 is connected to a first end of the forty-second capacitor C42, and a second end of the forty-fourth capacitor C44 is connected to a second end of the forty-second capacitor C42;

[0354] A fifth MOS tube M5, a drain of the fifth MOS tube M5 is connected to a power pin of the USB connector USB1, and a source of the fifth MOS tube M5 is connected to the battery management circuit 5;

[0355] a fifty-sixth resistor R56, wherein a first end of the fifty-sixth resistor R56 is connected to the gate of the fifth MOS transistor M5, and a second end of the fifty-sixth resistor R56 is grounded;

[0356] a fifty-seventh resistor R57, wherein a first end of the fifty-seventh resistor R57 is connected to the gate of the fifth MOS transistor M5, and a second end of the fifty-seventh resistor R57 is connected to the source of the fifth MOS transistor M5;

[0357] The fourth connector J4, the first pin J4_1 of the fourth connector J4 is connected to the source of the fifth MOS tube M5, and the second pin J4_2 of the fourth connector J4 is connected to the second end of the fifty-sixth resistor R56.

[0358] Specifically, the fourth inductor L4 and the fifth inductor L5 are PZ1608D691-R50TF inductors, and the thirty-seventh capacitor C37 is 0.1uF / 25V.

[0359] The control chip U1 adopts the STM32F103C8T6 chip, and the power pins of the control chip U1 adopt the first pin U1_1, the twenty-fourth pin U1_24, the thirty-sixth pin U1_36 and the forty-eighth pin U1_48 of the STM32F103C8T6; the ground pins of the control chip U1 adopt the twenty-third pin U1_23, the thirty-fifth pin U1_35 and the forty-seventh pin U1_47 of the STM32F103C8T6; the crystal oscillator X1 adopts the TAXM8M4RDBCCT2T crystal oscillator, the fifty-third resistor R53 has a resistance of 1M ohm, and the thirty-eighth capacitor C38 and the thirty-ninth capacitor C39 adopt capacitors with a specification of 10pF / 25V.

[0360] The resistance of the fifty-fourth resistor R54 is 10K ohms, the third connector J3 adopts the HDR2.54-1X4 model connector, and the fortieth capacitor C40 adopts a 0.1uF / 25V capacitor.

[0361] The forty-fifth capacitor C45, the forty-sixth capacitor C46 and the forty-seventh capacitor C47 are all 0.1uF / 25V capacitors.

[0362] Specifically, the USB connector USB1 adopts a USB connector of model TYPEC-304J-BCP16, the first transmission pin of the USB connector USB1 adopts the sixth pin USB1_6 and the eighth pin USB1_8 of TYPEC-304J-BCP16, the second transmission pin of the USB connector USB1 adopts the fifth pin USB1_5 and the seventh pin USB1_7 of TYPEC-304J-BCP16, the ground pin of the USB connector USB1 adopts the first pin USB1_1 and the twelfth pin USB1_12 and the SH1, SH2, SH3 and SH4 pins of TYPEC-304J-BCP16, and the power pin of the USB connector USB1 adopts the second pin USB1_2 and the eleventh pin USB1_11 of TYPEC-304J-BCP16.

[0363] The forty-second capacitor C42 and the forty-third capacitor C43 are 22uF / 25V capacitors, and the forty-fourth capacitor C44 is 0.1uF / 25V capacitor.

[0364] The fifth MOS tube M5 adopts a MOS tube of the HSCE2631 model, the source of the fifth MOS tube M5 adopts the first pin M5_1, the second pin M5_2 and the third pin M5_3 of the HSCE2631, the gate of the fifth MOS tube M5 adopts the fourth pin M5_4 of the HSCE2631, and the drain of the fifth MOS tube M5 adopts the fifth pin M5_5, the sixth pin M5_6, the seventh pin M5_7, the eighth pin M5_8 and the ninth pin M5_9 of the HSCE2631.

[0365] The resistance value of the fifty-sixth resistor R56 is 1M ohm, the resistance value of the fifty-seventh resistor R57 is 10K ohm, and the fourth connector J4 adopts the HDR2.54-1X2 model connector.

[0366] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-precision digital angle measuring instrument, characterized in that: include, Control chip (U1); A sensor (2) acquires an angle signal, wherein the sensor (2) is connected to the control chip (U1) via a level conversion circuit (3) to transmit the angle signal; A communication circuit (4) connected to the control chip (U1) for transmitting the angle signal to an external terminal; A battery management circuit (5) is connected to the control chip (U1) via a step-up / step-down circuit (51) to output a first power supply voltage (V1) and a second power supply voltage (V2); A switch control circuit (6) is connected to the battery management circuit (5).

2. The high-precision digital angle measuring instrument according to claim 1, characterized in that: The sensor (2) adopts a 3D-MEMS-based sensing chip (U3), and two acceleration sensing elements are arranged inside the sensor (2), wherein the measuring axes of the two acceleration sensing elements are parallel to the installation plane and orthogonal to each other.

3. The high-precision digital angle measuring instrument according to claim 1, characterized in that: The buck-boost circuit (51) adopts a single-ended start-up flyback topology structure, and the buck-boost circuit (51) is connected to a switch control signal output by the switch control circuit (6).

4. The high-precision digital angle measuring instrument according to claim 1, characterized in that: The control chip (U1), the sensor (2), the communication circuit (4), the battery management circuit (5) and the switch control circuit (6) are all arranged in an outer shell, the outer surface of the outer shell is embedded with a magnet, the outer shell can be magnetically attracted to an external measuring device through the magnet, and the outer side of the outer shell is provided with an impact-resistant layer and a wear-resistant layer.

5. The high-precision digital angle measuring instrument according to claim 1, characterized in that: It also comprises a display drive circuit (7) and a power collection circuit, wherein the control chip (U1) is connected to the display screen (8) via the display drive circuit (7) to output the angle signal, and the power collection circuit is connected to the display screen (8) to output a remaining power signal.

6. The high-precision digital angle measuring instrument according to claim 4, characterized in that: The communication circuit (4) comprises an RS485 communication circuit (41) and a LoRa wireless communication circuit (42); the RS485 communication circuit (41) is connected to the control chip (U1) via an RS485 interface; and an isolation chip (U4) and an electrostatic protection circuit are provided on the RS485 interface; The RS485 communication circuit (41) comprises: An isolation chip (U4) connected to the control chip (U1); a converter chip (U5), the converter chip (U5) being connected to the isolation chip (U4), and the converter chip (U5) outputting a third power supply voltage (V3) based on the second power supply voltage (V2); RS485 transceiver chip (U6), connected to the isolation chip; The LoRa wireless communication circuit (42) is provided with a LoRa chip (U7), and the LoRa chip (U7) is connected to the control chip.

7. The high-precision digital angle measuring instrument according to claim 1, characterized in that: The level conversion circuit (3) comprises a level conversion chip (U2), a first level receiving pin of the level conversion chip (U2) is connected to a first level output pin of the control chip (U1), a first transmission end pin of the level conversion chip (U2) is connected to a first serial transmission pin of the control chip (U1), a first logic pin of the level conversion chip (U2) is connected to a level conversion control pin (U1_46) of the control chip (U1), a second logic pin of the level conversion chip (U2) is grounded, a first power pin of the level conversion chip (U2) is connected to the first power supply voltage (V1), a second power pin of the level conversion chip (U2) is connected to the second power supply voltage (V2), and a ground pin of the level conversion chip (U2) is grounded; The level conversion circuit (3) further includes: a first capacitor (C1), wherein a first end of the first capacitor (C1) is connected to a first power pin of the level conversion chip (U2), and a second end of the first capacitor (C1) is connected to a second logic pin of the level conversion chip (U2); a second capacitor (C2), wherein a first end of the second capacitor (C2) is connected to a second power supply pin of the level conversion chip (U2), and a second end of the second capacitor (C2) is grounded; A sensing chip (U3), wherein a transmission end pin of the sensing chip (U3) is connected to a second transmission end pin of the level conversion chip (U2), an output pin of the sensing chip (U3) is connected to a first receiving pin of the level conversion chip (U2), a power supply pin of the sensing chip (U3) is connected to the first power supply voltage (V1), and a ground pin of the sensing chip (U3) is grounded; The sensor (2) further comprises a third capacitor (C3), a first end of the third capacitor (C3) being connected to a power pin of the sensor chip (U3), and a second end of the third capacitor (C3) being grounded.

8. The high-precision digital angle measuring instrument according to claim 3, characterized in that: The battery management circuit (5) comprises: A battery management chip (U8), wherein a temperature monitoring pin (U8_10) of the battery management chip (U8) is connected to a thermistor voltage (TS), and an analog ground pin (U8_25) of the battery management chip (U8) is grounded; A first diode (D1), wherein an anode of the first diode (D1) is connected to a charging voltage; a second diode (D2), wherein an anode of the second diode (D2) is connected to an input voltage, and a cathode of the second diode (D2) is connected to a cathode of the first diode (D1); a twentieth resistor (R20), wherein a first end of the twentieth resistor (R20) is connected to the cathode of the second diode (D2), and a second end of the twentieth resistor (R20) is connected to the first power pin (U8_4) of the battery management chip (U8); a ninth capacitor (C9), wherein a first end of the ninth capacitor (C9) is connected to a second end of the twentieth resistor (R20), and a second end of the ninth capacitor (C9) is grounded; a twenty-first resistor (R21), wherein a first end of the twenty-first resistor (R21) is connected to the input voltage; a tenth capacitor (C10), wherein a first end of the tenth capacitor (C10) is connected to a second end of the twenty-first resistor (R21), and a second end of the tenth capacitor (C10) is grounded; a first MOS transistor (M1), wherein a drain of the first MOS transistor (M1) is connected to the input voltage; a twenty-second resistor (R22), wherein a first end of the twenty-second resistor (R22) is connected to the gate of the first MOS tube (M1), and a second end of the twenty-second resistor (R22) is connected to a first driving pin (U8_8) of the battery management chip (U8); a twenty-third resistor (R23), wherein a first end of the twenty-third resistor (R23) is connected to the source of the first MOS tube (M1), and a second end of the twenty-third resistor (R23) is connected to a current detection pin (U8_7) of the battery management chip (U8); a second MOS transistor (M2), wherein a source of the second MOS transistor (M2) is connected to a source of the first MOS transistor (M1), a gate of the second MOS transistor (M2) is connected to a first end of a twenty-second resistor (R22), and a drain of the second MOS transistor (M2) is connected to a first positive input pin (U8_6) of the battery management chip (U8); a twenty-fourth resistor (R24), wherein a first end of the twenty-fourth resistor (R24) is connected to the drain of the second MOS tube (M2), a second end of the twenty-fourth resistor (R24) is connected to a second power pin (U8_2) (U8_2), a third power pin (U8_3) and a first negative input pin (U8_5) of the battery management chip (U8), and a supply voltage (V0) is output from the second end of the twenty-fourth resistor (R24); an eleventh capacitor (C11), a first end of the eleventh capacitor (C11) being connected to a first end of the twenty-fourth resistor (R24), and a second end of the eleventh capacitor (C11) being connected to a second end of the twenty-fourth resistor (R24); a twelfth capacitor (C12), wherein a first end of the twelfth capacitor (C12) is connected to a second power pin (U8_2) of the battery management chip (U8), and a second end of the twelfth capacitor (C12) is grounded; a twenty-fifth resistor (R25), wherein a first end of the twenty-fifth resistor (R25) is connected to a reference voltage; An indicator light (LED1), wherein a positive electrode of the indicator light (LED1) is connected to a first end of the twenty-fifth resistor (R25), and a negative electrode of the indicator light (LED1) is connected to a status indication pin (U8_9) of the battery management chip (U8); a twenty-sixth resistor (R26), a first end of the twenty-sixth resistor (R26) being connected to the first end of the twenty-fifth resistor (R25), and a second end of the twenty-sixth resistor (R26) being connected to a temperature monitoring pin (U8_10) of the battery management chip (U8); a twenty-seventh resistor (R27), a first end of the twenty-seventh resistor (R27) being connected to the second end of the twenty-sixth resistor (R26), and a second end of the twenty-seventh resistor (R27) being grounded; a thirteenth capacitor (C13), wherein a first end of the thirteenth capacitor (C13) is connected to a termination control pin (U8_11) of the battery management chip (U8), and a first end of the thirteenth capacitor (C13) is grounded; a fourteenth capacitor (C14), wherein a first end of the fourteenth capacitor (C14) is connected to a first switch pin (U8_1) and a second switch pin (U8_24) of the battery management chip (U8), and a second end of the fourteenth capacitor (C14) is connected to a temperature compensation pin (U8_21) of the battery management chip (U8); a third diode (D3), wherein a cathode of the third diode (D3) is connected to a first end of the fourteenth capacitor (C14), and an anode of the third diode (D3) is grounded; a first inductor (L1), wherein a first end of the first inductor (L1) is connected to a cathode of the third diode (D3), and a second end of the first inductor (L1) is connected to a second positive input pin (U8_16) of the battery management chip (U8); a twenty-eighth resistor (R28), wherein a first end of the twenty-eighth resistor (R28) is connected to a second end of the first inductor (L1), a second end of the twenty-eighth resistor (R28) is connected to a second negative input pin (U8_15) of the battery management chip (U8), and the charging voltage is output from the second end of the twenty-eighth resistor (R28); a fifteenth capacitor (C15), wherein a first end of the fifteenth capacitor (C15) is connected to a first end of the twenty-eighth resistor (R28), and a second end of the fifteenth capacitor (C15) is connected to a second end of the twenty-eighth resistor (R28); a sixteenth capacitor (C16), a first end of the sixteenth capacitor (C16) being connected to the second end of the twenty-eighth resistor (R28), and a second end of the sixteenth capacitor (C16) being grounded; a seventeenth capacitor (C17), wherein a first end of the seventeenth capacitor (C17) is connected to a second end of the twenty-eighth resistor (R28), and a second end of the seventeenth capacitor (C17) is grounded; a third MOS transistor (M3), wherein a drain of the third MOS transistor (M3) is connected to the second end of the twenty-eighth resistor (R28), and a source of the third MOS transistor (M3) is connected to the power supply voltage (V0); an eighteenth capacitor (C18), wherein a first end of the eighteenth capacitor (C18) is connected to a second end of the eleventh capacitor (C11), and a second end of the eighteenth capacitor (C18) is grounded; A nineteenth capacitor (C19), wherein a first end of the nineteenth capacitor (C19) is connected to an output voltage pin (U8_20) of the battery management chip (U8), and a second end of the nineteenth capacitor (C19) is connected to a first power ground pin (U8_22) and a second power ground pin (U8_23) of the battery management chip (U8) and then grounded; a twenty-ninth resistor (R29), wherein a first end of the twenty-ninth resistor (R29) is connected to a second drive pin of the battery management chip (U8), and a second end of the twenty-ninth resistor (R29) is connected to a gate of the third MOS tube (M3); a twentieth capacitor (C20), wherein a first end of the twentieth capacitor (C20) is connected to the second end of the first inductor (L1), and a second end of the twentieth capacitor (C20) is grounded; a 30th resistor (R30), wherein a first end of the 30th resistor (R30) is connected to a first setting pin (U8_17) of the battery management chip (U8), and a second end of the 30th resistor (R30) is connected to the reference voltage; a thirty-first resistor (R31), wherein a first end of the thirty-first resistor (R31) is connected to a second end of the thirtieth resistor (R30), and a second end of the thirty-first resistor (R31) is grounded; a thirty-second resistor (R32), a first end of the thirty-second resistor (R32) being connected to a battery voltage, and a second end of the thirty-second resistor (R32) being connected to a protection pin (U8_18) of the battery management chip (U8); a thirty-third resistor (R33), wherein a first end of the thirty-third resistor (R33) is connected to a second end of the thirty-second resistor (R32), and a second end of the thirty-third resistor (R33) is grounded; a thirty-fourth resistor (R34), a first end of the thirty-fourth resistor (R34) being connected to the drain of the third MOS tube (M3), and a second end of the thirty-fourth resistor (R34) being connected to the feedback pin (U8_14) of the battery management chip (U8); a thirty-fifth resistor (R35), wherein a first end of the thirty-fifth resistor (R35) is connected to a second end of the thirty-fourth resistor (R34), and a second end of the thirty-fifth resistor (R35) is grounded; a thirty-sixth resistor (R36), wherein a first end of the thirty-sixth resistor (R36) is connected to a fourth power pin (U8_12) of the battery management chip (U8) and then connected to the reference voltage, and a second end of the thirty-sixth resistor (R36) is connected to a second setting pin (U8_13) of the battery management chip (U8); a thirty-seventh resistor (R37), a first end of the thirty-seventh resistor (R37) being connected to the second end of the thirty-sixth resistor (R36), and a second end of the thirty-seventh resistor (R37) being grounded; A twenty-first capacitor (C21), a first end of the twenty-first capacitor (C21) is connected to the first end of the thirty-sixth resistor (R36), and a second end of the twenty-first capacitor (C21) is grounded.

9. The high-precision digital angle measuring instrument according to claim 8, characterized in that: The switch control circuit (6) comprises: A switch control chip (U11), wherein a power supply pin (U11_6) of the switch control chip (U11) is connected to the power supply voltage (V0), an interrupt output pin (U11_8) of the switch control chip (U11) is connected to an interrupt control pin (U1_22) of the control chip (U1), and an enable output pin (U11_2) of the switch control chip (U11) is connected to a forty-fourth resistor (R44) and then connected to a drive control pin (U1_21) of the control chip (U1); a forty-second resistor (R42), wherein a first end of the forty-second resistor (R42) is connected to a power pin (U11_6) of the switch control chip (U11), and a second end of the forty-second resistor (R42) is connected to a monitoring input pin (U11_1) of the switch control chip (U11); a forty-third resistor (R43), wherein a first end of the forty-third resistor (R43) is connected to a second end of the forty-second resistor (R42), and a second end of the forty-third resistor (R43) is grounded; a twenty-ninth capacitor (C29), wherein a first end of the twenty-ninth capacitor (C29) is connected to a first end of the forty-second resistor (R42), and a second end of the twenty-ninth capacitor (C29) is grounded; a 30th capacitor (C30), wherein a first end of the 30th capacitor (C30) is connected to a timer pin (U11_3) of the switch control chip (U11), and a second end of the 30th capacitor (C30) is grounded; a fourth MOS tube (M4), wherein the drain of the fourth MOS tube (M4) is connected to the first end of the twenty-ninth capacitor (C29), the gate of the fourth MOS tube (M4) is connected to the enable pin (U11_7) of the switch control chip (U11), and the source of the fourth MOS tube (M4) generates the switch control signal; a forty-fifth resistor (R45), wherein a first end of the forty-fifth resistor (R45) is connected to the gate of the fourth MOS tube (M4), and a second end of the forty-fifth resistor (R45) is connected to a ground pin (U11_4) of the switch control chip (U11) and then grounded; a forty-sixth resistor (R46), a first end of the forty-sixth resistor (R46) being connected to the second power supply voltage (V2), and a second end of the forty-sixth resistor (R46) being connected to an enable output pin (U11_2) of the switch control chip (U11); a forty-seventh resistor (R47), a first end of the forty-seventh resistor (R47) being connected to the second power supply voltage (V2), and a second end of the forty-seventh resistor (R47) being connected to an interrupt output pin (U11_8) of the switch control chip (U11); A first connector (J1), wherein a first pin (J1_1) of the first connector (J1) is grounded, a second pin (J1_2) of the first connector (J1) is connected to a holding pin (U1_41) of the control chip (U1), a third pin (J1_3) of the first connector (J1) is connected to a second reset control pin (U1_10) of the control chip (U1), and a fourth pin (J1_4) of the first connector (J1) is connected to a button input pin (U11_5) of the switch control chip (U11) to receive a system switch signal; a first protection diode (ESD1), wherein a first end of the first protection diode (ESD1) is connected to a fourth pin (J1_4) of the first connector (J1), and a second end of the first protection diode (ESD1) is connected to a first pin (J1_1) of the first connector (J1); a thirty-first capacitor (C31), wherein a first end of the thirty-first capacitor (C31) is connected to a first end of the first protection diode (ESD1), and a second end of the thirty-first capacitor (C31) is connected to a second end of the first protection diode (ESD1); a second protection diode (ESD2), wherein a first end of the second protection diode (ESD2) is connected to a third pin (J1_3) of the first connector (J1), and a second end of the first protection diode (ESD1) is connected to a first pin (J1_1) of the first connector (J1); a thirty-second capacitor (C32), wherein a first end of the thirty-second capacitor (C32) is connected to a first end of the second protection diode (ESD2), and a second end of the thirty-second capacitor (C32) is connected to a second end of the second protection diode (ESD2); a third protection diode (ESD3), wherein a first end of the third protection diode (ESD3) is connected to a second pin (J1_2) of the first connector (J1), and a second end of the third protection diode (ESD3) is connected to a first pin (J1_1) of the first connector (J1); a thirty-third capacitor (C33), wherein a first end of the thirty-third capacitor (C33) is connected to a first end of the third protection diode (ESD3), and a second end of the thirty-third capacitor (C33) is connected to a second end of the third protection diode (ESD3); a forty-eighth resistor (R48), wherein a first end of the forty-eighth resistor (R48) is connected to the second supply voltage (V2), and a second end of the forty-eighth resistor (R48) is connected to a first end of the thirty-first capacitor (C31); a forty-ninth resistor (R49), wherein a first end of the forty-ninth resistor (R49) is connected to a first end of the forty-eighth resistor (R48), and a second end of the forty-ninth resistor (R49) is connected to a first end of the thirty-second capacitor (C32); A fiftieth resistor (R50), a first end of the fiftieth resistor (R50) is connected to a first end of the forty-eighth resistor (R48), and a second end of the fiftieth resistor (R50) is connected to a first end of the thirty-third capacitor (C33).

10. The high-precision digital angle measuring instrument according to claim 6, characterized in that: Also includes, a fourth inductor (L4), a first end of the fourth inductor (L4) connected to the second supply voltage (V2), a second end of the fourth inductor (L4) connected to an analog power pin (U1_9) of the control chip (U1), and a power pin of the control chip (U1) connected to the second supply voltage (V2); a fifth inductor (L5), wherein a first end of the fifth inductor (L5) is connected to an analog ground pin (U1_8) of the control chip (U1), and a second end of the fifth inductor (L5) is connected to a ground pin of the control chip (U1) and then grounded; A thirty-seventh capacitor (C37), a first end of the thirty-seventh capacitor (C37) is connected to an analog power pin (U1_9) of the control chip (U1), and a second end of the thirty-seventh capacitor (C37) is connected to an analog ground pin (U1_8) of the control chip (U1); A crystal oscillator (X1), wherein a first crystal pin of the crystal oscillator (X1) is connected to a first crystal oscillator pin (U1_5) of the control chip (U1), a second crystal pin of the crystal oscillator (X1) is connected to a second crystal oscillator pin (U1_6) of the control chip (U1), and a ground pin of the crystal oscillator (X1) is grounded; a fifty-third resistor (R53), wherein a first end of the fifty-third resistor (R53) is connected to a first crystal pin of the crystal oscillator (X1), and a second end of the fifty-third resistor (R53) is connected to a second crystal pin of the crystal oscillator (X1); a thirty-eighth capacitor (C38), wherein a first end of the thirty-eighth capacitor (C38) is connected to a first crystal pin of the crystal oscillator (X1), and a second end of the thirty-eighth capacitor (C38) is connected to a ground pin of the crystal oscillator (X1); a thirty-ninth capacitor (C39), wherein a first end of the thirty-ninth capacitor (C39) is connected to a second crystal pin of the crystal oscillator (X1), and a second end of the thirty-ninth capacitor (C39) is connected to a ground pin of the crystal oscillator (X1); a fifty-fourth resistor (R54), wherein a first end of the fifty-fourth resistor (R54) is connected to an on pin (U1_44) of the control chip (U1), and a second end of the fifty-fourth resistor (R54) is grounded; a third connector (J3), wherein a first pin (J3_1) of the third connector (J3) is grounded, a second pin (J3_2) of the third connector (J3) is connected to a second clock signal pin (U1_37) of the control chip (U1), a third pin (J3_3) of the third connector (J3) is connected to a data transmission pin (U1_34) of the control chip (U1), and a fourth pin (J3_4) of the third connector (J3) is connected to the second power supply voltage (V2); a fortieth capacitor (C40), wherein a first end of the fortieth capacitor (C40) is connected to a fourth pin (J3_4) of the third connector (J3), and a second end of the fortieth capacitor (C40) is grounded; a fifty-fifth resistor (R55), a first end of the fifty-fifth resistor (R55) being connected to the second supply voltage (V2), and a second end of the fifty-fifth resistor (R55) being connected to a reset pin (U1_7) of the control chip (U1); a forty-first capacitor (C41), a first end of the forty-first capacitor (C41) being connected to the second end of the fifty-fifth resistor (R55), and a second end of the forty-first capacitor (C41) being grounded; a forty-fifth capacitor (C45), wherein a first end of the forty-fifth capacitor (C45) is connected to the second supply voltage (V2), and a second end of the forty-fifth capacitor (C45) is grounded; a forty-sixth capacitor (C46), a first end of the forty-sixth capacitor (C46) connected to the first end of the forty-fifth capacitor (C45), and a second end of the forty-sixth capacitor (C46) connected to the second end of the forty-fifth capacitor (C45); a forty-seventh capacitor (C47), a first end of the forty-seventh capacitor (C47) connected to the first end of the forty-fifth capacitor (C45), and a second end of the forty-seventh capacitor (C47) connected to the second end of the forty-fifth capacitor (C45); Also included is an interface circuit, the interface circuit comprising, A USB connector (USB1), wherein a first transmission pin of the USB connector (USB1) is connected to a second transmission pin (U6_6) of the RS485 transceiver chip (U6), and the second transmission pin of the USB connector (USB1) is connected to a first transmission pin (U6_7) of the RS485 transceiver chip (U6); a forty-second capacitor (C42), wherein a first end of the forty-second capacitor (C42) is connected to a power pin of the USB connector (USB1), and a second end of the forty-second capacitor (C42) is grounded; a forty-third capacitor (C43), wherein a first end of the forty-third capacitor (C43) is connected to a first end of the forty-second capacitor (C42), and a second end of the forty-third capacitor (C43) is connected to a second end of the forty-second capacitor (C42); a forty-fourth capacitor (C44), a first end of the forty-fourth capacitor (C44) connected to the first end of the forty-second capacitor (C42), and a second end of the forty-fourth capacitor (C44) connected to the second end of the forty-second capacitor (C42); a fifth MOS tube (M5), wherein a drain electrode of the fifth MOS tube (M5) is connected to a power pin of the USB connector (USB1), and a source electrode of the fifth MOS tube (M5) is connected to the battery management circuit (5); a fifty-sixth resistor (R56), wherein a first end of the fifty-sixth resistor (R56) is connected to the gate of the fifth MOS transistor (M5), and a second end of the fifty-sixth resistor (R56) is grounded; a fifty-seventh resistor (R57), wherein a first end of the fifty-seventh resistor (R57) is connected to the gate of the fifth MOS transistor (M5), and a second end of the fifty-seventh resistor (R57) is connected to the source of the fifth MOS transistor (M5); A fourth connector (J4), wherein a first pin (J4_1) of the fourth connector (J4) is connected to a source of the fifth MOS tube (M5), and a second pin (J4_2) of the fourth connector (J4) is connected to a second end of the fifty-sixth resistor (R56).

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