Hardware circuit for realizing DRAM (Dynamic Random Access Memory) capacity expansion and solid state disk
By designing a hardware circuit that includes a main controller and multiple synchronous dynamic random memory, using specific plug-in connections and zero-ohm resistor plug-in, the problems of DDR4 particle capacity limitation and SSD PCB size limitation are solved, and the DRAM capacity is doubled and the SSD disk design is supported with a larger capacity.
Patent Information
- Application Number
- CN202421837925.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2034-07-31
AI Technical Summary
Due to the DDR4 particle capacity limitation and SSD PCB size limitation, existing solid state drives (SSDs) cannot effectively expand DRAM storage capacity, resulting in the inability to achieve SSD hardware design with 32TB and larger capacity.
Design a hardware circuit to realize DRAM expansion, including a main controller and multiple synchronous dynamic random memory, and double the DRAM capacity through specific plug-in connections and zero-ohm resistor plug-in.
Without changing the SSD PCB stacking design and hardware overall solution, double the DRAM capacity and support larger-capacity SSD disk design.
Smart Images
Figure CN222813139U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of storage, and in particular to a hardware circuit and a solid state hard disk for realizing DRAM capacity expansion. Background Art
[0002] Compared with hard disk drives (HDD), solid state drives (SSD) have greater advantages in speed, power consumption, capacity, noise, reliability and other performance. At present, although hard disks have certain advantages in price, with the emergence of large-capacity flash memory chips (Flash EEPROM Memory, FLASH, of which NAND Flash is a type of FLASH), SSDs are increasingly widely used in servers and storage devices. From a hardware perspective, SSDs include a main controller and dynamic random access memory (Dynamic Random Access Memory, DRAM). The main controller is generally composed of one or more CPU cores to achieve communication between the standard front-end interface (such as PCIe interface) and the host. DRAM is used for caching and information management of front-end and back-end data during SSD operation. In order to ensure the read and write performance of SSD, the ratio of NAND Flash to DRAM capacity must be at least 1000:1. Therefore, if the NAND raw capacity of a single disk is 128TB, the required DRAM cache storage capacity is 128GB.
[0003] In SSD-related products, different DDR4 chips are generally used as external DRAM cache space, but due to the capacity limitations of the SSD PCB board space and DDR4 chips (the capacity of DDR4 chips is generally 4Gb / 8Gb / 16Gb, etc.), the external DRAM capacity can generally only reach 16GB. Therefore, the capacity of a single DDR4 chip cannot be increased and the limitation of the SSD PCB size makes it impossible to expand the DRAM storage capacity, and thus it is impossible to implement the hardware design of 32T and larger capacity SSD disks. Summary of the invention
[0004] In order to solve the problem of expanding the storage capacity of a solid state hard disk DRAM, the utility model provides a hardware circuit and a solid state hard disk for realizing DRAM expansion.
[0005] In the first aspect, the technical solution of the utility model provides a hardware circuit for realizing DRAM expansion, including a main controller and a plurality of synchronous dynamic random access memories;
[0006] Each of the synchronous dynamic random access memories is provided with a data port, a first function configuration input pin, a second function configuration input pin and a third function configuration input pin; the first function configuration input pins of the synchronous dynamic random access memories are connected, the second function configuration input pins are connected, and the third function configuration input pins are connected;
[0007] The main controller comprises a first selection pin, a second selection pin, a third selection pin, a second clock enable pin, a second chip select pin, a second internal termination pin and a plurality of data interfaces; each data port of the synchronous dynamic random access memory is respectively connected to a data interface of the main controller;
[0008] A first function configuration input pin of a synchronous dynamic random access memory is connected to a first selection pin and a second clock enable pin through a socket, a second function configuration input pin is connected to a second selection pin and a second chip select pin through a socket, and a third function configuration input pin is connected to a third selection pin and a second internal termination pin through a socket;
[0009] According to the type of synchronous dynamic random access memory, a zero-ohm resistor is plugged into the corresponding socket to electrically connect the main controller with the synchronous dynamic random access memory to realize DRAM expansion.
[0010] As a preferred embodiment of the technical solution of the utility model, the main controller is also provided with a first clock enable pin, a first chip select pin and a first internal termination pin; each synchronous dynamic random access memory is provided with a clock enable pin, a chip select pin and an internal termination pin;
[0011] The first clock enable pin, the first chip select pin and the first internal termination pin of the main controller are respectively connected in sequence with the clock enable pin, the chip select pin and the internal termination pin of each synchronous dynamic random access memory.
[0012] As a preferred embodiment of the technical solution of the utility model, the synchronous dynamic random access memory includes at least one of a single-chip packaged dynamic random access memory, a dual-chip packaged dynamic random access memory, a 2H three-dimensional stacked synchronous dynamic random access memory, a 4H three-dimensional stacked synchronous dynamic random access memory, and an 8H three-dimensional stacked synchronous dynamic random access memory.
[0013] As a preferred embodiment of the technical solution of the utility model, when the synchronous dynamic random access memory is a single-chip packaged dynamic random access memory, all the sockets are not loaded.
[0014] As a preferred embodiment of the technical solution of the utility model, when the synchronous dynamic random access memory is a dual-chip packaged dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin and the second clock enable pin, and the first function configuration input pin is electrically connected to the second clock enable pin; a zero-ohm resistor is inserted into the socket connecting the second function configuration input pin and the second chip select pin, and the second function configuration input pin is electrically connected to the second chip select pin; a zero-ohm resistor is inserted into the socket connecting the third function configuration input pin and the second internal termination pin, and the third function configuration input pin is electrically connected to the second internal termination pin.
[0015] As a preferred embodiment of the technical solution of the utility model, when the synchronous dynamic random access memory is a 2H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin and the first selection pin, the first function configuration input pin is electrically connected to the first selection pin, and the remaining sockets are not loaded.
[0016] As a preferred embodiment of the technical solution of the utility model, when the synchronous dynamic random access memory is a 4H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is plugged into the socket connecting the first function configuration input pin and the first selection pin, and the first function configuration input pin is electrically connected to the first selection pin; a zero-ohm resistor is plugged into the socket connecting the second function configuration input pin and the second selection pin, and the second function configuration input pin is electrically connected to the second selection pin, and the remaining sockets are not loaded.
[0017] As a preferred embodiment of the technical solution of the utility model, when the synchronous dynamic random access memory is an 8H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is plugged into the socket connecting the first function configuration input pin and the first selection pin, and the first function configuration input pin is electrically connected to the first selection pin; a zero-ohm resistor is plugged into the socket connecting the second function configuration input pin and the second selection pin, and the second function configuration input pin is electrically connected to the second selection pin; a zero-ohm resistor is plugged into the socket connecting the third function configuration input pin and the third selection pin, and the third function configuration input pin is electrically connected to the third selection pin, and the remaining sockets are not loaded.
[0018] In a second aspect, the utility model provides a solid state hard disk, comprising a hardware circuit for realizing DRAM capacity expansion as described in the first aspect.
[0019] As a preferred embodiment of the technical solution of the utility model, it also includes a mainboard, the hardware circuit is arranged on the mainboard, and a storage connector is also arranged on the mainboard; the synchronous dynamic random access memory is arranged on the storage connector and connected to the main controller through the storage connector.
[0020] It can be seen from the above technical scheme that the utility model has the following advantages: using 3DS DDR4 materials with the same package size as ordinary DDR4 for material selection and hardware circuit design can double the capacity of DRAM, thereby realizing the design of a large-capacity disk while keeping the same PCB stacking design and overall hardware solution unchanged.
[0021] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 It is an application circuit and a topological diagram provided by the utility model.
[0024] Figure 2 It is the main controller extended SDP DDR4 application circuit and topology diagram in the embodiment of the utility model.
[0025] Figure 3 This is the main controller expansion 32Gb x8 DDP DDR4 application circuit and topology diagram in the embodiment of the utility model.
[0026] Figure 4 This is the main controller expansion 16Gb x8 2H 3DS DDR4 application circuit and topology diagram in the embodiment of the utility model.
[0027] Figure 5 This is the main controller expansion 16Gb x8 4H 3DS DDR4 application circuit and topology diagram in the embodiment of the utility model.
[0028] Figure 6 This is the main controller expansion 16Gb x8 8H 3DS DDR4 application circuit and topology diagram in the embodiment of the utility model. DETAILED DESCRIPTION
[0029] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention. The abbreviations and key terms that need to be annotated in this application are as follows:
[0030] SSD (Solid State Disk);
[0031] HDD (Hard Disk Drive);
[0032] CPU (Central Processing Unit);
[0033] DDR4 SDRAM (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory);
[0034] SDP (Single Die per Package, also known as single chip package in this application);
[0035] DDP (Double Die per Package, double die package, also called dual chip package in this application);
[0036] 2H / 4H / 8H 3DS (Three Dimensional Stacking);
[0037] DRAM (Dynamic Random Access Memory);
[0038] FLASH (Flash EEPROM Memory, flash memory chip, NAND Flash is a type of Flash);
[0039] PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard);
[0040] PCB (Printed Circuit Board);
[0041] NC (NO Connection, meaning no connection, no welding);
[0042] ECC (Error Correcting Code, error checking and correction).
[0043] like Figure 1 As shown, the embodiment of the utility model provides a hardware circuit for realizing DRAM expansion, including a main controller and a plurality of synchronous dynamic random access memories; in the embodiment of the utility model, the number of the synchronous dynamic random access memories is nine;
[0044] Each synchronous dynamic random access memory is provided with a data port, a first function configuration input pin G2, a second function configuration input pin G8 and a third function configuration input pin F2; the first function configuration input pins of the synchronous dynamic random access memories are connected, the second function configuration input pins are connected, and the third function configuration input pins are connected;
[0045] The main controller includes a first selection pin DDR_CID0, a second selection pin DDR_CID1, a third selection pin DDR_CID2, a second clock enable pin DDR_CKE1, a second chip select pin DDR_CS1, a second internal termination pin DDR_ODT1 and a plurality of data interfaces; the data port of each synchronous dynamic random access memory is respectively connected to a data interface of the main controller;
[0046] A first function configuration input pin G2 of one dynamic random access memory is connected to the first selection pin DDR_CID0 through the first socket W1, the first function configuration input pin G2 is connected to the second clock enable pin DDR_CKE1 through the second socket W2, the second function configuration input pin G8 is connected to the second selection pin DDR_CID1 through the third socket W3, the second function configuration input pin G8 is connected to the second chip select pin DDR_CS1 through the fourth socket W4, the third function configuration input pin F2 is connected to the third selection pin DDR_CID2 through the fifth socket W5, and the third function configuration input pin F2 is connected to the second internal termination pin DDR_ODT1 through the sixth socket W5;
[0047] According to the type of synchronous dynamic random access memory, a zero-ohm resistor is plugged into the corresponding socket to electrically connect the main controller to the synchronous dynamic random access memory to achieve DRAM expansion.
[0048] It should be noted that the main controller is also provided with a first clock enable pin DDR_CKE0, a first chip select pin DDR_CS0 and a first internal termination pin DDR_ODT0; each synchronous dynamic random access memory is provided with a clock enable pin CKE, a chip select pin CS_n and an internal termination pin ODT;
[0049] The first clock enable pin DDR_CKE0, the first chip select pin DDR_CS0 and the first internal termination pin DDR_ODT0 of the main controller are respectively connected in sequence with the clock enable pin CKE, the chip select pin CS_n and the internal termination pin ODT of each synchronous dynamic random access memory.
[0050] In an embodiment of the utility model, the synchronous dynamic random access memory includes a single die packaged dynamic random access memory, a dual die packaged dynamic random access memory, a 2H three-dimensional stacked synchronous dynamic random access memory, a 4H three-dimensional stacked synchronous dynamic random access memory, and an 8H three-dimensional stacked synchronous dynamic random access memory.
[0051] The embodiment of the utility model takes Microchip PCIe5.0 controller Yorktown as an example to illustrate. The main controller supports 2H / 4H / 8H 3DS DDR4 and ordinary SDP, DDP DDR4. The main controller supports 72-bit DDR data bit width (64 data bits + 8 ECC check bits). According to the conventional way of expanding DDR4 capacity, (8+1) pieces of 4Gb / 8Gb / 16Gb x8-bit DDR4 are used respectively. The DDR4 capacity space that can be expanded is 4GB, 8GB, and 16GB respectively. The circuit topology diagram of the application is shown in the figure. Figure 1 As shown in Table 1, the effective DRAM space expanded using 4Gb / 8Gb / 16Gb x8 bit width DDR4 is shown.
[0052] Table 1
[0053]
[0054] Yorktown master chip supports 2H / 4H / 8H 3DS DDR4 devices, and its corresponding pins are DDR_CID0, DDR_CID1, and DDR_CID2, which are used to select each layer of dynamic random access memory chip of 2H / 4H / 8H 3DS DDR4 devices. The function distribution of ordinary SDP, DDP DDR4 and 2H / 4H / 8H 3DS DDR4 pins is shown in Table 2. When using SDP DDR4 materials, G2, G8, and F2 pins are NC pins, indicating that they can be disconnected; when using DDP DDR4 materials, G2, G8, and F2 pins are CKE1, CS1_n, and ODT1, respectively, indicating the hardware topology when the DRAM is used as Rank1 and the clock enable signal, chip select signal, and ODT signal when connected. When using 3DS DDR4 materials, the G2, G8, and F2 pins are C0, C1, and C2 respectively, indicating the stack address input pins, which are used to select each layer of dynamic random access memory chip in the 2H / 4H / 8H stack.
[0055] Table 2
[0056]
[0057] like Figure 2 As shown, in one embodiment of the utility model, when the synchronous dynamic random access memory is a single-die packaged dynamic random access memory, all the sockets are not loaded.
[0058] The G2, G8, and F2 pins in the DDR4 chip have no actual function. Figure 1 W1, W2, W3, W4, W5, and W6 are not connected, that is, there is no resistor on the socket and the two ends of the socket are not connected, that is, there is no electrical connection between the six signals DDR_CID0, DDR_CID1, DDR_CID2, DDR_CKE1, DDR_CS1, and DDR_ODT1 of the Yorktown master chip and the nine DDR4 particles; the data lines of the master chip are connected to the data lines of the nine DDR4 particles in sequence to form a 72-bit data bus, and the DDR_CS0, DDR_CKE0, and DDR_ODT0 of the master chip are connected to the CS_n, CKE, and ODT signals of each DDR4 particle in sequence, that is, the Yorktown master chip and the (8+1) DDR4 materials are single-rank communication, and the relevant application circuit is shown in the attached figure. Figure 2 By traversing 8 DDR4 chips and 1 ECC check chip, when the single DDR4 chip is 4Gb, 8Gb, 16Gb x8 bit width, the Yorktown main control chip can achieve 4GB, 8GB, and 16GB of DRAM addressing space.
[0059] In some embodiments, Figure 3 As shown, when the synchronous dynamic random access memory is a dual-die packaged dynamic random access memory, a zero-ohm resistor R2 is inserted into the second socket W2 connecting the first function configuration input pin (clock enable function) and the second clock enable pin, and the first function configuration input pin is electrically connected to the second clock enable pin; a zero-ohm resistor R4 is inserted into the fourth socket W4 connecting the second function configuration input pin (chip select function) and the second chip select pin, and the second function configuration input pin is electrically connected to the second chip select pin; a zero-ohm resistor R6 is inserted into the sixth socket W6 connecting the third function configuration input pin (on-chip internal termination function) and the second internal termination pin, and the third function configuration input pin is electrically connected to the second internal termination pin.
[0060] when Figure 1 When the DDR4 in the application is a DDP material (generally speaking, only large-capacity DRAM particles are available in DDP packaging), in this application, the 32Gb x8-bit DDR4 is a DDP material (that is, it is internally spliced and synthesized by 2 16Gb x8-bit DDR4s, and is a dual-die dual-Rank DDP material). The G2, G8, and F2 pins in the DDP DDR4 particles are CKE1, CS1_n, and ODT1 functions respectively. Figure 1 A zero-ohm resistor R2 is plugged into W2, a zero-ohm resistor R4 is plugged into W4, and a zero-ohm resistor R6 is plugged into W6, that is, the three signals DDR_CKE1, DDR_CS1, and DDR_ODT1 of the Yorktown master chip are electrically connected to the CKE1, CS1_n, and ODT1 signals of the nine DDR4 particles in sequence, respectively, and there is no electrical connection between the three signals DDR_CID0, DDR_CID1, and DDR_CID2 and the nine DDR4 particles; similarly, the data lines of the master are connected to the data lines of the nine DDR4 particles in sequence to form a 72-bit data bus, and the DDR_CS0, DDR_CKE0, and DDR_ODT0 of the master are connected to the CS_n, CKE, and ODT signals of each DDR4 particle in sequence, respectively. The corresponding application circuit and topology are as follows: Figure 3 As shown. When the Yorktown master outputs the control signal DDR_CS0 / DDR_CKE0 / DDR_ODT0, the dynamic random access memory chip corresponding to Rank0 inside each DDP material is selected; when the Yorktown master outputs the control signal DDR_CS1 / DDR_CKE1 / DDR_ODT1, the dynamic random access memory chip corresponding to Rank1 of each DDP material is selected. In short, the master can achieve 32GB of DRAM addressing space through 8 DDP DDR4 and 1 ECC check particle.
[0061] In some embodiments, when the synchronous dynamic random access memory is a 2H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin (first stacked address input function) and the first selection pin, the first function configuration input pin is electrically connected to the first selection pin, and the remaining sockets are not connected.
[0062] when Figure 1 When the DDR4 in the chip is 2H 3DS material, the G2, G8, and F2 pins of the 3DS DDR4 chip have the functions of C0, NC, and NC respectively. Figure 1 A zero-ohm resistor R1 is inserted into W1 in the circuit, that is, the DDR_CID0 signal of the Yorktown master chip is electrically connected to the C0 signal pin of the nine DDR4 particles, and there is no electrical signal connection between the five signals DDR_CKE1, DDR_CS1, DDR_ODT1, DDR_CID1, and DDR_CID2 and the nine DDR4 particles; similarly, the data lines of the master are connected to the data lines of the nine DDR4 particles in sequence to form a 72-bit data bus, and the DDR_CS0, DDR_CKE0, and DDR_ODT0 of the master are connected to the CS_n, CKE, and ODT signals of each DDR4 particle in sequence. The corresponding application circuit and topology are shown in the following figure. Figure 4 The communication between Yorktown master control and 3DSDDR4 particles is single rank. When Yorktown master control outputs 0 and 1 respectively for the ID selection pin DDR_CID0 of DDR4 particles, it selects the two groups of stacking addresses of 2H 3DS DDR4 materials in turn. Since each stacking address can address 16GB, the two groups realize a total of 32GB of DRAM addressing space.
[0063] In some embodiments, when the synchronous dynamic random access memory is a 4H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin (first stacked address input function) and the first selection pin, and the first function configuration input pin is electrically connected to the first selection pin; a zero-ohm resistor is inserted into the socket connecting the second function configuration input pin (second stacked address input function) and the second selection pin, and the second function configuration input pin is electrically connected to the second selection pin, and the remaining sockets are not loaded.
[0064] when Figure 1 When the DDR4 in the chip is 4H 3DS material, the G2, G8, and F2 pins of the 3DS DDR4 chip have the functions of C0, C1, and NC respectively. Figure 1W1 is connected to zero-ohm resistor R1, and W3 is connected to zero-ohm resistor R3, that is, the DDR_CID0 and DDR_CID1 signals of the Yorktown master chip are electrically connected to the C0 and C1 signal pins of the 9 DDR4 particles in sequence, and there is no signal electrical connection between the four signals DDR_CKE1, DDR_CS1, DDR_ODT1, and DDR_CID2 and the 9 DDR4 particles; similarly, the data lines of the master are connected to the data lines of the 9 DDR4 particles in sequence to form a 72-bit data bus, and the DDR_CS0, DDR_CKE0, and DDR_ODT0 of the master are connected to the CS_n, CKE, and ODT signals of each DDR4 particle in sequence. The corresponding application circuit and topology are as follows: Figure 5 The Yorktown master chip and the 3DS DDR4 particles communicate in a single rank. When the Yorktown master selects the ID selection pins DDR_CID0 and DDR_CID1 of the DDR4 particles and outputs 00, 01, 10, and 11 respectively, the 4 groups of stacking addresses of the 4H 3DS DDR4 material are selected in sequence. Since each stacking address can address 16GB, the four groups realize a total of 64GB of DRAM addressing space.
[0065] In some embodiments, when the synchronous dynamic random access memory is an 8H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin (first stacked address input function) and the first selection pin, and the first function configuration input pin is electrically connected to the first selection pin; a zero-ohm resistor is inserted into the socket connecting the second function configuration input pin (second stacked address input function) and the second selection pin, and the second function configuration input pin is electrically connected to the second selection pin; a zero-ohm resistor is inserted into the socket connecting the third function configuration input pin (third stacked address input function) and the third selection pin, and the third function configuration input pin is electrically connected to the third selection pin, and the remaining sockets are not loaded.
[0066] when Figure 1 When the DDR4 in the chip is 8H 3DS material, the G2, G8, and F2 pins of the 3DS DDR4 chip have the functions of C0, C1, and C2 respectively. Figure 1In the figure, zero-ohm resistor R1 is plugged into W1, zero-ohm resistor R3 is plugged into W3, and zero-ohm resistor R5 is plugged into W5, that is, the DDR_CID0, DDR_CID1, and DDR_CID2 signals of the Yorktown master chip are electrically connected to the C0, C1, and C2 signal pins of the nine DDR4 particles in sequence, and there is no signal electrical connection between the three signals DDR_CKE1, DDR_CS1, and DDR_ODT1 and the nine DDR4 particles; similarly, the data lines of the master are connected to the data lines of the nine DDR4 particles in sequence to form a 72-bit data bus, and the DDR_CS0, DDR_CKE0, and DDR_ODT0 of the master are connected to the CS_n, CKE, and ODT signals of each DDR4 particle in sequence, respectively. The corresponding application circuit and topology are as follows: Figure 6 The communication between Yorktown master control and 3DS DDR4 particles is single rank. When Yorktown master control outputs 000, 001, 010, 011, 100, 101, 110, 111 for the ID selection pins DDR_CID0, DDR_CID1, and DDR_CID2 of the DDR4 particles respectively, the 8 groups of stacking addresses of 8H 3DS DDR4 materials are selected in sequence. Since each stacking address can address 16GB, the four groups realize a total of 128GB of DRAM addressing space.
[0067] An embodiment of the utility model provides a solid state hard disk, comprising a hardware circuit for realizing DRAM capacity expansion as described in the above embodiment.
[0068] In some embodiments, the solid state drive includes a mainboard, the hardware circuit is arranged on the mainboard, and a storage connector is also arranged on the mainboard; the synchronous dynamic random access memory is arranged on the storage connector and connected to the main controller through the storage connector.
[0069] Although the present invention is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person skilled in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present technical field may easily think of changes or substitutions within the technical scope disclosed in the present invention, and these shall be within the scope of protection of the present invention.
Claims
1. A hardware circuit for realizing DRAM capacity expansion, characterized in that: It includes a main controller and a plurality of synchronous dynamic random access memories; Each of the synchronous dynamic random access memories is provided with a data port, a first function configuration input pin, a second function configuration input pin and a third function configuration input pin; the first function configuration input pins of the synchronous dynamic random access memories are connected, the second function configuration input pins are connected, and the third function configuration input pins are connected; The main controller comprises a first selection pin, a second selection pin, a third selection pin, a second clock enable pin, a second chip select pin, a second internal termination pin and a plurality of data interfaces; each data port of the synchronous dynamic random access memory is respectively connected to a data interface of the main controller; A first function configuration input pin of a synchronous dynamic random access memory is connected to a first selection pin and a second clock enable pin through a socket, a second function configuration input pin is connected to a second selection pin and a second chip select pin through a socket, and a third function configuration input pin is connected to a third selection pin and a second internal termination pin through a socket; According to the type of synchronous dynamic random access memory, a zero-ohm resistor is plugged into the corresponding socket to electrically connect the main controller to the synchronous dynamic random access memory to achieve DRAM expansion.
2. The hardware circuit for realizing DRAM capacity expansion according to claim 1, characterized in that: The main controller is also provided with a first clock enable pin, a first chip select pin and a first internal termination pin; each of the synchronous dynamic random access memories is provided with a clock enable pin, a chip select pin and an internal termination pin; The first clock enable pin, the first chip select pin and the first internal termination pin of the main controller are respectively connected in sequence with the clock enable pin, the chip select pin and the internal termination pin of each synchronous dynamic random access memory.
3. The hardware circuit for realizing DRAM capacity expansion according to claim 2, characterized in that: The synchronous dynamic random access memory includes at least one of a single-chip packaged dynamic random access memory, a dual-chip packaged dynamic random access memory, a 2H three-dimensional stacked synchronous dynamic random access memory, a 4H three-dimensional stacked synchronous dynamic random access memory, and an 8H three-dimensional stacked synchronous dynamic random access memory.
4. The hardware circuit for realizing DRAM capacity expansion according to claim 3, characterized in that: When the synchronous dynamic random access memory is a single-chip packaged dynamic random access memory, all the sockets are not loaded.
5. The hardware circuit for realizing DRAM capacity expansion according to claim 3, characterized in that: When the synchronous dynamic random access memory is a dual-chip package dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin and the second clock enable pin, and the first function configuration input pin is electrically connected to the second clock enable pin; a zero-ohm resistor is inserted into the socket connecting the second function configuration input pin and the second chip select pin, and the second function configuration input pin is electrically connected to the second chip select pin; a zero-ohm resistor is inserted into the socket connecting the third function configuration input pin and the second internal termination pin, and the third function configuration input pin is electrically connected to the second internal termination pin.
6. The hardware circuit for realizing DRAM capacity expansion according to claim 3, characterized in that: When the synchronous dynamic random access memory is a 2H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin and the first selection pin, the first function configuration input pin is electrically connected to the first selection pin, and the remaining sockets are not connected.
7. The hardware circuit for realizing DRAM capacity expansion according to claim 3, characterized in that: When the synchronous dynamic random access memory is a 4H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin and the first selection pin, and the first function configuration input pin is electrically connected to the first selection pin; a zero-ohm resistor is inserted into the socket connecting the second function configuration input pin and the second selection pin, and the second function configuration input pin is electrically connected to the second selection pin, and the remaining sockets are not loaded.
8. The hardware circuit for realizing DRAM capacity expansion according to claim 3, characterized in that: When the synchronous dynamic random access memory is an 8H three-dimensional stacked synchronous dynamic random access memory, a zero-ohm resistor is inserted into the socket connecting the first function configuration input pin and the first selection pin, and the first function configuration input pin is electrically connected to the first selection pin; a zero-ohm resistor is inserted into the socket connecting the second function configuration input pin and the second selection pin, and the second function configuration input pin is electrically connected to the second selection pin; a zero-ohm resistor is inserted into the socket connecting the third function configuration input pin and the third selection pin, and the third function configuration input pin is electrically connected to the third selection pin, and the remaining sockets are not loaded.
9. A solid state hard disk, characterized in that: The invention comprises a hardware circuit for realizing DRAM capacity expansion as described in any one of claims 1 to 8.
10. The solid state drive according to claim 9, characterized in that: The solid state hard disk also includes a mainboard, the hardware circuit is arranged on the mainboard, and a storage connector is also arranged on the mainboard; the synchronous dynamic random access memory is arranged on the storage connector and connected to the main controller through the storage connector.