Three-power-supply switching circuit
By designing a three-power switching circuit including transistors, PMOS tubes, NMOS tubes and diodes, the existing technology can only adapt to the voltage drop problem when two sets of different power supplies and external power supply is achieved, and flexible switching of three sets of different power supplies and low voltage drop external power supply is achieved.
Patent Information
- Application Number
- CN202420235586.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-31
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2034-01-31
AI Technical Summary
The existing technology can only adapt to two different sets of power supply, and there is a voltage drop when external power supply is supplied, which has great limitations.
A three-power switching circuit is designed, using components such as transistors, PMOS tubes, NMOS tubes and diodes. Through reasonable circuit structure design, it can be suitable for three different groups of power supply, and there is almost no voltage drop when externally supplied.
It realizes flexible switching of three different power groups, and has almost no voltage drop when external power supply, which improves the practicality and applicability of the circuit.
Smart Images
Figure CN222814270U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a switching circuit, in particular to a three-power supply switching circuit. Background Art
[0002] In recent years, electronic products from all walks of life, such as artificial intelligence, instrumentation, industrial automation, and new energy, are almost inseparable from power supply. There are many power supply solutions in actual product design. Here, taking general microcontroller products as an example, the system with a power supply of about 3.3V is commonly powered by USB, external power adapter, and battery.
[0003] When designing a product, in order to make the product more stable and intelligent, two or even more power supply methods are usually reserved. Generally, each power supply can power the product alone.
[0004] Many existing products use single power or dual power switching, generally an external power supply plus an internal battery, and the external power supply has a higher priority than the internal battery. When there is a battery, the battery powers the system, and when there is an external power supply, the external power supply powers the system. Sometimes, the external power supply powers the system and also charges the battery. If the external power supply is accidentally cut off, the internal battery will continue to supply power.
[0005] like Figure 1 As shown, when VUSB has power, PMOS tube Q1 is turned off. Even if body diode current flows through it, because VUSB is higher than Vbat voltage, PMOS's Vgs>0, so PMOS body diode is turned off and the load is powered by VUSB; when VUSB has no power, PMOS is turned on and the load is powered by VBat.
[0006] The disadvantages of the above prior art are as follows:
[0007] 1. It can only adapt to 2 groups of different power supplies, which has certain limitations;
[0008] 2. There is a voltage drop when the external power supply is supplied, at least 0.3V. Utility Model Content
[0009] In view of the deficiencies in the prior art, the utility model aims to provide a three-power switching circuit with a reasonable circuit structure design, which can be applied to three groups of different power supplies, has almost no voltage drop when powered externally, and is highly practical.
[0010] In order to achieve the above-mentioned purpose, the utility model is realized by the following technical scheme: a three-power switching circuit, including a transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, an NMOS transistor, a first diode, a second diode, a third diode and a fourth diode, a first input terminal VIN1 is connected to the drain of the first PMOS transistor, a gate of the first PMOS transistor is respectively connected to the drain of the NMOS transistor, the gate of the second PMOS transistor and one end of the fourth resistor, a source of the first PMOS transistor is respectively connected to one end of the first resistor, the other end of the fourth resistor, and the source of the second PMOS transistor, a distribution table at the other end of the first resistor is connected to one end of the third resistor, the collector of the transistor, and the gate of the NMOS transistor, and the emitter of the transistor, the third diode and the emitter of the third diode are connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor and the fourth resistor. The other end of the resistor and the source of the NMOS tube are grounded, the base of the transistor is respectively connected to the cathode of the first diode and the cathode of the second diode through the fifth resistor, the anode of the first diode is connected to the third input terminal VIN3, the anode of the second diode is connected to the second input terminal VIN2, the drain of the second PMOS tube is respectively connected to the cathode of the third diode, the cathode of the fourth diode, the anode of the capacitor and the output terminal VOUT, the cathode of the capacitor is grounded, the anode of the fourth diode is connected to the drain of the third PMOS tube, the source of the third PMOS tube is connected to the second input terminal VIN2, the gate of the third PMOS tube is respectively connected to one end of the second resistor and one end of the sixth resistor, the other end of the second resistor and the anode of the third diode are both connected to the third input terminal VIN3, and the other end of the sixth resistor is grounded.
[0011] The resistance of the second resistor and the sixth resistor of the utility model cannot be too small, otherwise it will increase the static power consumption. Generally, it is several hundred K. The resistance of the second resistor and the sixth resistor is selected according to the threshold voltage of the third PMOS tube. VIN1, VIN2, and VIN3 are three groups of power supplies with different voltages, and VOUT is the output to power the system. There is no strict priority for VOUT power supply. A single group of power supplies can be independently powered. If there is a battery power supply, the battery voltage is preferentially connected to the position of VIN1. This voltage has basically no voltage drop. When there are external VIN1 and VIN2, VIN2 will be used for power supply; when there are VIN1 and VIN3, VIN3 will be used for power supply; when there are external VIN2 and VIN3, VIN3 will be used for power supply; when there are external VIN1, VIN2, and VIN3, VIN3 will be used for power supply.
[0012] Beneficial effects of the utility model: the circuit structure of the utility model is reasonably designed, can be applied to three groups of different power supplies, has almost no voltage drop when external power supply is used, and has strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The utility model is described in detail below with reference to the accompanying drawings and specific implementation methods;
[0014] Figure 1It is a structural schematic diagram of the background technology of the utility model;
[0015] Figure 2 A circuit diagram of the utility model;
[0016] Figure 3 This is the application circuit diagram of the utility model. DETAILED DESCRIPTION
[0017] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below in conjunction with specific implementation methods.
[0018] Reference Figure 2 The present specific implementation adopts the following technical scheme: a three-power switching circuit, including a transistor Q1, a first PMOS transistor Q2, a second PMOS transistor Q3, a third PMOS transistor Q4, an NMOS transistor Q5, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4, a first input terminal VIN1 is connected to the drain of the first PMOS transistor Q2, a gate of the first PMOS transistor Q2 is respectively connected to the drain of the NMOS transistor Q5, the gate of the second PMOS transistor Q3 and one end of the fourth resistor R4, a source of the first PMOS transistor Q2 is respectively connected to one end of the first resistor R1, the other end of the fourth resistor R4 and the source of the second PMOS transistor Q3, the other end of the first resistor R1 is connected to one end of the third resistor R3, the collector of the transistor Q1 and the gate of the NMOS transistor Q5, the emitter of the transistor Q1, the other end of the third resistor R3 The first input terminal VIN3 and the second input terminal VIN2 are connected to the positive electrode of the first diode D1 and the positive electrode of the second diode D2 respectively. The drain of the second PMOS tube Q3 is connected to the negative electrode of the third diode D3, the negative electrode of the fourth diode D4, the positive electrode of the capacitor C1 and the output terminal VOUT respectively. The negative electrode of the capacitor C1 is grounded. The positive electrode of the fourth diode D4 is connected to the drain of the third PMOS tube Q4. The source of the third PMOS tube Q4 is connected to the second input terminal VIN2. The gate of the third PMOS tube Q4 is connected to one end of the second resistor R2 and one end of the sixth resistor R6 respectively. The other end of the second resistor R2 and the positive electrode of the third diode D3 are connected to the third input terminal VIN3. The other end of the sixth resistor R6 is grounded.
[0019] The working principle of this specific implementation method:
[0020] 1. When there is only VIN1, the voltage passes through the body diode of the first PMOS tube Q2, and is divided by the first resistor R1 and the third resistor R3. The base of the NMOS tube Q5 is at a high level, and the NMOS tube Q5 is turned on, pulling down the gate (G pole) of the first PMOS tube Q2 and the second PMOS tube Q3. The first PMOS tube Q2 and the second PMOS tube Q3 are turned on, and VIN1 supplies power to VOUT through the first PMOS tube Q2 and the second PMOS tube Q3. Due to the presence of the third diode D3 and the fourth diode D4, the voltage can be prevented from flowing back to VIN2 and VIN3.
[0021] 2. When there is only VIN2, due to the existence of the sixth resistor R6, the gate (G pole) of the third PMOS tube Q4 is pulled down, the third PMOS tube Q4 is turned on, and VIN2 supplies power to VOUT through the third PMOS tube Q4 and D4. Due to the existence of D3, the voltage can be prevented from flowing back to VIN3;
[0022] 3. When only VIN3 is present, the power supply supplies power to VOUT through D3. Due to the presence of the fourth diode D4, the voltage can be prevented from flowing back to VIN2. VIN3 provides base current to transistor Q1 through the first diode D1 and the fifth resistor R5. Transistor Q1 is turned on, NMOS transistor Q5 is not turned on, and the gates (G) of the first PMOS transistor Q2 and the second PMOS transistor Q3 are pulled up through R4. The first PMOS transistor Q2 and the second PMOS transistor Q3 are not turned on, and VOUT will not flow back to VIN1.
[0023] 4. When VIN2 and VIN1 exist at the same time, the third PMOS tube Q4 is turned on, and VOOUT is powered through D4. VIN2 provides current to the base of Q1 through the second diode D2 and the fifth resistor R5. The transistor Q1 is turned on, and the gate (G pole) of the NMOS tube Q5 is pulled down. The NMOS tube Q5 is not turned on. The gate (G pole) of the first PMOS tube Q2 and the second PMOS tube Q3 is pulled up through the fourth resistor R4 and is not turned on. VOUT will not flow back to VIN1.
[0024] 5. When VIN3 and VIN2 exist at the same time, transistor Q1 is turned on, and the first PMOS tube Q2, the second PMOS tube Q3 and the NMOS tube Q5 are turned off to prevent VOUT from flowing back to VIN1. VIN3 pulls up the gate (G) of the third PMOS tube Q4 through R2 and R6, and the third PMOS tube Q4 is not turned on. VIN3 supplies power to VOUT through D3. Due to the existence of D4, VOUT can be prevented from flowing back to VIN2.
[0025] 6. When VIN3 and VIN1 exist at the same time, the transistor Q1 is turned on, the first PMOS tube Q2, the second PMOS tube Q3 and the NMOS tube Q5 are turned off, the third PMOS tube Q4 is turned off, and VIN3 supplies power to VOUT through the third diode D3.
[0026] 7. When VIN1, VIN2 and VIN3 exist at the same time, refer to 4&5&6, VOUT draws power from VIN3.
[0027] Example 1: Figure 3 As shown, an application circuit of an embodiment of the present invention has the following principles:
[0028] 1. When there is only VIN-BAT, the voltage passes through the body diode of the first PMOS tube Q2, and is divided by the first resistor R1 and the third resistor R3. The base of the NMOS tube Q5 is at a high level, and the NMOS tube Q5 is turned on, pulling down the gate (G pole) of the first PMOS tube Q2 and the second PMOS tube Q3. The first PMOS tube Q2 and the second PMOS tube Q3 are turned on, and VOUT draws power from VIN-BAT. Due to the presence of the third diode D3 and the fourth diode D4, the voltage can be prevented from flowing back to 5V and 12V.
[0029] 2. When there is only 5V, due to the existence of the sixth resistor R6, the gate (G pole) of the third PMOS tube Q4 is pulled down, the third PMOS tube Q4 is turned on, and 5V supplies power to VOUT through the third PMOS tube Q4 and the fourth diode D4.
[0030] 3. When there is only 12V, the power supply supplies power to VOUT through D3. Due to the existence of D4, the voltage can be prevented from flowing back to 5V. 12V provides base current to transistor Q1 through the first diode D1 and the fifth resistor R5. Transistor Q1 is turned on, NMOS tube Q5 is not turned on, and the gates (G) of the first MOS tube Q2 and the second MOS tube Q3 are pulled up through resistor R4. The first MOS tube Q2 and the second MOS tube Q3 are not turned on, and VOUT will not flow back to VIN-BAT.
[0031] 4. When 5V and VIN-BAT exist at the same time, the third PMOS tube Q4 is turned on, and VOOUT is powered through D4. 5V provides current to the base of the transistor Q1 through the second diode D2 and the fifth resistor R5. The transistor Q1 is turned on, and the gate (G pole) of the NMOS tube Q5 is pulled down. The NMOS tube Q5 is not turned on. The gate (G pole) of the first MOS tube Q2 and the second MOS tube Q3 is pulled up through the fourth resistor R4 and is not turned on. VOUT will not flow back to VIN-BAT.
[0032] 5. When 12V and 5V exist at the same time, transistor Q1 is turned on, and the first PMOS tube Q2, the second PMOS tube Q3 and the NMOS tube Q5 are turned off; 12V will pull up the gate (G) of the third PMOS tube Q4, and the third PMOS tube Q4 will not be turned on. 12V supplies power to VOUT through the third diode D3.
[0033] 6. When 12V and VIN-BAT exist at the same time, transistor Q1 is turned on, the first PMOS tube Q2, the second PMOS tube Q3 and the NMOS tube Q5 are turned off, the third PMOS tube Q4 is turned off, and 12V supplies power to VOUT through the third diode D3.
[0034] 7. When VIN-BAT, 5V and 12V exist at the same time, refer to 4&5&6, VOUT draws power from 12V.
[0035] 8. When VIN-BAT is used for power supply, since the first MOS tube Q2 and the second MOS tube Q3 are turned on, there is basically no voltage drop when supplying power to the external power supply.
[0036] The above shows and describes the basic principle and main features of the utility model and the advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only for explaining the principle of the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection claimed by the utility model is defined by the attached claims and their equivalents.
Claims
1. A three-power switching circuit, characterized in that: The invention comprises a transistor (Q1), a first PMOS transistor (Q2), a second PMOS transistor (Q3), a third PMOS transistor (Q4), an NMOS transistor (Q5), a first diode (D1), a second diode (D2), a third diode (D3) and a fourth diode (D4); a first input terminal VIN1 is connected to the drain of the first PMOS transistor (Q2); a gate of the first PMOS transistor (Q2) is respectively connected to the drain of the NMOS transistor (Q5), the gate of the second PMOS transistor (Q3) and one end of a fourth resistor (R4); a source of the first PMOS transistor (Q2) is respectively connected to one end of the first resistor (R1), the other end of the fourth resistor (R4) and the source of the second PMOS transistor (Q3); the other end of the first resistor (R1) is connected to one end of the third resistor (R3), the collector of the transistor (Q1) and the gate of the NMOS transistor (Q5); an emitter of the transistor (Q1), the other end of the third resistor (R3) and the gate of the NMOS transistor (Q5); The source of the transistor (Q5) is grounded, the base of the transistor (Q1) is respectively connected to the cathode of the first diode (D1) and the cathode of the second diode (D2) through the fifth resistor (R5), the anode of the first diode (D1) is connected to the third input terminal VIN3, the anode of the second diode (D2) is connected to the second input terminal VIN2, the drain of the second PMOS transistor (Q3) is respectively connected to the cathode of the third diode (D3), the cathode of the fourth diode (D4), the anode of the capacitor C1 and the output terminal VOUT, the cathode of the capacitor C1 is grounded, the anode of the fourth diode (D4) is connected to the drain of the third PMOS transistor (Q4), the source of the third PMOS transistor (Q4) is connected to the second input terminal VIN2, the gate of the third PMOS transistor (Q4) is respectively connected to one end of the second resistor (R2) and one end of the sixth resistor (R6), the other end of the second resistor (R2) and the anode of the third diode (D3) are both connected to the third input terminal VIN3, and the other end of the sixth resistor (R6) is grounded.