Clock signal generation circuit, system, chip and electronic equipment

Abstract

The utility model provides a clock signal generation circuit and system, a chip and electronic equipment. The clock signal generation circuit comprises a current mirror module; the switched capacitor module is connected with the first mirror image branch; the resistor module is connected with the second mirror image branch; the voltage-controlled oscillation module is connected with the second mirror image branch; wherein the second mirror current changes along with the first mirror current, and the voltage-controlled oscillation module is connected with the switched capacitor module so as to control the switched capacitor module based on clock signal feedback. The current mirror module, the switched capacitor module and the voltage-controlled oscillation module form a loop, and the switched capacitor module serves as a negative feedback module to control the magnitude of the control voltage output by the current mirror module, so that the voltage-controlled oscillation module can output a clock signal of a target frequency through negative feedback; a comparator does not need to participate in the process of generating the clock signal, and finally the influence of the delay of the comparator on the frequency precision of the oscillating circuit can be avoided.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a clock signal generating circuit, system, chip and electronic device. Background Art

[0002] At present, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. The output frequency of the RC oscillator is determined based on the time constant of the resistor R and the capacitor C. In circuits of on-chip systems that do not require high clock source accuracy and frequency, RC oscillators are widely used due to their low cost, fast circuit startup, and easy on-chip integration.

[0003] However, during the operation of the RC oscillator, a comparator is required to compare the reference voltage with the voltage during the capacitor charging and discharging process. The delay of the comparator will seriously deteriorate the frequency drift of the RC oscillator, which leads to the problem of reduced output frequency accuracy of the RC oscillator. Utility Model Content

[0004] In view of the above problems, the embodiments of the present application provide a clock signal generating circuit, system, chip and electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a clock signal generating circuit, comprising:

[0006] A current mirror module, the current mirror module comprising a first mirror branch for outputting a first mirror current and a second mirror branch for outputting a second mirror current;

[0007] A switch capacitor module, the switch capacitor module is connected to the first mirror branch so that the first mirror current flows through the switch capacitor module;

[0008] A resistor module, the resistor module is connected to the second mirror branch so that the second mirror current flows through the resistor module and generates a control voltage in the second mirror branch;

[0009] A voltage-controlled oscillation module, the voltage-controlled oscillation module is connected to the second mirror branch to oscillate under the control of a control voltage and output a clock signal;

[0010] The second mirror current follows the change of the first mirror current, and the voltage-controlled oscillation module is connected to the switch capacitor module to control the switch capacitor module based on clock signal feedback.

[0011] In a second aspect, the present application provides a clock signal generating system, comprising:

[0012] The clock signal generating circuit as described in the first aspect;

[0013] The first voltage generating circuit is used for generating a first preset voltage. The first voltage generating circuit is connected to the clock signal generating circuit to supply power to the clock signal generating circuit.

[0014] In a third aspect, the present application provides a chip comprising the clock signal generating circuit as described in the first aspect.

[0015] In a fourth aspect, the present application provides an electronic device comprising the chip as described in the second aspect.

[0016] The present application receives the first mirror current output by the first mirror branch through the switch capacitor module, and receives the second mirror current output by the second mirror branch through the resistor module to generate a control voltage, so that the voltage-controlled oscillation module can oscillate and output a clock signal under the control of the control voltage. Since the clock signal output by the voltage-controlled oscillation module can be fed back to control the switch capacitor module, the magnitude of the first mirror current flowing through the switch capacitor module can be changed before the output clock frequency of the voltage-controlled oscillation module is stable. For example, when the clock signal is lower than the target frequency, the first mirror current, the second mirror current and the control voltage increase accordingly, so that the voltage-controlled oscillation module accelerates the oscillation, and finally the frequency of the clock signal approaches the target frequency; conversely, when the clock signal is higher than the target frequency, the first mirror current, the second mirror current and the control voltage decrease accordingly, so that the voltage-controlled oscillation module reduces the oscillation frequency, and finally the frequency of the clock signal approaches the target frequency.

[0017] That is to say, the present application forms a loop through a current mirror module, a switching capacitor module and a voltage-controlled oscillation module. The switching capacitor module acts as a negative feedback module to control the size of the control voltage output by the current mirror module, so that the voltage-controlled oscillation module can output a clock signal of the target frequency through negative feedback. The process of generating the clock signal does not require the participation of a comparator, and ultimately the influence of the delay of the comparator on the frequency accuracy of the oscillation circuit can be avoided. At the same time, since the second mirror current flows through the resistor module and generates a control voltage in the second mirror branch, the control voltage generated by the second mirror branch has a smaller voltage fluctuation than that of the first mirror branch. After the clock signal output by the voltage-controlled oscillation module stabilizes, the control voltage with smaller voltage fluctuation is conducive to the voltage-controlled oscillation module outputting a clock signal with a stable frequency, thereby avoiding the phenomenon that the frequency of the clock signal output by the voltage-controlled oscillation module is sometimes fast and sometimes slow due to large fluctuations in the control voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A circuit diagram of an RC oscillator in the related art is shown.

[0020] Figure 2 A schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0021] Figure 3 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0022] Figure 4 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0023] Figure 5 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0024] Figure 6 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0025] Figure 7 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0026] Figure 8 A schematic diagram of the first capacitor in an embodiment of the present application is shown.

[0027] Fig. 9 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0028] Fig.10 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0029] Fig.11 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0030] Fig.12 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0031] Fig.13 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0032] Fig.14 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0033] Fig.15 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0034] Fig.16Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0035] Fig.17 A simulation schematic diagram of a clock signal output by a clock signal generating circuit in an embodiment of the present application is shown.

[0036] Fig.18 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0037] Fig.19 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0038] Fig. 20 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0039] Fig.21 A schematic diagram of a clock signal generating system in an embodiment of the present application is shown.

[0040] Fig. 22 Another schematic diagram of a clock signal generating system in an embodiment of the present application is shown.

[0041] Fig.23 Another schematic diagram of a clock signal generating system in an embodiment of the present application is shown.

[0042] Among them, 10 is a current mirror module, 11 is a first mirror branch, 12 is a second mirror branch, 20 is a switch capacitor module, 30 is a resistor module, 40 is a voltage-controlled oscillator module, 41 is a voltage-controlled oscillator, 42 is a non-overlapping clock generation module, 43 is a level conversion module, 50 is a counter, 60 is a frequency divider, 70 is a logic module, and 80 is a delay module;

[0043] 100 clock signal generating circuit, 200 first voltage generating circuit, 300 second voltage generating circuit, 400 bandgap reference source, 500 control module;

[0044] A first mirror current I1, a second mirror current I2, a control voltage Vc, a clock signal CLK, a first clock signal CLKA, a second clock signal CLKB, a power supply terminal VDD, and a ground terminal GND;

[0045] A first capacitor C1, a first switch S1, a second capacitor C2, a second switch S2, a first sub-capacitor C01, and a first sub-switch S01;

[0046] A first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a third capacitor C3, a fourth capacitor C4, a first resistor R1, and a third switch S3. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0048] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0049] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0050] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0051] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0052] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0053] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0054] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0055] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0056] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0057] At present, the RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. Figure 1 , Figure 1 A circuit diagram of an RC oscillator in the related art is shown, where the RC oscillator includes a comparator COMP1, a comparator COMP2, a logic circuit composed of two NAND gates, a capacitor Cx, a capacitor Cy, a transistor MN1 for controlling the charging and discharging of the capacitor Cx, and a transistor MN2 for controlling the charging and discharging of the capacitor Cy.

[0058] During the operation of the RC oscillator, the two NAND gates control the alternating charging of capacitors Cx and Cy through control signals OUT1, OUT2, transistors MN1, and transistor MN2 respectively. When the output voltages IN1 and IN2 of capacitors Cx and Cy exceed the reference voltage Vref, one of capacitors Cx and Cy is switched to charge and the other is discharged, so that the output ends of comparators COMP1 and COMP2 output clock signals that alternate between high and low levels.

[0059] In an ideal case where loop delay (such as comparator delay) is not considered, the capacitor Cx\Cy is charged to the reference voltage Vref for half a cycle of the clock signal. It can be seen that the oscillation frequency f of the output clock signal is:

[0060] f=N / 2RC

[0061] Wherein, N is the ratio of the charging current NIref of the capacitor Cx\Cy to the reference current Iref, R is the resistor corresponding to the reference voltage Vref, and C is the capacitance value of the capacitor Cx\Cy.

[0062] In the actual case of considering the comparator delay, the oscillation frequency f of the output clock signal is:

[0063] f=N / 2(RC+t)

[0064] Where t is the time corresponding to the comparator delay.

[0065] It can be seen that since the RC oscillator needs to compare the reference voltage with the voltage during the charging and discharging process of the capacitor through a comparator during operation, the delay of the comparator will seriously worsen the frequency drift of the RC oscillator, which leads to the problem of reduced output frequency accuracy of the RC oscillator.

[0066] To this end, the present application provides a clock signal generating circuit, system, chip and electronic device, which are described in detail below.

[0067] First, see Figure 2 , Figure 2 A schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown, wherein the clock signal generating circuit includes a current mirror module 10 , a switch capacitor module 20 , a resistor module 30 and a voltage-controlled oscillator module 40 .

[0068] Specifically, the current mirror module 10 includes a first mirror branch 11 for outputting a first mirror current I1 and a second mirror branch 12 for outputting a second mirror current I2, so as to input the first mirror current I1 to the switch capacitor module 20 and input the second mirror current I2 to the resistor module 30. The second mirror current I2 can change with the first mirror current I1, for example, when the first mirror current I1 increases, the second mirror current I2 will increase almost synchronously / proportionally with the first mirror current I1; for another example, when the first mirror current I1 decreases, the second mirror current I2 will decrease almost synchronously / proportionally with the first mirror current I1.

[0069] Exemplarily, the current mirror module 10 may include but is not limited to a simple current mirror, a cascode current mirror, a low-voltage cascode current mirror, a low-voltage cascode current mirror, a high-compliance regulated output cascode current mirror, a high-compliance regulated input cascode current mirror, a bipolar current mirror, etc.

[0070] The switch capacitor module 20 is connected to the first mirror branch 11 so that the first mirror current I1 flows through the switch capacitor module 20, wherein the switching frequency of the switch capacitor module 20 determines the magnitude of the current flowing through the switch capacitor module 20. In some embodiments of the present application, the switching frequency of the switch capacitor module 20 is positively correlated with the first mirror current I1. For example, the switch capacitor module 20 includes at least one switch and at least one capacitor, one plate of the capacitor is connected to the first mirror branch 11, the other plate of the capacitor is grounded, and the two ends of the switch are respectively connected to the two plates of the capacitor. When the switch is closed, the first mirror current I1 can flow normally into the ground terminal, and when the switch is disconnected, the first mirror current I1 charges the capacitor. Therefore, according to the characteristics of the capacitor passing AC and blocking DC, the higher the switching frequency, the larger the first mirror current I1; conversely, the lower the switching frequency, the smaller the first mirror current I1.

[0071] In some other embodiments of the present application, the switching frequency of the switching capacitor module 20 is negatively correlated with the first mirror current I1. For example, the switching capacitor module 20 includes at least one switch and at least one inductor. When the switch is closed, the first mirror current I1 can flow normally through the switch into the ground terminal GND, and when the switch is open, the first mirror current I1 flows into the ground terminal GND through the inductor. Therefore, according to the characteristic of the inductor that the inductor passes alternating current and blocks direct current, the higher the switching frequency, the smaller the first mirror current I1; conversely, the lower the switching frequency, the larger the first mirror current I1.

[0072] The resistor module 30 is connected to the second mirror branch 12 so that the second mirror current I2 flows through the resistor module 30 and generates a control voltage Vc in the second mirror branch 12. For example, the control voltage Vc can be generated at the first end of the second mirror branch 12 outputting the second mirror current I2; for another example, the control voltage Vc can be generated at any circuit node in the second mirror branch 12. In some embodiments of the present application, the resistor module 30 may include a polysilicon resistor. In some embodiments of the present application, the resistor module 30 may include a transistor resistor, such as a diode or a diode resistor formed by short-circuiting the drain and gate of a MOS tube.

[0073] It should be noted that, since the second mirror current I2 can follow the change of the first mirror current I1, according to the voltage calculation formula, the magnitude of the control voltage Vc actually follows the change of the first mirror current I1. For example, for the embodiment in which the switching frequency of the switch capacitor module 20 is negatively correlated with the first mirror current I1, the higher the switching frequency, the smaller the control voltage Vc; conversely, the lower the switching frequency, the larger the control voltage Vc; for another example, for the embodiment in which the switching frequency of the switch capacitor module 20 is positively correlated with the first mirror current I1, the higher the switching frequency, the larger the control voltage Vc; conversely, the lower the switching frequency, the smaller the control voltage Vc.

[0074] The voltage controlled oscillator module 40 is connected to the second mirror branch 12, so that the voltage controlled oscillator module 40 is connected to the control voltage Vc and oscillates under the control of the control voltage Vc to output the clock signal CLK. The frequency of the clock signal CLK output by the voltage controlled oscillator module 40 is controlled by the magnitude of the control voltage Vc. In some embodiments of the present application, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 40 is positively correlated with the magnitude of the control voltage Vc. For example, for an embodiment in which the switching frequency of the switch capacitor module 20 is negatively correlated with the first mirror current I1, the voltage-controlled oscillation module 40 includes a voltage-controlled oscillator 41, and the control voltage Vc directly controls the voltage-controlled oscillator 41 to output the clock signal CLK. When the control voltage Vc is too large and the frequency of the output clock signal CLK is too high, the first mirror current I1, the second mirror current I2 and the control voltage Vc will be reduced, thereby reducing the frequency of the output clock signal CLK, thereby achieving feedback regulation to balance the frequency of the clock signal CLK to the target frequency; conversely, when the control voltage Vc is too small and the frequency of the output clock signal CLK is too small, the first mirror current I1, the second mirror current I2 and the control voltage Vc will be increased, thereby achieving feedback regulation to balance the frequency of the clock signal CLK to the target frequency.

[0075] In some embodiments of the present application, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 40 is negatively correlated with the magnitude of the control voltage Vc. For example, for an embodiment in which the switching frequency of the switch capacitor module 20 is positively correlated with the first mirror current I1, when the voltage-controlled oscillation module 40 includes an inverting amplifier and a voltage-controlled oscillator (or when the transistor controlling the input of the voltage-controlled oscillator is a PMOS tube), the control voltage Vc controls the voltage-controlled oscillator to output the clock signal CLK through the voltage signal output by the inverting amplifier. When the control voltage Vc is too large, the voltage signal output by the inverting amplifier is too small, resulting in the output clock signal CLK being too large. When the frequency is too low, the first mirror current I1, the second mirror current I2 and the control voltage Vc will be reduced, thereby increasing the frequency of the output clock signal CLK, thereby achieving feedback regulation to balance the frequency of the clock signal CLK to the target frequency; conversely, when the control voltage Vc is too small, the voltage signal output by the inverting amplifier is too large, resulting in an excessively large frequency of the output clock signal CLK, the first mirror current I1, the second mirror current I2 and the control voltage Vc will be increased, thereby reducing the frequency of the output clock signal CLK, thereby achieving feedback regulation to balance the frequency of the clock signal CLK to the target frequency.

[0076] Exemplarily, the voltage-controlled oscillator module 40 may include but is not limited to a harmonic oscillator or a relaxation oscillator, wherein the harmonic oscillator is such as an LC crystal oscillator and a crystal oscillator, and the relaxation oscillator is such as a delay-based ring voltage-controlled oscillator, a grounded capacitor-based voltage-controlled oscillator, and an emitter-coupled voltage-controlled oscillator.

[0077] In the embodiment of the present application, the present application receives the first mirror current I1 output by the first mirror branch 11 through the switch capacitor module 20, and receives the second mirror current I2 output by the second mirror branch 12 through the resistor module 30 to generate a control voltage Vc, so that the voltage-controlled oscillation module 40 can oscillate and output the clock signal CLK under the control of the control voltage Vc. Since the clock signal CLK output by the voltage-controlled oscillation module 40 can feedback control the switch capacitor module 20, the magnitude of the first mirror current I1 flowing through the switch capacitor module 20 can be changed before the output clock frequency of the voltage-controlled oscillation module is stable. For example, when the clock signal CLK is lower than the target frequency, the first mirror current I1, the second mirror current I2 and the control voltage Vc change accordingly, so that the voltage-controlled oscillation module 40 accelerates the oscillation, and finally the frequency of the clock signal CLK approaches the target frequency; for another example, when the clock signal CLK is higher than the target frequency, the first mirror current I1, the second mirror current I2 and the control voltage Vc change accordingly, so that the voltage-controlled oscillation module 40 reduces the oscillation frequency, and finally the frequency of the clock signal CLK approaches the target frequency.

[0078] That is to say, the present application forms a loop through the current mirror module 10, the switch capacitor module 20 and the voltage-controlled oscillation module 40. The switch capacitor module 20 acts as a negative feedback module to control the size of the control voltage Vc output by the current mirror module 10, so that the voltage-controlled oscillation module 40 can output the clock signal CLK of the target frequency through negative feedback. The process of generating the clock signal CLK does not require the participation of the comparator, and ultimately the delay of the comparator can be avoided from affecting the frequency accuracy of the oscillation circuit. At the same time, since the second mirror current I2 flows through the resistor module 30 and generates the control voltage Vc in the second mirror branch 12, the control voltage Vc generated by the second mirror branch 12 has a smaller voltage fluctuation than that of the first mirror branch 11. After the clock signal CLK output by the voltage-controlled oscillation module 40 is stable, the control voltage Vc with smaller voltage fluctuation is conducive to the voltage-controlled oscillation module 40 outputting a clock signal CLK with a stable frequency, thereby avoiding the phenomenon that the frequency of the clock signal CLK output by the voltage-controlled oscillation module 40 is sometimes fast and sometimes slow due to large fluctuations in the control voltage Vc.

[0079] In some embodiments of the present application, after the clock signal CLK reaches the target frequency, the first mirror current I1 flowing through the switch capacitor module 20 is equal to the second mirror current I2 flowing through the resistor module 30, that is, the mirror ratio of the current mirror module 10 can be 1:1. In some embodiments of the present application, after the clock signal CLK reaches the target frequency, the first mirror current I1 flowing through the switch capacitor module 20 is N times the second mirror current I2 flowing through the resistor module 30, that is, the mirror ratio of the current mirror module 10 can be 1:N, and before the clock signal CLK reaches the target frequency, the second mirror current I2 has a larger change amplitude than the first mirror current I1, so it is beneficial to shorten the time taken by the voltage-controlled oscillation module 40 from starting oscillation to outputting a stable clock signal CLK, so as to improve the response speed of the system.

[0080] In some embodiments of the present application, for example, for an embodiment in which the switch capacitor module 20 includes at least one switch and at least one capacitor, see Figure 3 , Figure 3 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the clock signal CLK includes a first clock signal CLKA and a second clock signal CLKB that do not overlap each other, and the switch capacitor module 20 includes a first capacitor C1, a first switch S1 and a second switch S2; the first end of the first switch S1 is connected to the first mirror branch 11, the second end of the first switch S1 is connected to the first plate of the first capacitor C1, and the second plate of the first capacitor C1 is connected to the ground terminal GND; the first end of the second switch S2 is connected to the first plate of the first capacitor C1, and the second end of the second switch S2 is connected to the ground terminal GND; wherein the control end of the first switch S1 is connected to the voltage-controlled oscillation module 40 to access the first clock signal CLKA, and the control end of the second switch S2 is connected to the voltage-controlled oscillation module 40 to access the second clock signal CLKB.

[0081] It should be noted that the non-overlapping first clock signal CLKA and second clock signal CLKB make the first switch S1 and the second switch S2 not closed or opened at the same time. For example, when the first switch S1 is closed and the second switch S2 is opened, the first mirror current I1 charges the first capacitor C1; when the first switch S1 is opened and the second switch S2 is closed, the first capacitor C1 discharges and flows into the ground terminal GND. According to the calculation formula of the equivalent impedance of the switch capacitor, it can be known that the equivalent impedance R of the switch capacitor module 20 at this time is: R = 1 / fC, f is the frequency of the first clock signal CLKA and the second clock signal CLKB, and C is the capacitance value of the first capacitor C1. Therefore, it can be known that the voltage U1 at one end of the switch capacitor module 20 connected to the first mirror branch 11 is:

[0082] U1=I1 / fC

[0083] At the same time, the voltage U2 at one end of the resistor module 30 connected to the second mirror branch 12 is:

[0084] U2=I2*R0

[0085] Wherein, R0 is the resistance value corresponding to the resistance module 30 .

[0086] Taking the case where the first mirror current I1 and the second mirror current I2 are equal after the frequency of the output clock signal CLK reaches the target frequency as an example, since the voltage drop of the first mirror branch 11 of the current mirror module 10 is equal to the voltage drop at the output end of the second mirror branch 12, that is, U1=U2, it can be known that the target frequency f0 of the clock signal CLK satisfies the following relationship:

[0087] f0=1 / R0*C

[0088] It can be seen that by changing the resistance value R0 of the resistance module 30 and / or the capacitance value of the first capacitor C1 , the target frequency of the clock signal CLK output by the voltage-controlled oscillation module 40 can be changed.

[0089] In some embodiments of the present application, see Figure 4 , Figure 4 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the switch capacitor module 20 further includes a second capacitor C2; the first plate of the second capacitor C2 is connected to the first mirror branch 11, and the second plate of the second capacitor C2 is connected to the ground terminal GND. Specifically, the capacitance value of the second capacitor C2 is usually greater than the capacitance value of the first capacitor C1, so the second capacitor C2 can be used as a voltage stabilizing capacitor to stabilize the voltage of the first mirror branch 11, prevent the first mirror current I1 of the first mirror branch 11 from changing dramatically when the switch is switched, and thus avoid the phenomenon that the control voltage Vc fluctuates greatly due to the dramatic change of the current of the second mirror branch 12.

[0090] It is understandable that the implementation of the switch capacitor module 20 is not limited thereto. For example, see Figure 5 , Figure 5 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown. The second capacitor C2 can also be connected in series with the first capacitor C1. For another example, refer to Figure 6 , Figure 6 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown. Whether the first mirror current I1 flows through the first inductor L1 can also be controlled by the first switch S1, so that the magnitude of the first mirror current I1 is controlled by the frequency of the clock signal CLK.

[0091] In some embodiments of the present application, for example, in embodiments where the target frequency of the clock signal CLK can be changed by changing the capacitance value of the first capacitor C1, continue to refer to Figure 7 , Figure 7 FIG. shows another schematic diagram of the clock signal generation circuit in an embodiment of the present application. The first capacitor C1 includes a plurality of first sub-capacitors C01 and a plurality of first sub-switches S01. The first sub-capacitors C01 and the first sub-switches S01 are in one-to-one correspondence; the first plate of each first sub-capacitor C01 is connected to the first end of the corresponding first sub-switch S01, the second plate of each first sub-capacitor C01 is connected to the ground terminal GND, and the second end of each first sub-switch S01 is connected to the first node between the first switch S1 and the second switch S2. Specifically, the more the number of closed first sub-switches S01, the more the number of parallel first sub-capacitors C01, and thus the larger the capacitance value of the first capacitor C1; conversely, the fewer the number of closed first sub-switches S01, the fewer the number of parallel first sub-capacitors C01, and thus the larger the capacitance value of the first capacitor C1. Finally, by controlling the plurality of first sub-switches S01, the purpose of controlling the capacitance value of the first capacitor C1 and adjusting the frequency of the clock signal CLK can be achieved.

[0092] For example, before changing the capacitance value of the first capacitor C1, the voltage-controlled oscillation module 40 outputs a clock signal CLK with a frequency of f1. After increasing the capacitance value of the first capacitor C1, it will cause the first mirror current I1 flowing through the switched-capacitor module 20 to increase, thereby increasing the control voltage Vc and decreasing the oscillation frequency of the voltage-controlled oscillation module 40. Finally, the voltage-controlled oscillation module 40 outputs a clock signal CLK with a frequency of f2, where f2 < f1. Conversely, if the capacitance value of the first capacitor C1 is decreased, it will cause the first mirror current I1 flowing through the switched-capacitor module 20 to decrease, thereby decreasing the control voltage Vc and increasing the oscillation frequency of the voltage-controlled oscillation module 40. Finally, the voltage-controlled oscillation module 40 outputs a clock signal CLK with a frequency of f3, where f3 > f1.

[0093] In some embodiments of the present application, the capacitance values of at least some of the plurality of first sub-capacitors C01 increase sequentially. For example, refer to Figure 8 , Figure 8 FIG. shows a schematic diagram of the first capacitor C1 in an embodiment of the present application. Among them, the capacitance values of a part of the first sub-capacitors C01 increase sequentially as 1 pF, 2 pF... 2 n pF. The first sub-switches S01 of this part of the first sub-capacitors C01 are controlled by frequency encoding to facilitate matching the capacitance value of the first capacitor C1 with the target frequency; the capacitance values of another part of the first sub-capacitors C01 can be the same, and the first sub-switches S01 of this part of the first sub-capacitors C01 are controlled by temperature encoding to calibrate the capacitance value of the first capacitor C1 at different temperatures.

[0094] In some embodiments of the present application, see Fig. 9 , Fig. 9 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, wherein the first mirror branch 11 includes a first transistor M1, and the second mirror branch 12 includes a second transistor M2; the first end of the first transistor M1 is connected to the power supply terminal VDD, and the second end of the first transistor M1 is connected to the switch capacitor module 20; the first end of the second transistor M2 is connected to the power supply terminal VDD, and the second end of the second transistor M2 is connected to the resistor module 30; wherein the control end of the second transistor M2 is connected to the control end of the first transistor M1, and the control end of the first transistor M1 is connected to the second end of the first transistor M1.

[0095] It should be noted that, since the second end of the first transistor M1 is connected to the control end, the first transistor M1 works as a diode at this time. When the first mirror current I1 flowing through the switch capacitor module 20 changes, the control end voltage of the first transistor M1 and the control end voltage of the second transistor M2 will change almost synchronously, so that the second mirror current I2 flowing through the second transistor M2 follows the change of the first mirror current I1, so as to generate a corresponding control voltage Vc through the resistor module 30 through which the second mirror current I2 flows.

[0096] In some embodiments of the present application, see Fig.10 , Fig.10 Another schematic diagram of the clock signal generating circuit in the present application is shown, wherein the first mirror branch 11 further includes a third transistor M3, and the second mirror branch 12 further includes a fourth transistor M4; the first end of the third transistor M3 is connected to the second end of the first transistor M1, and the second end of the third transistor M3 is connected to the switch capacitor module 20; the first end of the fourth transistor M4 is connected to the second end of the second transistor M2, and the second end of the fourth transistor M4 is connected to the resistor module 30; wherein the control end of the first transistor M1 is connected to the second end of the third transistor M3, and the control end of the third transistor M3 and the control end of the fourth transistor M4 are connected to each other and connected to the first bias voltage. It should be noted that since the control end of the third transistor M3 and the control end of the fourth transistor M4 are connected to each other and connected to the first bias voltage, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 constitute a low-voltage cascode current mirror. Compared with the simple current mirror, the low-voltage cascode current mirror is conducive to ensuring that all transistors work in the saturation region and is conducive to ensuring the swing of the control voltage Vc.

[0097] In some embodiments of the present application, see Fig.11 , Fig.11Another schematic diagram of the clock signal generating circuit in the present application is shown, wherein the first mirror branch 11 further includes a fifth transistor M5, and the second mirror branch 12 further includes a sixth transistor M6; the first end of the fifth transistor M5 is connected to the second end of the third transistor M3, and the second end of the fifth transistor M5 is connected to the switch capacitor module 20; the first end of the sixth transistor M6 is connected to the second end of the fourth transistor M4, and the second end of the sixth transistor M6 is connected to the resistor module 30. It should be noted that, since the control ends of the fifth transistor M5 and the sixth transistor M6 are further connected to each other and connected to the second bias voltage, the fifth transistor M5 and the sixth transistor M6 can clamp the control voltage Vc, thereby reducing the fluctuation of the control voltage Vc after the clock signal CLK reaches the target frequency.

[0098] In some embodiments of the present application, see Fig.12 , Fig.12 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the first mirror branch 11 further includes a seventh transistor M7, and the second mirror branch 12 further includes an eighth transistor M8; the first end of the seventh transistor M7 is connected to the second end of the fifth transistor M5, and the second end of the seventh transistor M7 is connected to the switch capacitor module 20; the first end of the eighth transistor M8 is connected to the second end of the sixth transistor M6, and the second end of the eighth transistor M8 is connected to the resistor module 30; wherein the control end of the seventh transistor M7 and the control end of the eighth transistor M8 are connected to each other and connected to the third bias voltage. Similarly, since the control end of the seventh transistor M7 and the control end of the eighth transistor M8 are connected to each other and connected to the third bias voltage, the seventh transistor M7 and the eighth transistor M8 can clamp the control voltage Vc, thereby reducing the fluctuation of the control voltage Vc after the clock signal CLK reaches the target frequency.

[0099] As an exemplary embodiment of generating a bias voltage, see Fig.13 , Fig.13A schematic diagram of a bias voltage generating circuit in an embodiment of the present application is shown, wherein the bias voltage generating circuit includes transistors m1 to m22, a resistor r1, and a resistor array R Array and capacitor c2, after the power supply terminal VDD is powered on, the transistors m1 and m2 with drains and gates shorted pass current to increase the second bias voltage V2 and the fourth bias voltage V4, and the transistors m5, m6, m7, m8, m13, m14, m15, and m16 are turned on, and then the gate voltages of the transistors m9, m10, m11, and m12 are reduced and turned on to generate the fifth bias voltage V5 and the sixth bias voltage V6. After the second bias voltage V2, the fourth bias voltage V4, the fifth bias voltage V5, and the sixth bias voltage V6 meet the regulation, the transistors m17, m18, m19, m20, m21, and m22 are turned on to generate the first bias voltage V1 and the third bias voltage V3, and finally the first bias voltage V1, the second bias voltage V2, and the third bias voltage V3 can be used to control the current mirror module 10.

[0100] It should be noted that the above Fig.13 As only an exemplary embodiment of generating a bias voltage, those skilled in the art may also use other methods to generate a bias voltage, for example, a resistor divider circuit; Figures 9 to 12 FIG. 4 shows a node where the second mirror branch 12 outputs the control voltage Vc, but is not limited thereto. For example, Fig.11 , the control voltage Vc can also be output through the node between the second transistor M2 and the fourth transistor M4; for example, Fig.12 In the embodiment, the control voltage Vc can also be output through the node between the sixth transistor M6 and the eighth transistor M8.

[0101] In some embodiments of the present application, see Fig.14 , Fig.14 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the second mirror branch 12 also includes a third capacitor C3 and / or a fourth capacitor C4; the first plate of the third capacitor C3 is connected to the power supply terminal VDD, and the second plate of the third capacitor C3 is connected to the second end of the second transistor M2; the first plate of the fourth capacitor C4 is connected to the second end of the second transistor M2, and the second plate of the fourth capacitor C4 is connected to the ground terminal GND. Specifically, the third capacitor C3 and the fourth capacitor C4 are used as voltage stabilizing capacitors to reduce the voltage fluctuation on the second mirror branch 12, so as to output a stable control voltage Vc after the clock signal CLK reaches the target frequency, and finally ensure that the clock signal CLK output by the voltage-controlled oscillation module 40 is stable at the target frequency.

[0102] In some embodiments of the present application, for example, for an embodiment in which the target frequency of the clock signal CLK can be changed by changing the resistance value of the resistance module 30, see Fig.15 , Fig.15 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the resistor module 30 includes a plurality of first resistors R1 and a plurality of third switches S3, and the third switches S3 correspond to the first resistors R1 one by one; the first end of each first resistor R1 is connected to the ground terminal GND, the second end of each first resistor R1 is connected to the first end of the corresponding third switch S3, and the second end of each third switch S3 is connected to the second mirror branch 12. Specifically, when the number of closed third switches S3 is more, the number of multiple first resistors R1 in parallel is more, so the resistance value of the resistor module 30 is smaller; conversely, when the number of closed third switches S3 is less, the number of multiple first resistors R1 in parallel is less, so the resistance value of the resistor module 30 is larger, so by controlling the number of closed third switches S3, the purpose of changing the resistance value of the resistor module 30 and thus changing the target frequency of the clock signal CLK can be achieved.

[0103] In some embodiments of the present application, for example, for an embodiment in which the voltage-controlled oscillator module 40 includes a voltage-controlled oscillator 41 and a non-overlapping clock generation module 42, see Fig.16 , Fig.16 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, wherein the voltage-controlled oscillation module 40 includes a voltage-controlled oscillator 41 and a non-overlapping clock generating module 42, the voltage-controlled oscillator 41 is connected to the second mirror branch 12 to generate a clock signal CLK based on the control voltage Vc, and the non-overlapping clock generating module 42 is connected to the voltage-controlled oscillator 41 to generate a first clock signal CLKA and a second clock signal CLKB that do not overlap each other according to the clock signal CLK.

[0104] It should be noted that, in the present application, non-overlapping means that the first clock signal CLKA and the second clock signal CLKB are not high or low at the same time, for example, when the first clock signal CLKA is high, the second clock signal CLKB is low; conversely, when the first clock signal CLKA is low, the second clock signal CLKB is high. Since the first clock signal CLKA and the second clock signal CLKB do not overlap, the first switch S1 and the second switch S2 will not be turned on at the same time, thereby realizing the normal charging and discharging alternating execution process of the first capacitor C1.

[0105] The clock signal generating circuit provided in the embodiment of the present application forms a loop through the current mirror module 10, the switch capacitor module 20 and the voltage-controlled oscillator module 40. The switch capacitor module 20 acts as a negative feedback module to control the magnitude of the control voltage Vc output by the current mirror module 10, so that the voltage-controlled oscillator module 40 can output the clock signal CLK of the target frequency through negative feedback. The process of generating the clock signal CLK does not require the participation of a comparator, and ultimately the delay of the comparator can be avoided from affecting the frequency accuracy of the oscillator circuit. For example, see Fig.17 , Fig.17 A simulation schematic diagram of the clock signal CLK output by the clock signal generating circuit in an embodiment of the present application is shown. It can be seen that the frequency deviation of the clock signal CLK with a target frequency of 64 MHz can be controlled at about 0.85% at -40°C and 125°C compared with 27°C. The present application significantly improves the accuracy of the clock signal output by the clock generating circuit.

[0106] In some embodiments of the present application, see Fig.18 , Fig.18 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown. The voltage-controlled oscillation module 40 may also include a level conversion module 43 to convert the high-voltage clock signal generated by the voltage-controlled oscillator 41 into a low-voltage clock signal, thereby supplying the low-voltage clock signal to the circuit in the low-voltage domain for use.

[0107] In some embodiments of the present application, see Fig.19 , Fig.19 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown. The clock signal generating circuit may also include a counter 50 and a frequency divider 60. After the counter 50 counts the clock signal output by the level conversion module 43 for a certain number of times, it indicates that the clock signal output by the voltage-controlled oscillation module 40 is stable. Therefore, the frequency divider 60 obtains a qualified clock signal with a stable frequency and a frequency that meets the requirements through frequency division.

[0108] It is worth noting that the above contents about the clock signal generating circuit are intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can also make equivalent modified designs under the guidance of the present application. For example, refer to Fig. 20 , Fig. 20 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown. The clock signal generating circuit may further include a logic module 70 and a delay module 80. The logic module 70 may be a logic circuit composed of a gate circuit, a counter, a timer, etc. The delay module 80 may include a delay circuit. The logic module 70 may control whether the delay module 80 outputs a control signal for controlling the counter 50 to start counting after a certain delay time. Therefore, the logic module 70 and the delay module 80 may achieve the purpose of indirectly controlling whether to output the clock signal.

[0109] Based on the clock signal generating circuit, the embodiment of the present application also provides a clock signal generating system, see Fig.21 , Fig.21 A schematic diagram of a clock signal generating system in an embodiment of the present application is shown, and the clock signal generating system includes: a clock signal generating circuit 100 as described in any of the above embodiments; a first voltage generating circuit 200 for generating a first preset voltage, and the first voltage generating circuit 200 is connected to the clock signal generating circuit 100 to power the clock signal generating circuit 100.

[0110] For example, the first preset voltage output by the first voltage generating circuit 200 can be used as the power supply voltage of all or part of the modules in the clock signal generating circuit 100, for example, the first preset voltage can be used as the power supply voltage of modules such as the current mirror module 10, the switch capacitor module 20, the resistor module 30 and the voltage controlled oscillator module 40. Exemplarily, the first voltage generating circuit 200 may include, but is not limited to, power supply circuits such as a low voltage dropout linear regulator and a bandgap reference circuit.

[0111] In some embodiments of the present application, see Fig. 22 , Fig. 22 Another schematic diagram of a clock signal generating system in an embodiment of the present application is shown. The clock signal generating system also includes a second voltage generating circuit 300 for generating a second preset voltage. The second voltage generating circuit 300 is connected to the clock signal generating circuit 100. The second preset voltage is less than the first preset voltage, so that the second preset voltage output by the second voltage generating circuit 300 is a low-voltage power supply in the clock signal generating circuit. For example, the second preset voltage can be used as a power supply voltage for low-voltage modules such as a level conversion module 43, a non-overlapping clock generating module 42, a counter 50, a divider 60, a logic module 70, and a delay module 80.

[0112] It can be understood that the above figure is only a schematic diagram of the clock signal generating system of the present application. In fact, the clock signal generating system may also include more or fewer modules, for example, see Fig.23 , Fig.23 Another schematic diagram of the clock signal generating system in an embodiment of the present application is shown. The clock signal generating system also includes a bandgap reference source 400 and a control module 500. The bandgap reference source 400 can provide power for the first voltage generating circuit 200 and the second voltage generating circuit 300, and the control module 500 can control whether the clock signal generating circuit 100, the first voltage generating circuit 200, and the second voltage generating circuit 300 are working.

[0113] The embodiment of the present application also provides a chip, which includes the above-mentioned clock signal generating circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip of the present application includes the clock signal generating circuit described in any of the above-mentioned embodiments, it has all the beneficial effects of the clock signal generating circuit, which will not be repeated here.

[0114] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0115] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A clock signal generating circuit, characterized in that: include: A current mirror module, the current mirror module comprising a first mirror branch for outputting a first mirror current and a second mirror branch for outputting a second mirror current; a switch capacitor module, wherein the switch capacitor module is connected to the first mirror branch so that the first mirror current flows through the switch capacitor module; a resistance module, the resistance module being connected to the second mirror branch so that the second mirror current flows through the resistance module and generates a control voltage in the second mirror branch; A voltage-controlled oscillation module, the voltage-controlled oscillation module is connected to the second mirror branch to oscillate under the control of the control voltage and output a clock signal; The second mirror current follows the change of the first mirror current, and the voltage-controlled oscillation module is connected to the switch capacitor module to feedback-control the switch capacitor module based on the clock signal.

2. The clock signal generating circuit according to claim 1, wherein: The clock signal includes a first clock signal and a second clock signal that do not overlap each other, and the switch capacitor module includes a first capacitor, a first switch, and a second switch; A first end of the first switch is connected to the first mirror branch, a second end of the first switch is connected to the first plate of the first capacitor, and a second plate of the first capacitor is connected to the ground end; A first end of the second switch is connected to the first plate of the first capacitor, and a second end of the second switch is connected to the ground end; The control end of the first switch is connected to the voltage-controlled oscillation module to access the first clock signal, and the control end of the second switch is connected to the voltage-controlled oscillation module to access the second clock signal.

3. The clock signal generating circuit according to claim 2, wherein: The switch capacitor module also includes a second capacitor; The first plate of the second capacitor is connected to the first mirror branch, and the second plate of the second capacitor is connected to the ground terminal.

4. The clock signal generating circuit according to claim 2, wherein: The first capacitor includes a plurality of first sub-capacitors and a plurality of first sub-switches, and the first sub-capacitors correspond to the first sub-switches one by one; The first plate of each first sub-capacitor is connected to the first end of the corresponding first sub-switch, the second plate of each first sub-capacitor is connected to the ground end, and the second end of each first sub-switch is connected to the first node between the first switch and the second switch.

5. The clock signal generating circuit according to claim 4, characterized in that: The capacitance values ​​of at least some of the first sub-capacitors in the plurality of first sub-capacitors increase sequentially.

6. The clock signal generating circuit according to claim 1, wherein: The first mirror branch includes a first transistor, and the second mirror branch includes a second transistor; The first end of the first transistor is connected to the power supply end, and the second end of the first transistor is connected to the switch capacitor module; A first end of the second transistor is connected to a power supply end, and a second end of the second transistor is connected to the resistance module; The control end of the second transistor is connected to the control end of the first transistor, and the control end of the first transistor is connected to the second end of the first transistor.

7. The clock signal generating circuit according to claim 6, wherein: The second mirror branch further includes a third capacitor and / or a fourth capacitor; The first plate of the third capacitor is connected to the power supply terminal, and the second plate of the third capacitor is connected to the second terminal of the second transistor; The first plate of the fourth capacitor is connected to the second end of the second transistor, and the second plate of the fourth capacitor is connected to the ground end.

8. The clock signal generating circuit according to claim 1, wherein: The resistance module includes a plurality of first resistors and a plurality of third switches, and the third switches correspond to the first resistors one by one; The first end of each first resistor is connected to the ground end, the second end of each first resistor is connected to the first end of the corresponding third switch, and the second end of each third switch is connected to the second mirror branch.

9. The clock signal generating circuit according to claim 1, wherein: The voltage-controlled oscillation module includes a voltage-controlled oscillator and a non-overlapping clock generation module; The voltage-controlled oscillator is connected to the second mirror branch to generate the clock signal based on the control voltage, and the non-overlapping clock generation module is connected to the voltage-controlled oscillator to generate a first clock signal and a second clock signal that do not overlap each other based on the clock signal.

10. A clock signal generating system, characterized in that: include: The clock signal generating circuit according to any one of claims 1 to 9; A first voltage generating circuit is used to generate a first preset voltage, wherein the first voltage generating circuit is connected to the clock signal generating circuit to supply power to the clock signal generating circuit.

11. A chip, characterized in that: The method comprises the clock signal generating circuit as claimed in any one of claims 1 to 9.

12. An electronic device, characterized in that: Comprising the chip as claimed in claim 11.

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