Nitride diode device structure

Abstract

The utility model discloses a nitride diode device structure. The device structure comprises a substrate, a graphic structure layer and a semiconductor structure layer. The graphic structure layer comprises an array layer, a doping layer and a covering layer; the array layer comprises a plurality of independent patterned convex structures, the doping layer is at least arranged on the top surfaces of the patterned convex structures, and the covering layer continuously covers the doping layer and partial areas among the plurality of patterned convex structures and is provided with a plurality of nanoscale hole structures; the material of the patterned convex structure comprises an oxide of a first element, the material of the covering layer comprises a nitride of the first element, and the material of the doping layer comprises a doping material formed by doping the nitride of the first element with a second element. According to the utility model, the crystal quality of nitride materials is improved; the interface charge trapping capability of the array layer and the covering layer is improved by utilizing doping defect control, and finally the electric leakage performance of the semiconductor epitaxial wafer is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a nitride diode device structure. Background Art

[0002] Nitride semiconductors have many outstanding properties. For example, gallium nitride (GaN) is the most widely used third-generation semiconductor material. It has the characteristics of high bandgap width, high critical breakdown electric field, high carrier saturation migration velocity, high thermal conductivity and direct band gap. It has great application prospects in the fields of high-temperature, high-frequency, high-power microelectronic devices and high-performance optoelectronic devices, and is hailed as the next generation display technology after LCD and OLED displays.

[0003] In the prior art, due to the heteroepitaxial growth of GaN materials on heterogeneous substrates such as sapphire or SiC, the lattice constant and thermal mismatch between different materials will produce dislocations or defects, and extend upward with the growth of the epitaxial layer. These dislocations appear as non-radiative recombination centers when the device is working, affecting the efficiency of the device. At the same time, as leakage channels, they cause the leakage current to increase and cause the device to age rapidly, affecting the working efficiency and life of the device, restricting its application in the field of semiconductor electronics. In addition, with the unprecedented development of high-end application fields, higher requirements are put forward for reducing defects in the epitaxial layer, and the existing process methods are difficult to meet the increasingly stringent high-end requirements.

[0004] In summary, further reducing the defect distribution in the epitaxial layer, improving the crystal quality of the epitaxial layer, and improving the leakage performance of semiconductor devices based on the existing process are of great significance for promoting the application and industrialization of high-end fields of semiconductor materials. Utility Model Content

[0005] In view of the deficiencies in the prior art, the purpose of the utility model is to provide a nitride diode device structure.

[0006] In order to achieve the above-mentioned utility model purpose, the technical solution adopted by the utility model includes:

[0007] The utility model provides a nitride diode device structure, which comprises a substrate, a graphic structure layer and a semiconductor structure layer which are sequentially stacked along a specified direction;

[0008] The graphic structure layer comprises an array layer, a doping layer and a covering layer arranged in sequence along the specified direction;

[0009] The array layer comprises a plurality of patterned protrusion structures independently distributed on a side of the substrate facing the semiconductor structure layer, the doping layer is at least arranged on a top surface of the patterned protrusion structure facing the patterned protrusion structure, the covering layer continuously covers the doping layer and a partial area between the plurality of patterned protrusion structures, and has a plurality of nanoscale hole structures;

[0010] The material of the patterned protruding structure includes an oxide of a first element, the material of the covering layer includes a nitride of the first element, and the material of the doping layer includes a doping material formed by doping the nitride of the first element with a second element.

[0011] Based on the above technical solution, compared with the prior art, the beneficial effects of the utility model at least include:

[0012] The utility model adopts a multi-layer composite graphic structure layer of an array layer, a doping layer and a covering layer. The arrayed multiple graphic protrusion structures improve the lateral epitaxial ability of the nitride material, block the dislocation of the substrate from extending upward, and improve the crystal quality of the nitride material; the covering layer uses its own nanoporous film structure to strengthen the lateral epitaxial ability of the epitaxial layer between adjacent graphic protrusion structures, so that the dislocation of the epitaxial layer in the merging process above the nanopore is diverted, further improving the crystal quality of the nitride material;

[0013] During the process of manufacturing, the covering layer tends to form bonds centered on the surface dangling bonds, which can shield the charged centers of the dangling bonds near the surface of the substrate and reduce the leakage channels between the surfaces of the substrate.

[0014] The doped layer between the two layers utilizes doping defect control to improve the interface charge capture capability of the array layer and the cover layer, improve the interface characteristics, reduce the interface charge movement, thereby greatly reducing the formation of leakage channels and ultimately improving the leakage performance of the semiconductor epitaxial wafer.

[0015] Therefore, under the combined effect of the array layer, the doping layer and the covering layer, the epitaxial quality and the leakage performance of the nitride diode device structure are significantly improved.

[0016] The above description is only an overview of the technical solution of the utility model. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement them according to the contents of the specification, the following is a preferred embodiment of the utility model with detailed drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of a nitride diode device structure provided by a typical implementation case of the utility model;

[0018] Figure 2 It is a structural schematic diagram of a nitride diode device structure provided by another typical implementation case of the utility model;

[0019] Figure 3a It is a structural schematic diagram of a nitride diode device structure provided by another typical implementation case of the utility model;

[0020] Figure 3b It is a structural schematic diagram of a nitride diode device structure provided by another typical implementation case of the utility model.

[0021] Description of reference numerals:

[0022] 10, substrate; 101, array layer; 1011, second protruding structure; 1012, first protruding structure; 102, doping layer; 103, covering layer;

[0023] 20. first nitride layer; 201. buffer layer;

[0024] 30. Active layer;

[0025] 40. a second nitride layer;

[0026] 501, first electrode; 502, second electrode. DETAILED DESCRIPTION

[0027] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the utility model after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0028] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0029] Moreover, relational terms such as “first” and “second” are merely used to distinguish one component or method step from another with the same name, but do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0030] See also Figure 1 or Figure 2The present invention provides a nitride diode device structure, which includes a substrate 10, a graphic structure layer and a semiconductor structure layer stacked in sequence along a specified direction; the graphic structure layer includes an array layer 101, a doping layer 102 and a covering layer 103 arranged in sequence along the specified direction; the array layer 101 includes a plurality of graphic protrusion structures independently distributed on a side of the substrate 10 facing the semiconductor structure layer, the doping layer 102 is at least arranged on the top surface of the graphic protrusion structure facing the graphic protrusion structure, the covering layer 103 continuously covers the doping layer 102 and a partial area between the plurality of graphic protrusion structures, and has a plurality of nanoscale hole structures; the material of the graphic protrusion structure includes an oxide of a first element, the material of the covering layer 103 includes a nitride of the first element, and the material of the doping layer 102 includes a doping material formed by doping the nitride of the first element with a second element.

[0031] In some embodiments, the doping of the second element improves the charge trapping capability of the pattern structure layer and / or produces a passivation effect on the pattern structure layer.

[0032] In some embodiments, the first element may include Si, for example.

[0033] In some embodiments, the nitride diode device structure is a nitride diode device; one case is as follows Figure 1 As shown, the doping layer 102 only covers the top surface of the patterned protruding structure, and the covering layer 103 is in direct contact with the sidewall of the patterned protruding structure; or another case as shown in FIG. Figure 2 As shown, the doping layer 102 continuously covers the top surface and the side surface of the patterned protruding structure and the surface of the substrate 10 between the plurality of the patterned protruding structures, and the covering layer 103 is isolated from the patterned protruding structure and the substrate 10 by the doping layer 102 .

[0034] The above structure is mainly applicable to most nitride diode devices. In recent years, Micro-LED display has become a hot research direction and has received great attention from domestic and foreign industries and academia. In addition, the optoelectronic modulation bandwidth of Micro-LED reaches GHz, which is much higher than that of lighting LED, and has the advantage of high-speed parallel visible light communication. However, there are still some problems to be solved in the application of Micro-LED in display technology. As the device size decreases, the external quantum efficiency of Micro-LED drops sharply. As the device size decreases, the surface area to volume ratio increases, and the side wall surface of the device is seriously damaged by cutting, resulting in current leakage and external quantum efficiency attenuation. Especially when the device size is reduced to below 100μm, the proportion of side wall defects increases sharply, and the resulting surface state recombination is more serious, affecting the optoelectronic properties of the device.

[0035] In summary, how to reduce the current leakage caused by sidewall damage is of great significance for realizing small-sized and high-efficiency Micro-LED chips.

[0036] Therefore, in some more specific implementation schemes, the present invention also specifically targets the technical problems existing in Micro-LEDs, and sets the device structure as follows: Figure 2 As shown, the graphic protrusion structure includes a first protrusion structure 1012 and a second protrusion structure 1011, the width and height of the first protrusion structure 1012 are smaller than those of the second protrusion structure 1011; the first protrusion structure 1012 is arranged in the middle part of the substrate 10, and the second protrusion structure 1011 is arranged near the edge of the substrate 10.

[0037] Regarding specific size parameters, in some embodiments, the first protrusion structure 1012 has a width of 0.5-2 μm, a height of 0.1-0.5 μm, and a pitch of 0.1-1 μm;

[0038] In some embodiments, the width and height of the second protruding structure 1011 are both more than twice the width and height of the first protruding structure 1012 .

[0039] As some typical examples of the above technical solutions, embodiments of another aspect of the present invention specifically relate to a high-efficiency Micro-LED epitaxial structure and chip.

[0040] Continue as Figure 2 As shown, the epitaxial structure at least includes a substrate 10, a first nitride layer 20, a nitride active layer 30, and a second nitride layer 40, and an array layer 101, a doping layer 102, and a covering layer 103 are disposed at least on the bottom substrate.

[0041] The base 10 is a substrate, which may be one of silicon, sapphire, silicon carbide, and gallium nitride, or may be a nitride material layer, which may be GaN, AlN, or an alloy thereof.

[0042] The array layer 101 is disposed on the substrate 10 , the doping layer 102 is disposed on the array layer 101 , and the covering layer 103 completely covers the array layer 101 .

[0043] The size of the second protruding structure 1011 is larger than that of the first protruding structure 1012, and the second protruding structure 1011 is located outside the first protruding structure 1012. The first protruding structure 1012 is made of SiO2, with a bottom width of 0.5 to 2 μm, a height of 0.1 to 0.5 μm, and a spacing of 0.1 to 1 μm; the doping layer 102 is made of Si-XN, with a thickness of 1 to 10 nm, where X is one of O, S, P, Cl, and F; the covering layer 103 has a thickness of 2 to 20 nm and a pore size of 5 to 100 nm;

[0044] The first nitride layer 20 and the second nitride layer 40 have different conductivity types and can be an n-type nitride layer or a p-type nitride layer. The n-type nitride layer is, for example, a Si-doped nitride layer with a thickness of 1 to 5 μm. The Si doping concentration can be, for example, 1×10 18 cm -3 ~8×10 18 cm -3 The p-type nitride layer is, for example, a Mg-doped nitride layer with a thickness of 20 to 300 nm and a Mg doping concentration of 1×10 19 cm -3 ~1×10 21 cm -3 The nitride active layer 30 includes, for example, 2 to 10 periodically overlappingly grown nitride quantum well layers with a thickness of 1 to 6 nm and nitride quantum barrier layers with a thickness of 6 to 25 nm.

[0045] The Micro-LED chip, for example, further includes at least a first electrode 501 and a second electrode 502. When the first electrode 501 and the second electrode 502 are disposed on the same side of the substrate 1, a front-mounted Micro-LED chip is formed. Figure 3a In addition, the first electrode 501 and the second electrode 502 can also be arranged on both sides of the substrate 10 to form a vertical Micro-LED chip, as shown in FIG. Figure 3b shown.

[0046] The above embodiment enhances the lateral epitaxy of the first nitride layer 20 and improves its crystal quality by setting graphic protrusion structures of different sizes. The cover layer 103 utilizes its own nanoporous film structure to enhance the lateral epitaxy between adjacent graphic structures, blocks the dislocations below the area between the graphic structures from extending upward, further improves the crystal quality of the nitride material, reduces the defect density in the epitaxial layer of the nitride material, and improves the leakage performance of the epitaxial wafer. The doping layer 102 utilizes doping defect control to improve the charge capture capability of the SiO2 and SiN interfaces, improves interface characteristics, and reduces interface charge movement.

[0047] In addition, the size of the second protruding structure 1011 is larger than that of the first protruding structure 1012, and a stronger charge capture capability is generated at the interface of the second protruding structure 1011. Therefore, a difference in charge capture capability is formed in the lateral direction inside the first nitride layer 20, resulting in a lower charge concentration above the side wall of the first nitride layer. Ultimately, carrier recombination near the side wall of the nitride active layer 30 is reduced, and the charges injected into the nitride active layer 30 from the second nitride layer 40 have more opportunities to recombine within the side wall of the nitride active layer 30, thereby improving the luminous efficiency of the Micro-LED chip, and is particularly suitable for chip sizes less than 100 μm.

[0048] Regardless of being applied to ordinary nitride diodes or nitride Micro-LEDs, regarding other implementation details, in some embodiments, the size of the hole structure in the cover layer 103 is 5-150 nm, and the porosity is 60-90%.

[0049] In other embodiments, the thickness of the cover layer 103 may be 2-50 nm.

[0050] In some embodiments, the second element includes any one of O, S, P, F, and Cl, or a combination of two or more thereof.

[0051] As some typical examples of the above technical solutions, the nitride diode device structure is, for example, a semiconductor epitaxial wafer with a low leakage channel bottom layer, including a substrate, a nitride buffer layer 201 with a thickness of 1 to 5 μm, a first nitride layer 20 with a thickness of 1 to 10 μm, a nitride active layer 30, and a second nitride layer 40 with a thickness of 20 to 300 nm. The nitride active layer 30 includes a periodically cyclically overlapping growth of a nitride quantum well layer with a thickness of 1 to 6 nm and a nitride quantum barrier layer with a thickness of 6 to 25 nm.

[0052] The above structure belongs to a conventional nitride diode epitaxial structure. The device structure provided by the embodiment of the utility model is characterized in that an array layer 101, a doping layer 102 and a covering layer 103 are arranged at least between the lower surface of the first nitride layer 20 and the upper surface of the substrate, and the doping layer 102 and the covering layer 103 are arranged on multiple patterned protruding structures of the array layer 101, and at least the covering layer 103 is a thin film with a nanopore structure; wherein the material of the array layer 101 can be, for example, SiO2, with a bottom width of 1 to 5 μm, a height of 1 to 5 μm, and a spacing of 0.1 to 1 μm; the material of the doping layer 102 can be, for example, Si-XN, with a thickness of 1 to 20 nm, wherein X is one or more combinations of O, S, P, F, and Cl; the material of the covering layer 103 can be, for example, SiN, with a thickness of 2 to 50 nm and a pore size of 5 to 150 nm.

[0053] The above exemplary technical scheme improves the crystal quality of the epitaxial wafer, reduces the defect density in the epitaxial layer of the nitride material, and improves the leakage performance of the epitaxial wafer by setting a doping layer 102 between the patterned protruding structure and the covering layer 103. Specifically: the patterned protruding structure improves the lateral epitaxy of the nitride material, blocks the dislocations below the pattern from extending upward, and improves the crystal quality of the nitride material. The covering layer 103 utilizes its own nanoporous thin film structure to strengthen the lateral epitaxy of the nitride buffer layer 201 between adjacent patterned protruding structure patterns. The dislocations of the nitride buffer layer 201 are diverted during the merging process above the nanopores, further improving the crystal quality of the nitride material and blocking the dislocations below the area between the patterns from extending upward, so that the dislocations will not extend upward to the nitride light-emitting layer. The doping layer 102 utilizes doping defect control to improve the interface charge capture capability of SiO2 and SiN, improve interface characteristics, reduce interface charge movement, thereby greatly reducing the formation of leakage channels and ultimately improving the leakage performance of the semiconductor epitaxial wafer.

[0054] The patterned structure of the array layer 101 made of SiO 2 may be prepared by referring to the patterning methods in the prior art, such as patterned etching or patterned growth.

[0055] The growth of porous SiN as the capping layer 103 can also refer to the relevant prior art; the control of semiconductor material defects plays a key role in the epitaxial growth of high-quality nitride materials. Since there is a high defect density (greater than 10 8 cm -2), the defects in the epitaxial layer can be connected to form a charge channel, which eventually causes leakage and affects the leakage performance of the epitaxial wafer; SiN has the characteristic of discontinuous film formation at the micro-nano level, and the thickness can be controlled to form a SiN nanoporous structure film; if there is no intercalated doping layer 102 in the middle, there will be more multiple Si· with dangling bonds in the array layer 101, the cover layer 103 and the interface between the two, which will become the charge capture center, and the X-Si· charge capture energy ΔE in the Si-XN structure layer of the doping layer 102 is reduced, thereby improving the charge capture ability, and the capture process product is more stable, which greatly improves the leakage performance of the epitaxial wafer.

[0056] Specifically, there is a Si atom bonded to three N atoms in the SiN material layer, and then there is a dangling bond (Si·) or a positive Si + Charge centers, these dangling bonds or positive charge centers can capture electrons to form electron capture centers. When the material is doped, the defect structure in the material is changed. Doping can change the type and number of defects that capture charges. The ability to capture charges is related to the formation energy of the defect capture charge process. According to the principle of minimum energy, the lower the formation energy of captured charges, the stronger the ability to capture charges and the more stable the energy state after capturing charges.

[0057] When Si-N is X-doped (O, S, P) to form X-Si·, the formation energy of its captured electrons is reduced by more than one third, and it has better electron capture ability. After capturing electrons, it forms a more stable energy state, and the captured electrons are more difficult to be released, which plays a better role in electron solidification, reduces the probability of electron movement, and thus greatly reduces the formation of leakage channels, and ultimately improves the leakage performance of semiconductor epitaxial wafers. Furthermore, the doped layer 102Si-XN utilizes doping defect control to improve the interface charge capture ability of SiO2 and SiN, improves interface characteristics, and reduces interface charge movement, thereby greatly reducing the formation of leakage channels and ultimately improving the leakage performance of semiconductor epitaxial wafers.

[0058] There are many ways to prepare the above-mentioned doping layer 102, and usually methods such as thermal decomposition, chemical vapor deposition, and plasma enhanced chemical vapor deposition can be used. Among them, thermal decomposition is one of the most commonly used methods, which generates silicon nitride by reacting silicon and ammonia at high temperature. Chemical vapor deposition is a method of generating SiN thin film using gas phase reaction, which is usually used to prepare silicon nitride materials with special surface properties, but the doping of SiN material layer is difficult to control. Generally, ion implantation can be used, but ion implantation separates the preparation and doping processes of SiN material layer, which increases the complexity of process steps, and the conventional in-situ doping process of SiN material is difficult to control, and doping atoms are more likely to combine with Si atoms to cause more N vacancy defects.

[0059] The optional range of doping elements also includes F and Cl, which are generally used for passivation of integrated circuits. Although they can produce the same capture mechanism as O, S, and P, Cl and F are more used for passivation of Si dangling bonds Si·, and their charge capture effect is weaker than O, S, and P. They can mainly reduce the charge center in the SiN layer itself, that is, their passivation effect is significantly stronger than the charge capture effect.

[0060] In practice, the inventors of the utility model have found that a better charge control effect can be achieved by overlapping multiple sublayers formed by doping with different types of doping elements. For example, SiN can be used to dope the first layer (O, S, P), and then another Si-XN (F, Cl doping) layer can be made on the Si-XN (O, S, P). The Si-XN (O, S, P) sublayer is used to capture charges close to the substrate, because in the epitaxial growth process, more dislocations come from the lattice mismatch between the substrate and the epitaxial layer, so there are more defects in the epitaxial layer close to the substrate, and the defects themselves are mostly charged centers that will cause charge generation; the Si-XN (F, Cl) sublayer is mainly used for charge passivation inside the SiN layer interface itself, providing a growth basis for low charge distribution; the alternating and coordinated stacking of the two sublayers not only strengthens the charge control, but also reduces the process difficulty when doping thicker single-layer films.

[0061] Specifically, the Si-XN(O, S, P) and Si-XN(F, Cl) sublayers can be overlapped periodically, and Si-XN(F, Cl) can block the charges leaked from the charge capture layer on the basis of providing multiple charge capture layers by Si-XN(O, S, P).

[0062] Therefore, in some embodiments, the doping layer 102 includes a first sublayer and a second sublayer that are periodically stacked; the doping element of the first sublayer is any one of O, S, and P or a combination of two or more, and the doping element of the second sublayer is any one of F and Cl or a combination of two.

[0063] In addition, regarding other implementation details, in some embodiments, the thickness of the first sublayer and / or the second sublayer is 2-5 nm;

[0064] In some embodiments, the in-plane doping concentration of the first sublayer is 5×10 13 ~5×10 17 cm -2 , the in-plane doping concentration of the second sub-layer is 1×10 13 ~1×10 17 cm -2 ;

[0065] In some embodiments, the number of cycles of the first sublayer and the second sublayer is 2-5.

[0066] Corresponding to the above device structure, the embodiment of the utility model further provides a method for preparing a nitride diode device structure, which comprises the following steps 1-5:

[0067] Step 1, providing a substrate 10;

[0068] Step 2, forming a plurality of independent patterned protruding structures arranged in a patterned array on the surface of the substrate 10 to constitute an array layer 101, wherein the material of the patterned protruding structures includes an oxide of a first element;

[0069] Step 3, at least a doping layer 102 is provided on the top surface of the patterned protruding structure, wherein the material of the doping layer 102 includes a material formed by a nitride of a first element doped with a second element;

[0070] Step 4, covering a portion of the area between the doping layer 102 and the plurality of the patterned protruding structures with a covering layer 103, wherein the covering layer 103 is made of a nitride of a first element, and the array layer 101, the doping layer 102 and the covering layer 103 constitute a patterned structure layer;

[0071] Step 5: Covering the surface of the graphic structure layer with a semiconductor structure layer to form a nitride diode device structure.

[0072] As some typical application examples of the above technical solution, the above preparation method can be implemented by the following process steps:

[0073] S1: providing a substrate, for example, comprising one of silicon, sapphire and silicon carbide;

[0074] S2: growing a nitride buffer layer 201 with a thickness of 1 to 5 μm on the substrate at a temperature of 1050 to 1250° C. and a pressure of 100 to 400 torr;

[0075] S3: growing a first nitride layer 20 with a thickness of 1 to 10 μm on the nitride buffer layer 2012 at a temperature of 1000 to 1200° C. and a pressure of 100 to 400 torr;

[0076] S4: growing a nitride active layer 30 on the first nitride layer 20 at a pressure of 100 to 500 torr, including periodically and cyclically growing a nitride quantum well layer with a thickness of 1 to 6 nm and a nitride quantum barrier layer with a thickness of 6 to 25 nm;

[0077] S5: growing a second nitride layer 40 with a thickness of 20 to 300 nm on the nitride active layer 30 at a temperature of 950 to 1050° C. and a pressure of 100 torr to 500 torr;

[0078] Wherein, on the substrate of step S1 or on the surface (or inside) of step S2, the following are arranged in sequence: the array layer 101 is SiO2, the growth temperature is 200-800°C, the bottom width is 1-5 μm, the height is 0.5-2.5 μm, and the spacing is 0.1-1 μm;

[0079] The doping layer 102 is Si-XN, with a growth temperature of 200-1000° C. and a thickness of 1-20 nm, wherein X is one of O, S, P, F or Cl;

[0080] The cover layer 103 is SiN, with a growth temperature of 200-1000° C., a thickness of 2-50 nm, and a pore size of 5-150 nm.

[0081] Corresponding to the implementation of the multi-layer stacking of different types of doping elements in the above embodiments, in some embodiments, the second element includes a first selected element and a second selected element. In step 3, the formation process of the doping layer 102 specifically includes sub-steps ae:

[0082] Step a, growing a first thin layer by vapor phase epitaxy under first process conditions, wherein the material of the first thin layer includes a nitride of the first element;

[0083] Step b, performing doping epitaxial growth of a first selected element on the surface of the first thin layer under a second process condition to form a first sublayer;

[0084] Step c, growing a second thin layer by vapor phase epitaxy under a third process condition, wherein the material of the second thin layer includes a nitride of the first element;

[0085] Step d, performing doping epitaxial growth of a second selected element on the surface of the second thin layer under a fourth process condition to form a first sublayer;

[0086] Step e: cyclically performing the growth process of the first sub-layer and the second sub-layer to form the doped layer 102.

[0087] As for the specific implementation process conditions, in some embodiments, the first process conditions in step a include a growth temperature of 200-1000° C. and a pressure of 100-400 torr;

[0088] In some embodiments, the second process conditions in step b include a growth temperature of 200-1000° C. and a pressure of 200-500 torr;

[0089] In some embodiments, the third process conditions in step c include a growth temperature of 200-1000° C. and a pressure of 100-400 torr;

[0090] In some embodiments, the fourth process conditions in step d include a growth temperature of 200-1000° C. and a pressure of 200-500 torr;

[0091] In order to improve doping efficiency and doping uniformity, it is preferably set that the growth pressure of the second process condition is higher than that of the first process condition, and the growth pressure of the fourth process condition is higher than that of the third process condition.

[0092] In addition, regarding the doping time, in some embodiments, the doping epitaxial growth time of the first selected element and / or the second selected element in steps b and c is 30-60 seconds.

[0093] Further in some embodiments, the preparation method also includes: growing the covering layer under fifth process conditions; wherein the Si / N atomic ratio adopted by the first process conditions and the third process conditions is greater than 1.2, and the Si / N atomic ratio adopted by the fifth process conditions is less than 1.2.

[0094] The above-mentioned implementation mode is optimized by limiting the Si / N atomic ratio of the doping layer and the covering layer. When growing the doping layer, a relatively high Si / N atomic ratio is used to improve the film density of the doping layer, thereby improving the passivation performance; when growing the covering layer, a relatively low Si / N atomic ratio is used to form a thin film structure with a gap distribution, thereby reducing the surface refractive index of the covering layer. On the one hand, a large light refraction can be formed at the interface of the nitride material, which is beneficial to improving the forward light output; on the other hand, the distribution of Si atoms in the covering layer close to the nitride material is reduced to avoid Si atom diffusion, which is beneficial to improving the leakage performance.

[0095] More specific exemplary conditions are as follows: In some embodiments, in the first process condition and the third process condition, the Si source flow rate is 10-100 sccm, and the N source flow rate is 2-20 slm; in the fifth process condition, the Si source flow rate is 100-300 sccm, and the N source flow rate is 5-50 slm

[0096] In some embodiments, the first selected element includes any one of O, S, and P or a combination of two or more thereof, and the second selected element includes any one of F and Cl or a combination of two thereof.

[0097] As some typical application examples of the above technical solution, for example, Si-XN (O, S, P) and Si-XN (F, Cl) can be periodically overlapped, on the one hand, Si-XN (O, S, P) provides multiple charge capture layers, and Si-XN (F, Cl) blocks the charges leaked in the charge capture layer; on the other hand, the doping efficiency of the SiN material layer is improved, and the difficulty of the doping process is reduced; its preparation process includes:

[0098] 1) Under the conditions of a growth temperature of 200-1000° C. and 100-400 torr, grow Si-N with a thickness of 2-5 nm as a first thin layer; 2) Under the conditions of a growth temperature of 200-1000° C. and 200-500 torr, perform a first co-growth doping treatment (O, S, P) on the SiN surface for 30-60 seconds to form a first sublayer; 3) Under the conditions of a growth temperature of 200-1000° C. and 100-400 torr, grow Si-N with a thickness of 2-5 nm to form a second thin layer; 4) Under the conditions of a growth temperature of 200-1000° C. and 200-500 torr, perform a second doping treatment (F, Cl) on the SiN surface for 30-60 seconds to form a second sublayer; 5) Periodically overlap growth steps 1) to 4) for a total of 2 to 5 cycles to form a doped layer 102.

[0099] In the above preparation process, when the SiN material layer is surface treated, the doping atoms can quickly diffuse and enter the lattice on the silicon nitride surface to replace atoms to complete the doping. However, after the surface lattice atom replacement is completed, the doping atoms will slowly diffuse into the SiN material layer. The doping process takes a long time, which reduces the production efficiency. In the utility model, since the thickness of the single thin layer is relatively thin, the repeated overlapping doping method can achieve uniform doping in the relatively thin SiN sublayer (nm level), thereby improving the doping efficiency.

[0100] The technical solution of the utility model is further described in detail below through several embodiments and in combination with the accompanying drawings. However, the selected embodiments are only used to illustrate the utility model, and do not limit the scope of the utility model.

[0101] Example 1

[0102] This embodiment illustrates a preparation process of a nitride diode epitaxial wafer, which is specifically as follows:

[0103] S1: Provide a silicon substrate and place it in the reaction chamber of the MOCVD equipment;

[0104] S11: placing a SiO2 layer in a reaction chamber of a PECVD device, and then preparing a plurality of independent patterned protruding structures by conventional photolithography process, wherein the growth temperature is 600° C., and the bottom width of the patterned protruding structures after etching is 5 μm, the height is 2.5 μm, and the spacing is 1 μm;

[0105] S12: placing the epitaxial wafer with the patterned protruding structure in a reaction chamber of an MOCVD device, and epitaxially growing a Si-XN doped layer on the top surface thereof, specifically comprising:

[0106] S121: growing SiN with a thickness of 3 nm as the first thin layer at a growth temperature of 600° C. and 300 torr, with a Si / N atomic ratio of 1.6;

[0107] S122: Under the conditions of growth temperature of 700°C and 400 torr, the SiN surface is subjected to the first co-growth doping treatment (O) for 40 seconds to form the first sublayer, wherein the doping concentration of O is 5×10 15 ;

[0108] S123: growing SiN with a thickness of 3 nm at a growth temperature of 600° C. and 300 torr to form a second thin layer, with an Si / N atomic ratio of 1.6;

[0109] S124: Under the conditions of growth temperature of 700°C and 400 torr, the SiN surface is subjected to a second doping treatment (Cl) for 40 seconds to form a second sublayer, wherein the doping concentration of Cl is 1×10 15 ;

[0110] S125: performing periodic overlapping growth steps S121-S124 for a total of 4 cycles to form a doped layer;

[0111] S13: growing SiN with a thickness of 25 nm as a covering layer at a growth temperature of 800° C., with a Si / N atomic ratio of 0.8 to cover the patterned protruding structure and its doping layer, the covering layer being a nanoporous structure with a pore size distribution of 5 to 150 nm;

[0112] S2: growing a 5 μm thick GaN buffer layer on the substrate at a temperature of 1150°C and a pressure of 250 torr;

[0113] S3: Under the conditions of temperature 1100℃ and pressure 100torr, 5μm n-type GaN is grown on the GaN buffer layer, with Si as dopant and doping concentration of 5×10 18 cm -3 .

[0114] S4: Under the condition of a pressure of 300 torr, a nitride active layer is grown on n-type GaN, with a cycle period of 2 to 15, the nitride quantum well is InGaN, the growth temperature is 800°C, and the nitride quantum barrier is GaN, the growth temperature is 850°C;

[0115] S5: At a temperature of 1000°C and a pressure of 300 torr, a p-type GaN layer with a thickness of 150 nm is grown on the nitride active layer. The dopant is Mg with a doping concentration of ~1×10 20 cm -3 .

[0116] S6: After the formed semiconductor device is connected to electrodes, a gallium nitride diode capable of emitting light is formed.

[0117] Performance Testing:

[0118] The Candela test results of the epitaxial wafer surface prepared in Example 1 show that the epitaxial wafer surface has a low defect distribution, and the surface defect density is 9.2×10 7 cm -2 Compared with the conventional process, the surface defect density of epitaxial wafers is greater than 5×10 8 cm -2 A significant reduction has been achieved.

[0119] In addition, the X-ray double crystal diffraction half-peak width test of the epitaxial wafer prepared in Example 1 shows that the (102) plane has a low half-peak width of 146 arcsec, which is significantly lower than the 200 arcsec or more of the conventional epitaxial wafer.

[0120] Example 2

[0121] This embodiment illustrates a preparation process of a nitride Micro-LED, which is specifically as follows:

[0122] Similar to Example 1, Micro-LED is formed by epitaxial growth, wherein, when preparing the SiO2 patterned convex structure in step S11, two types of patterned structures, large and small, are etched by multiple patterned photolithography, the smaller first convex structure is arranged in the middle area of ​​the Micro-LED light-emitting unit, and the larger second convex structure is arranged at the edge of the Micro-LED light-emitting unit, as shown in FIG. Figure 2 shown.

[0123] The first protruding structure has a bottom width of 1 μm, a height of 0.5 μm, and a spacing of 1 μm. The width and height of the second protruding structure are both twice that of the first protruding structure, and the spacing between adjacent protruding structures is equal to the spacing between the first protruding structures.

[0124] Comparative Example 1

[0125] This comparative example is substantially the same as Example 1, except that:

[0126] In step S124 , O doping continues without Cl doping, so the formed doping layer is an integral O doping layer rather than a multilayer stack of two differently doped sub-layers.

[0127] Comparative Example 2

[0128] This comparative example is substantially the same as Example 1, except that:

[0129] In step S122, Cl is doped but O is no longer doped. Therefore, the formed doping layer is an integral Cl-doped layer rather than a multilayer stack of two differently doped sub-layers.

[0130] Performance Testing:

[0131] The photoelectric performance test of the prepared light-emitting diode device is shown in the following table

[0132] Comparative Example 3

[0133] This comparative example is substantially the same as Example 2, except that:

[0134] The raised structures at the edge are consistent in size with the raised structures in the center, and there is no combination of raised structures that are larger outside and smaller inside.

[0135] Example 3

[0136] This embodiment is substantially the same as Embodiment 1, and the main difference is that the conditions of steps S12-S13 are different, specifically:

[0137] S12: placing the epitaxial wafer with the patterned protruding structure in a reaction chamber of an MOCVD device, and epitaxially growing a Si-XN doped layer on the top surface thereof, specifically comprising:

[0138] S121: growing SiN with a thickness of 2 nm as the first thin layer at a growth temperature of 300° C. and 400 torr, with a Si / N atomic ratio of 2.0;

[0139] S122: Under the conditions of growth temperature of 300°C and 500 torr, the SiN surface is subjected to the first co-growth doping treatment (S) for 30 seconds to form the first sublayer, where the S doping concentration is 5×10 13 ;

[0140] S123: growing SiN with a thickness of 2 nm at a growth temperature of 300° C. and 400 torr to form a second thin layer, with an Si / N atomic ratio of 2.0;

[0141] S124: Under the conditions of growth temperature of 300°C and 500 torr, the SiN surface is subjected to a second doping treatment (F) for 30 seconds to form a second sublayer, wherein the F doping concentration is 1×10 13 ;

[0142] S125: performing periodic overlapping growth steps S121-S124 for a total of 3 cycles to form a doped layer;

[0143] S13: The growth temperature is 800° C., and SiN with a thickness of 5 nm is grown as a covering layer. The Si / N atomic ratio used is 0.6 to cover the graphic protrusion structure and its doping layer. The covering layer is a nanoporous structure with a pore size distribution of 5 to 150 nm.

[0144] Example 4

[0145] This embodiment is substantially the same as Embodiment 1, and the main difference is that the conditions of steps S12-S13 are different, specifically:

[0146] S12: placing the epitaxial wafer with the patterned protruding structure in a reaction chamber of an MOCVD device, and epitaxially growing a Si-XN doped layer on the top surface thereof, specifically comprising:

[0147] S121: growing SiN with a thickness of 5 nm as the first thin layer at a growth temperature of 1000° C. and 100 torr, with an Si / N atomic ratio of 3.0;

[0148] S122: Under the conditions of growth temperature of 1000°C and 200 torr, the SiN surface is subjected to the first co-growth doping treatment (P) for 60 seconds to form the first sublayer, wherein the doping concentration of P is 5×10 17 ;

[0149] S123: growing SiN with a thickness of 5 nm at a growth temperature of 1000° C. and 100 torr to form a second thin layer, with an Si / N atomic ratio of 3.0;

[0150] S124: Under the conditions of growth temperature of 1000°C and 200 torr, the SiN surface is subjected to a second doping treatment (F) for 60 seconds to form a second sublayer, wherein the F doping concentration is 1×10 17 ;

[0151] S125: performing periodic overlapping growth steps S121-S124 for a total of 5 cycles to form a doped layer;

[0152] S13: The growth temperature is 800° C., and SiN with a thickness of 50 nm is grown as a covering layer. The Si / N atomic ratio used is 1.0 to cover the graphic protrusion structure and its doping layer. The covering layer is a nanoporous structure with a pore size distribution of 5 to 150 nm.

[0153] Embodiment 3 and Embodiment 4 have the same technical effects as Embodiment 1, so that the epitaxial quality and leakage performance of the nitride diode device structure are significantly improved.

[0154] Comparative Example 4

[0155] This comparative example is substantially the same as Example 3, with the main difference being that the magnitude relationship of Si / N in steps S12 and S13 of this comparative example is opposite to that of Example 3.

[0156] Epitaxial wafers with a wavelength of 460±0.5 nm were grown through the above-mentioned embodiments and comparative examples, and Micro-LED chips with a size of 100*80 μm were manufactured through conventional chip preparation work. The photoelectric performance of the chip was measured by LED chip spot testing equipment as shown in the following table:

[0157]

[0158] From the above table, we can see that the brightness of the epitaxial wafer chip of the utility model is significantly improved compared with the conventional process epitaxial wafer <12.5mW, and the leakage yield is improved by more than 2% compared with the conventional process epitaxial wafer <97%. In addition, the size relationship of different silicon nitrogen atomic ratios in steps S12 and S13 also affects the brightness, leakage yield, and optoelectronic properties such as half-peak width.

[0159] Based on the above embodiments and comparative examples, it can be clearly seen that the technical solution provided by the embodiments of the utility model adopts a multi-layer composite graphic structure layer of an array layer, a doping layer and a covering layer. The arrayed multiple graphic protrusion structures improve the lateral epitaxial ability of the nitride material, block the upward extension of the dislocations of the substrate, and improve the crystal quality of the nitride material; the covering layer utilizes its own nanoporous film structure to strengthen the lateral epitaxial ability of the epitaxial layer between adjacent graphic protrusion structures, so that the dislocations of the epitaxial layer in the merging process above the nanopores are diverted, further improving the crystal quality of the nitride material; and the doping layer between the two layers utilizes doping defect control to improve the interface charge capture ability of the array layer and the covering layer, improve the interface characteristics, reduce the interface charge movement, thereby greatly reducing the formation of leakage channels and ultimately improving the leakage performance of the semiconductor epitaxial wafer.

[0160] It should be understood that the above embodiments are only for illustrating the technical concept and features of the utility model, and their purpose is to enable people familiar with the technology to understand the content of the utility model and implement it accordingly, and they cannot be used to limit the protection scope of the utility model. Any equivalent changes or modifications made according to the spirit of the utility model should be included in the protection scope of the utility model.

Claims

1. A nitride diode device structure, characterized in that: It includes a substrate, a graphic structure layer and a semiconductor structure layer which are sequentially stacked along a specified direction; The graphic structure layer comprises an array layer, a doping layer and a covering layer arranged in sequence along the specified direction; The array layer comprises a plurality of patterned protrusion structures independently distributed on a side of the substrate facing the semiconductor structure layer, the doping layer is at least arranged on a top surface of the patterned protrusion structure facing the patterned protrusion structure, the covering layer continuously covers the doping layer and a partial area between the plurality of patterned protrusion structures, and has a plurality of nanoscale hole structures; The material of the patterned protruding structure includes an oxide of a first element, the material of the covering layer includes a nitride of the first element, and the material of the doping layer includes a doping material formed by doping the nitride of the first element with a second element.

2. The nitride diode device structure according to claim 1, characterized in that: The doping of the second element improves the charge capture capability of the graphic structure layer and / or produces a passivation effect on the graphic structure layer; The first element includes Si.

3. The nitride diode device structure according to claim 1, characterized in that: The nitride diode device structure is a nitride diode device; The doping layer only covers the top surface of the patterned protruding structure, and the covering layer is in direct contact with the sidewall of the patterned protruding structure; Alternatively, the doping layer continuously covers the top surface and side surfaces of the patterned protruding structure and the surface of the substrate between the plurality of patterned protruding structures, and the covering layer is isolated from the patterned protruding structure and the substrate by the doping layer.

4. The nitride diode device structure according to claim 3, characterized in that: The graphic protrusion structure includes a first protrusion structure and a second protrusion structure, wherein the width and height of the first protrusion structure are both smaller than those of the second protrusion structure; The first protruding structure is arranged at the middle part of the base, and the second protruding structure is arranged near the edge of the base.

5. The nitride diode device structure according to claim 4, characterized in that: The first protrusion structure has a width of 0.5-2 μm, a height of 0.1-0.5 μm, and a spacing of 0.1-1 μm; And / or, the width and height of the second protruding structure are both more than twice the width and height of the first protruding structure.

6. The nitride diode device structure according to any one of claims 1 to 5, characterized in that: The size of the pore structure in the cover layer is 5-150nm, and the porosity is 60-90%; And / or, the covering layer has a thickness of 2-50 nm.

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