Level-to-pulse activation circuit and charger

Abstract

The utility model provides a level-to-pulse activation circuit and a charger, the circuit comprises a time delay circuit, a driving circuit, a switch control circuit and an output circuit, the time delay circuit comprises a first resistor, a second resistor, a first field effect transistor and a first capacitor, and the driving circuit comprises a seventh resistor and a triode. According to the level-to-pulse activation circuit, when a charger is connected, the triode is turned on, at the moment, current sequentially passes through the fourth resistor and the triode to be grounded, the second field-effect tube is turned on, high level is output at the voltage output end, after the first capacitor is charged for a period of time, the first field-effect tube is turned on and grounded, and the triode and the second field-effect tube are sequentially turned off. Therefore, the voltage output end outputs low level, one pulse period is completed, the rising edge of the pulse signal is fast, and the voltage and the pulse width are appropriate. When the battery is powered on, the battery takes power from the charging anode, and when the battery is not charged, the charging anode has no voltage because the first field effect transistor and the triode are turned off, so that power consumption is avoided.

Description

Technical Field

[0001] The present disclosure relates to the technical field of charger charging, and in particular to a level-to-pulse activation circuit and a charger. Background Art

[0002] As people's environmental awareness increases, they gradually consciously choose greener travel methods that are more environmentally friendly and energy-saving, and lithium-ion batteries have emerged as a trend, occupying an important position in the field of new energy. In the lithium-ion battery industry, developers usually design intelligent battery management systems (BMS) in a shutdown state to reduce battery power consumption when not in use, avoid battery exhaustion, and extend battery life.

[0003] In current technology, the charging activation method mainly uses the principle that capacitors cannot change suddenly to produce a pulse voltage. However, this pulse voltage is greatly affected by the rising edge of the charger. If the rising edge of the charger is slow, after a specific period, the single pulse voltage flowing through the capacitor cannot meet expectations, resulting in the BMS being unable to activate and malfunctioning. Utility Model Content

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a level-to-pulse activation circuit and a charger that can make the rising edge of a pulse signal faster and have appropriate voltage and pulse width.

[0005] The purpose of this disclosure is achieved through the following technical solutions:

[0006] A level-to-pulse activation circuit, comprising:

[0007] A delay circuit, comprising a first resistor, a second resistor, a first field effect transistor and a first capacitor, wherein the first end of the second resistor is connected to a positive charging electrode, the first end of the second resistor is also connected to the first end of the first field effect transistor, the second end of the second resistor is respectively connected to a control end of the first field effect transistor, an upper half end of the first capacitor and the first end of the first resistor, the second end of the first resistor is connected to a negative charging electrode, the second end of the first field effect transistor is connected to a lower half end of the first capacitor, and the lower half end of the first capacitor is connected to the second end of the first resistor;

[0008] The driving circuit includes a seventh resistor and a transistor, wherein the first end of the first field effect transistor is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the control end of the transistor, and the second end of the transistor is connected to the negative charging electrode;

[0009] A switch control circuit, wherein the power connection terminal of the switch control circuit is connected to the positive charging electrode, and the connection terminal of the switch control circuit is connected to the first end of the transistor;

[0010] An output circuit, wherein the power connection end of the output circuit is electrically connected to the output end of the switch control circuit, and the voltage output end of the output circuit is used to output a pulse signal.

[0011] In one embodiment, the delay circuit further includes a third resistor, and the first end of the second resistor is connected to the first end of the first field effect transistor through the third resistor.

[0012] In one embodiment, the driving circuit further includes an eighth resistor, a first end of the eighth resistor is connected to the control end of the transistor, and a second end of the eighth resistor is connected to the second end of the transistor.

[0013] In one embodiment, the driving circuit further includes a second capacitor, an upper half of the second capacitor is connected to the first end of the eighth resistor, and a lower half of the second capacitor is connected to the second end of the eighth resistor.

[0014] In one embodiment, the switch control circuit includes a fourth resistor and a second field effect transistor, the first end of the fourth resistor is connected to the charging positive electrode, the first end of the second field effect transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the control end of the second field effect transistor and the first end of the transistor, and the second end of the second field effect transistor is electrically connected to the power connection end of the output circuit.

[0015] In one embodiment, the switch control circuit further includes a third capacitor, an upper half of the third capacitor is connected to the first end of the fourth resistor, and a lower half of the third capacitor is connected to the second end of the fourth resistor.

[0016] In one embodiment, the switch control circuit further includes a third voltage regulator tube, an anode of the third voltage regulator tube is connected to the lower half of the third capacitor, and a cathode of the third voltage regulator tube is connected to the upper half of the third capacitor.

[0017] In one embodiment, the output circuit includes a ninth resistor and a tenth resistor, the first end of the tenth resistor is connected to the output end of the switch control circuit, the second end of the tenth resistor is connected to the first end of the ninth resistor, the second end of the tenth resistor is connected to the voltage output end, and the second end of the ninth resistor is connected to the negative charging electrode.

[0018] In one embodiment, the output circuit further includes a second voltage regulator tube, an anode of the second voltage regulator tube is connected to the second end of the ninth resistor, and a cathode of the second voltage regulator tube is connected to the first end of the tenth resistor.

[0019] A charger comprises the level-to-pulse activation circuit described in any one of the above embodiments.

[0020] Compared with the prior art, the present invention has the following advantages, including but not limited to:

[0021] 1. When the charger is connected, the transistor is turned on due to the high level at its control end, and the first capacitor starts to charge. At this time, the current passes through the fourth resistor and the transistor to ground, and turns on the second field effect transistor, so that the voltage output end outputs a high level. After the first capacitor is charged for a period of time, the first field effect transistor is turned on and grounded, and the transistor and the second field effect transistor are turned off in turn, so that the voltage output end outputs a low level, thereby completing a pulse cycle. The pulse signal has a fast rising edge, and the voltage and pulse width are appropriate, which is sufficient to activate the BMS to charge the battery.

[0022] 2. When the level-to-pulse activation circuit is powered, the battery draws power from the positive charging electrode. When the battery is not charging, since the first field effect transistor and the transistor are turned off, there is no voltage at the positive charging electrode, so no power consumption is generated, achieving the purpose of energy saving, environmental protection and improving battery life. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 Schematic diagram of the structure of a level-to-pulse activation circuit in one embodiment.

[0025] : 10, level-to-pulse activation circuit; 100, delay circuit; 200, drive circuit; 300, switch control circuit; 400, output circuit; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R12, twelfth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; Q1, first field effect transistor; Q2, second field effect transistor; M1, triode; D1, general diode; D2, second voltage regulator; D3, third voltage regulator. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thoroughly and comprehensively understood.

[0027] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0029] In order to better understand the technical solutions and beneficial effects of the present invention, the present invention is further described in detail below in conjunction with specific embodiments:

[0030] See also Figure 1 , which is a level-to-pulse activation circuit 10 according to an embodiment of the present invention, including a delay circuit 100 , a drive circuit 200 , a switch control circuit 300 and an output circuit 400 .

[0031] The delay circuit 100 includes a first resistor R1, a second resistor R2, a first field effect transistor Q1 and a first capacitor C1, a first end of the second resistor R2 is connected to a positive charging electrode, a first end of the second resistor R2 is also connected to a first end of the first field effect transistor Q1, a second end of the second resistor R2 is respectively connected to a control end of the first field effect transistor Q1, an upper half end of the first capacitor C1 and a first end of the first resistor R1, a second end of the first resistor R1 is connected to a negative charging electrode, a second end of the first field effect transistor Q1 is connected to a lower half end of the first capacitor C1, and a lower half end of the first capacitor C1 is connected to a second end of the first resistor R1. In this embodiment, the first capacitor C1 is a storage capacitor, so that the first capacitor C1 controls the switch state of the first field effect transistor Q1 through a charge and discharge function.

[0032] The driving circuit 200 includes a seventh resistor R7 and a transistor M1. The first terminal of the first field effect transistor Q1 is connected to the first terminal of the seventh resistor R7. The second terminal of the seventh resistor R7 is connected to the control terminal of the transistor M1. The second terminal of the transistor M1 is connected to the negative charging electrode.

[0033] The power connection end of the switch control circuit 300 is connected to the positive charging electrode, and the connection end of the switch control circuit 300 is connected to the first end of the transistor M1. In this embodiment, the switch control circuit 300 includes a fourth resistor R4 and a second field effect transistor Q2. The first end of the fourth resistor R4 is connected to the positive charging electrode, the first end of the second field effect transistor Q2 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is respectively connected to the control end of the second field effect transistor Q2 and the first end of the transistor M1.

[0034] The power connection end of the output circuit 400 is electrically connected to the output end of the switch control circuit 300, and the voltage output end of the output circuit 400 is used to output a pulse signal. In this embodiment, the output circuit 400 includes a ninth resistor R9 and a tenth resistor R10, the first end of the tenth resistor R10 is connected to the output end of the switch control circuit 300, that is, the second end of the second field effect transistor Q2, the second end of the tenth resistor R10 is connected to the first end of the ninth resistor R9, and the second end of the tenth resistor R10 is also connected to the voltage output end, so that when the second field effect transistor Q2 is turned on, the corresponding current is output to the voltage output end to activate the BMS, and the second end of the ninth resistor R9 is connected to the negative charging electrode.

[0035] In this embodiment, when the level-to-pulse activation circuit 10 is connected to the charger, the transistor M1 is turned on due to the high level at its control end, and the first capacitor C1 starts to charge. At this time, the current passes through the fourth resistor R4 and the transistor M1 to ground in sequence, and the second field effect transistor Q2 is turned on, so that the voltage output end outputs a high level. After the first capacitor C1 is charged for a period of time, the first field effect transistor Q1 is turned on and grounded, and the transistor M1 and the second field effect transistor Q2 are turned off in sequence, so that the voltage output end outputs a low level, thereby completing a pulse cycle, and the pulse signal has a fast rising edge, and the voltage and pulse width are appropriate, which is sufficient to activate the BMS and charge the battery; when the level-to-pulse activation circuit 10 is powered on, the battery draws power from the charging positive electrode. When the battery is not charging, since the first field effect transistor Q1 and the transistor M1 are turned off, there is no voltage at the charging positive electrode, so that no power consumption is generated, thereby achieving the purpose of energy saving, environmental protection and improving battery life.

[0036] It can be understood that when the charger is connected, the current passes through the control end of the transistor M1, so that the control end of the transistor M1 reaches a high level and is then turned on. At this time, the current of the charging positive electrode passes through the fourth resistor R4 and the transistor M1 to ground in sequence, so that the control end of the second field effect transistor Q2 is at a low level and turned on. Subsequently, the current passes through the tenth resistor R10 and outputs a high level signal at the voltage output end; while the transistor M1 is turned on, the charger charges the first capacitor C1, and the first resistor R1 and the second resistor R2 divide the voltage to control the charging time of the first capacitor C1. When the predetermined time is reached, the first capacitor C1 is disconnected and the first field effect transistor Q1 is turned on. At this time, the current passes through the first field effect transistor Q1 to ground, so that the control end of the transistor M1 is at a low level and then turned off. The turning off of the transistor M1 causes the control end voltage of the second field effect transistor Q2 to be equal to the voltage of its first end, thereby turning off the second field effect transistor Q2. At this time, the voltage output end outputs a low level signal, completes a pulse cycle, and obtains a pulse signal to activate the BMS, so that the battery is charged.

[0037] In this embodiment, the first field effect transistor Q1 is an N-type MOS transistor, whose first end is a drain, whose second end is a source, and whose control end is a gate; the second field effect transistor Q2 is a P-type MOS transistor, whose first end is a source, whose second end is a drain, and whose control end is a gate; the transistor M1 is an NPN transistor, whose first end is a collector, whose second end is an emitter, and whose control end is a base.

[0038] Furthermore, the delay circuit 100 further includes a third resistor R3, and the first end of the second resistor R2 is connected to the first end of the first field effect transistor Q1 through the third resistor R3 to further protect the first field effect transistor Q1 and prevent the first field effect transistor Q1 from being broken down. At the same time, the third resistor R3 is connected in series with the seventh resistor R7 to further protect the control end of the transistor M1 and prevent the transistor M1 from being broken down due to excessive current.

[0039] Furthermore, the driving circuit 200 further includes an eighth resistor R8, a first end of the eighth resistor R8 is connected to the control end of the transistor M1, and a second end of the eighth resistor R8 is connected to the second end of the transistor M1. It can be understood that when the charger is turned on, the seventh resistor R7 and the eighth resistor R8 divide the voltage to turn on the transistor M1, and at the same time, the charger charges the first capacitor C1, and the first resistor R1, the second resistor R2 and the third resistor R3 divide the voltage to control the charging time of the first capacitor C1, and then according to the charging time of the first capacitor C1, the first field effect transistor Q1 is turned on and the transistor M1 is turned off, so as to complete a pulse cycle according to the high and low level states output by the voltage output terminal.

[0040] In one embodiment, the driving circuit 200 further includes a second capacitor C2, the upper half of the second capacitor C2 is connected to the first end of the eighth resistor R8, and the lower half of the second capacitor C2 is connected to the second end of the eighth resistor R8. It can be understood that the second capacitor C2 is connected in parallel with the eighth resistor R8 to form a resistor-capacitor circuit (RC circuit). When the transistor M1 is turned on, the second capacitor C2 can filter the control terminal voltage of the transistor M1 to avoid unnecessary signal interference and voltage mutation. At the same time, before the transistor M1 is turned on, it can be determined whether the transistor M1 is turned on based on whether the second capacitor C2 reaches the PN junction voltage of the transistor M1, that is, the voltage from the control terminal to the second terminal of the transistor M1.

[0041] Further, the switch control circuit 300 also includes a twelfth resistor R12, and the second end of the fourth resistor R4 is connected to the first end of the transistor M1 through the twelfth resistor R12. It can be understood that the twelfth resistor R12 is connected in series to the first end of the transistor M1 to further protect the transistor M1 and avoid the situation where a large current breaks down the transistor M1. Further, the switch control circuit 300 also includes a sixth resistor R6, and the sixth resistor R6 is arranged between the second end of the fourth resistor R4 and the control end of the second field effect transistor Q2 to further protect the second field effect transistor Q2 and further avoid the situation where the control end of the second field effect transistor Q2 is broken down due to the presence of an excessive voltage.

[0042] In one embodiment, the switch control circuit 300 further includes a third capacitor C3, the upper half of the third capacitor C3 is connected to the first end of the fourth resistor R4, and the lower half of the third capacitor C3 is connected to the second end of the fourth resistor R4. It can be understood that the third capacitor C3 and the fourth resistor R4 are connected in parallel to form an RC circuit, which can filter the voltage of the positive charging electrode to avoid interference from redundant signals and ensure that the second field effect tube Q2 is normally turned on or off.

[0043] In one embodiment, the switch control circuit 300 further includes a third voltage regulator tube D3, the anode of the third voltage regulator tube D3 is connected to the lower half of the third capacitor C3, and the cathode of the third voltage regulator tube D3 is connected to the upper half of the third capacitor C3. It can be understood that the third voltage regulator tube D3 is connected in parallel with the third capacitor C3, so that the voltage between the control end and the first end of the second field effect tube Q2 can be stabilized while the voltage can be filtered, so as to avoid voltage fluctuation or excessive voltage that damages the second field effect tube Q2, and ensure the normal operation of the second field effect tube Q2.

[0044] In order to enable the voltage output terminal to stably output a level signal, in one embodiment, the output circuit 400 further includes a second voltage regulator tube D2, the anode of the second voltage regulator tube D2 is connected to the second end of the ninth resistor R9, and the cathode of the second voltage regulator tube D2 is connected to the first end of the tenth resistor R10. It can be understood that the ninth resistor R9 and the tenth resistor R10 are connected in series, and the second voltage regulator tube D2 is connected in parallel to the above two resistors, so that when the second field effect tube Q2 is turned on, the voltage can be stabilized to a predetermined value, and when the voltage is stable, the voltage output terminal stably outputs a high-level signal through the voltage division of the ninth resistor R9 and the tenth resistor R10 to activate the BMS to charge the battery, and at the same time, it can prevent the situation where the voltage is too high and the battery is damaged due to the wrong charger being connected.

[0045] In order to ensure that the current outputted from the second end of the second field effect transistor Q2 flows in one direction, the output circuit 400 further includes a general diode D1, the anode of the general diode D1 is connected to the second end of the second field effect transistor Q2, and the cathode of the general diode D1 is connected to the first end of the tenth resistor R10. That is, the general diode D1 is connected in series with the tenth resistor R10, and when the second field effect transistor Q2 is turned on, the current sequentially passes through the general diode D1 and the tenth resistor R10 to output a high-level signal, thereby preventing the current from flowing back and damaging the circuit components.

[0046] The present disclosure also provides a charger, including any level-to-pulse activation circuit 10 of the above-mentioned embodiments. When the charger adopts the level-to-pulse activation circuit 10, the switch state of the second field effect transistor Q2 is determined by the cooperation of the first field effect transistor Q1 and the transistor M1, and then the high and low levels are output at the voltage output terminal to generate a pulse signal with a fast rising edge, appropriate voltage, and appropriate pulse width, so as to activate the BMS and stably charge the battery.

[0047] Compared with the prior art, the present invention has the following advantages, including but not limited to:

[0048] 1. When the charger is connected, the level-to-pulse activation circuit 10 is turned on due to the high level at its control end, and the first capacitor C1 starts to charge. At this time, the current passes through the fourth resistor R4 and the transistor M1 to ground, and turns on the second field effect transistor Q2, so that the voltage output end outputs a high level. After the first capacitor C1 is charged for a period of time, the first field effect transistor Q1 is turned on and grounded, and the transistor M1 and the second field effect transistor Q2 are turned off in turn, so that the voltage output end outputs a low level, thereby completing a pulse cycle, and the pulse signal has a fast rising edge, and the voltage and pulse width are appropriate, which is sufficient to activate the BMS and charge the battery.

[0049] 2. When the level-to-pulse activation circuit 10 is powered, the battery draws power from the positive charging electrode. When the battery is not charging, since the first field effect transistor Q1 and the transistor M1 are turned off, there is no voltage at the positive charging electrode, so no power consumption is generated, thereby achieving the purpose of energy saving, environmental protection and improving battery life.

[0050] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A level-to-pulse activation circuit, characterized in that: include: A delay circuit, comprising a first resistor, a second resistor, a first field effect transistor and a first capacitor, wherein the first end of the second resistor is connected to a positive charging electrode, the first end of the second resistor is also connected to the first end of the first field effect transistor, the second end of the second resistor is respectively connected to a control end of the first field effect transistor, an upper half end of the first capacitor and the first end of the first resistor, the second end of the first resistor is connected to a negative charging electrode, the second end of the first field effect transistor is connected to a lower half end of the first capacitor, and the lower half end of the first capacitor is connected to the second end of the first resistor; The driving circuit includes a seventh resistor and a transistor, wherein the first end of the first field effect transistor is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the control end of the transistor, and the second end of the transistor is connected to the negative charging electrode; A switch control circuit, wherein the power connection terminal of the switch control circuit is connected to the positive charging electrode, and the connection terminal of the switch control circuit is connected to the first end of the transistor; An output circuit, wherein the power connection end of the output circuit is electrically connected to the output end of the switch control circuit, and the voltage output end of the output circuit is used to output a pulse signal.

2. The level-to-pulse activation circuit according to claim 1, characterized in that: The delay circuit further includes a third resistor, and the first end of the second resistor is connected to the first end of the first field effect transistor through the third resistor.

3. The level-to-pulse activation circuit according to claim 1, characterized in that: The driving circuit further includes an eighth resistor, a first end of the eighth resistor is connected to the control end of the transistor, and a second end of the eighth resistor is connected to the second end of the transistor.

4. The level-to-pulse activation circuit according to claim 3, characterized in that: The driving circuit further includes a second capacitor, an upper half of the second capacitor is connected to the first end of the eighth resistor, and a lower half of the second capacitor is connected to the second end of the eighth resistor.

5. The level-to-pulse activation circuit according to claim 1, characterized in that: The switch control circuit includes a fourth resistor and a second field effect transistor, the first end of the fourth resistor is connected to the charging positive electrode, the first end of the second field effect transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the control end of the second field effect transistor and the first end of the transistor, and the second end of the second field effect transistor is electrically connected to the power connection end of the output circuit.

6. The level-to-pulse activation circuit according to claim 5, characterized in that: The switch control circuit further includes a third capacitor, an upper half of the third capacitor is connected to the first end of the fourth resistor, and a lower half of the third capacitor is connected to the second end of the fourth resistor.

7. The level-to-pulse activation circuit according to claim 6, characterized in that: The switch control circuit also includes a third voltage regulator tube, an anode of the third voltage regulator tube is connected to the lower half of the third capacitor, and a cathode of the third voltage regulator tube is connected to the upper half of the third capacitor.

8. The level-to-pulse activation circuit according to claim 1, characterized in that: The output circuit includes a ninth resistor and a tenth resistor, wherein the first end of the tenth resistor is connected to the output end of the switch control circuit, the second end of the tenth resistor is connected to the first end of the ninth resistor, the second end of the tenth resistor is connected to the voltage output end, and the second end of the ninth resistor is connected to the negative charging electrode.

9. The level-to-pulse activation circuit according to claim 8, characterized in that: The output circuit further includes a second voltage regulator tube, wherein an anode of the second voltage regulator tube is connected to the second end of the ninth resistor, and a cathode of the second voltage regulator tube is connected to the first end of the tenth resistor.

10. A charger, characterized in that: The invention comprises the level-to-pulse activation circuit as described in any one of claims 1 to 9.

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