UART receiving circuit and communication system

Abstract

The utility model provides a UART (Universal Asynchronous Receiver / Transmitter) receiving circuit and a communication system, the UART receiving circuit comprises an enable circuit and a level conversion circuit, the enable circuit comprises a first triode, a first resistor and a second resistor, and the level conversion circuit comprises a second triode, a third resistor and a fourth resistor. When the UART does not communicate, the partial voltage of the first resistor and the second resistor cannot reach the conduction condition of the first triode, at the moment, the signal output end outputs no voltage, and then the UART receiving circuit plays an isolation role in the absence of communication so as to protect the chip. During UART communication, the chip continuously identifies high and low levels and receives the high and low levels through continuous connection and disconnection of the first triode and the second triode so as to realize receiving of a data command, external high voltage can be converted into a voltage value which can be borne when the chip identifies the high level through the first triode and the second triode, and then the safety performance is good. And the risk of external short circuit is avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a UART receiving circuit and a communication system. Background Art

[0002] Universal Asynchronous Receiver / Transmitter, commonly known as UART (Universal Asynchronous Receiver / Transmitter), is an asynchronous receiver / transmitter and is part of computer hardware. In UART communication, two UARTs communicate directly with each other. The sending UART converts the parallel data from the control device such as the CPU into serial form and sends it serially to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs, and the data flows from the TX pin of the sending UART to the RX pin of the receiving UART. The RXD, TXD, etc. of the UART serial port are generally directly connected to the pins of the processor chip, while the RXD, TXD, etc. of the serial port of the computer we usually use generally need to be level converted before they can be connected to the pins of the processor chip.

[0003] In the prior art, bipolar transistors are usually used to input high-level voltage values, or MOS tubes are used to achieve level conversion. The above two schemes are relatively commonly used level conversion circuits in UART communication. However, in the absence of communication, the circuit interface still has voltage output to the outside, and there is a risk of external short circuit, which will damage the internal chip. Utility Model Content

[0004] The purpose of the present disclosure is to overcome the deficiencies in the prior art and to provide a UART receiving circuit and a communication system that has no external short circuit risk and has no external voltage output when there is no communication.

[0005] The purpose of this disclosure is achieved through the following technical solutions:

[0006] A UART receiving circuit, comprising:

[0007] An enabling circuit comprises a first transistor, a first resistor and a second resistor, wherein a first end of the first resistor is used to connect to a signal enabling end, a second end of the first resistor is respectively connected to a control end of the first transistor and a first end of the second resistor, a second end of the second resistor is connected to a second end of the first transistor, and the second end of the first transistor is grounded;

[0008] The level conversion circuit includes a second triode, a third resistor and a fourth resistor, wherein the first end of the second triode is connected to a reference power supply, the first end of the third resistor is connected to the first end of the second triode, the second end of the third resistor is respectively connected to the control end of the second triode and the first end of the first triode, the second end of the second triode is connected to the first end of the fourth resistor, the second end of the second triode is also used to connect to a signal output end, and the second end of the fourth resistor is grounded.

[0009] In one embodiment, the enabling circuit further includes a fifth resistor, a first end of the fifth resistor is connected to the second end of the third resistor, and a second end of the fifth resistor is connected to the first end of the first transistor.

[0010] In one embodiment, the fifth resistor is a variable resistor.

[0011] In one embodiment, at least one of the first resistor and the second resistor is a variable resistor.

[0012] In one embodiment, the third resistor is a variable resistor.

[0013] In one embodiment, the fourth resistor is a variable resistor.

[0014] In one embodiment, the first transistor is an NPN transistor.

[0015] In one embodiment, the second transistor is a PNP transistor.

[0016] In one embodiment, the signal enable terminal is a data receiving pin.

[0017] In one embodiment, the signal output terminal is a chip pin.

[0018] A communication system comprises the UART receiving circuit described in any one of the above embodiments.

[0019] Compared with the prior art, the present invention has at least the following advantages:

[0020] 1. According to the conduction characteristics of the transistor, when the universal asynchronous receiver and transmitter UART has no communication, the voltage division of the first resistor and the second resistor cannot reach the conduction condition of the first transistor. At this time, there is no voltage output at the signal output end, and then the UART receiving circuit plays an isolation role in the absence of communication to protect the chip.

[0021] 2. When UART communicates, the UART receiving circuit continuously turns on and off the first transistor and the second transistor, and the chip continuously recognizes and receives high and low levels to realize the reception of data commands. The external high voltage can be converted into a voltage value that the chip can withstand when it recognizes a high level through the first transistor and the second transistor, thereby having better safety performance and avoiding the risk of external short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 FIG. 4 is a schematic diagram of the structure of a UART receiving circuit in an embodiment.

[0024] Figure numerals: 10, UART receiving circuit; 100, enabling circuit; 200, level conversion circuit; RX6, first resistor; RX8, second resistor; RX4, third resistor; RX7, fourth resistor; RX5, fifth resistor; QX1, first transistor; QX2, second transistor; RXD, receiving data pin; RXD_MSP, chip pin. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thoroughly and comprehensively understood.

[0026] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0028] In order to better understand the technical solutions and beneficial effects of the present invention, the present invention is further described in detail below in conjunction with specific embodiments:

[0029] See also Figure 1 , which is a UART receiving circuit 10 according to an embodiment of the utility model, includes an enabling circuit 100 and a level conversion circuit 200 .

[0030] The enabling circuit 100 includes a first transistor QX1, a first resistor RX6 and a second resistor RX8. The first end of the first resistor RX6 is used to connect to the signal enable end, the second end of the first resistor RX6 is respectively connected to the control end of the first transistor QX1 and the first end of the second resistor RX8, the second end of the second resistor RX8 is connected to the second end of the first transistor QX1, and the second end of the first transistor QX1 is grounded.

[0031] The level conversion circuit 200 includes a second transistor QX2, a third resistor RX4 and a fourth resistor RX7. The first end of the second transistor QX2 is connected to a reference power supply, the first end of the third resistor RX4 is connected to the first end of the second transistor QX2, the second end of the third resistor RX4 is respectively connected to the control end of the second transistor QX2 and the first end of the first transistor QX1, the second end of the second transistor QX2 is connected to the first end of the fourth resistor RX7, the second end of the second transistor QX2 is also used to connect to the signal output end, and the second end of the fourth resistor RX7 is grounded.

[0032] In this embodiment, the UART receiving circuit 10 can be based on the conduction characteristics of the transistor. When the universal asynchronous receiver / transmitter UART is not communicating, the voltage division of the first resistor RX6 and the second resistor RX8 cannot reach the conduction condition of the first transistor QX1. At this time, there is no voltage output at the signal output end, and the UART receiving circuit 10 plays an isolation role in the absence of communication to protect the chip; in addition, when the UART is communicating, the UART receiving circuit 10 continuously turns on and off the first transistor QX1 and the second transistor QX2, and the chip continuously recognizes high and low levels and receives them to realize the reception of data commands. The external high voltage can be converted into a voltage value that the chip can withstand when recognizing a high level through the first transistor QX1 and the second transistor QX2, so that the safety performance is better and the risk of external short circuit is avoided.

[0033] It can be understood that when the UART is not communicating, there is a low-level signal at the signal enable end, and the low-level signal is connected to the ground through the first resistor RX6 and the second resistor RX8 in sequence. Since the control end of the first transistor QX1 is at a low level, the conduction condition of the first transistor QX1 is not met and it cannot be turned on, so the voltage of the first transistor QX1 is zero, and the UART receiving circuit 10 does not have a current loop formed from the reference power supply to the ground, and then the second transistor QX2 cannot be turned on. In this way, in the state of no communication, the UART receiving circuit 10 can isolate the external voltage and realize the function of no voltage output to protect the chip; when the UART is communicating, there is a high-level input at the signal enable end, and the current is connected to the ground through the first resistor RX6 and the second resistor RX8 in sequence, and at the same time passes through the first resistor RX 6 and the second resistor RX8, a voltage drop is generated in the second resistor RX8, thereby turning on the first transistor QX1. The current of the reference power supply passes through the third resistor RX4 and the first transistor QX1 in sequence and then is grounded. At this time, the voltage between the control end and the first end of the second transistor QX2 (that is, the voltage Vbe between the base and the emitter) is greater than the minimum voltage required for the conduction of the second transistor QX2, thereby turning on the second transistor QX2. The current of the reference power supply passes through the second transistor QX2 and the fourth resistor RX7 in sequence and is grounded, and after passing through the second end of the second transistor QX2, a high-level signal is output from the signal output end. The chip can recognize the high-level signal, and the settings of the first transistor QX1 and the second transistor QX2 can protect the chip. Therefore, when in the high-level state, the chip can also be recognized normally. During communication, the signal received by the universal asynchronous receiver / transmitter (UART) is usually a high level, low level, high level, low level cycle signal. Therefore, the first transistor QX1 and the second transistor QX2 are also in a cycle state of on, off, on, off, and the signal output end outputs a high level, low level, high level, low level cycle signal, and the chip can recognize the corresponding cycle signal.

[0034] Furthermore, the first transistor QX1 is an NPN transistor, whose first end is the collector, the second end is the emitter, and the control end is the base; the second transistor QX2 is a PNP transistor, whose first end is the emitter, the second end is the collector, and the control end is the base.

[0035] In one embodiment, the enabling circuit 100 further includes a fifth resistor RX5, a first end of the fifth resistor RX5 is connected to the second end of the third resistor RX4, and a second end of the fifth resistor RX5 is connected to the first end of the first transistor QX1. It can be understood that the fifth resistor RX5 is connected in series to the first end of the first transistor QX1, and when the first transistor QX1 is turned on, the third resistor RX4 and the fifth resistor RX5 are in a series relationship. The setting of the fifth resistor RX5 can further protect the first end of the first transistor QX1, and further reduce the possibility of the first transistor QX1 being broken down by an excessive current.

[0036] In one embodiment, the fifth resistor RX5 is a variable resistor. In this embodiment, when the fifth resistor RX5 is a variable resistor, the voltage at the first end of the first transistor QX1 when it is turned on can be adjusted by adjusting the resistance value of the fifth resistor RX5, so as to ensure that the first transistor QX1 is normally turned on when the turn-on condition is met.

[0037] In one embodiment, at least one of the first resistor RX6 and the second resistor RX8 is a variable resistor. In this embodiment, when one or both of the first resistor RX6 and the second resistor RX8 are variable resistors, the resistance ratio of the first resistor RX6 and the second resistor RX8 can be adjusted by adjusting the resistance value of one or both of the first resistor RX6 and the second resistor RX8, thereby adjusting the conduction condition of the first transistor QX1 to adapt to more models of the first transistor QX1.

[0038] In one embodiment, the third resistor RX4 is a variable resistor. In this embodiment, when the third resistor RX4 is a variable resistor, the resistance value of the third resistor RX4 can be adjusted to adjust the conduction condition of the second transistor QX2 to adapt to more models of the second transistor QX2.

[0039] In one embodiment, the fourth resistor RX7 is a variable resistor. In this embodiment, when the fourth resistor RX7 is a variable resistor, the voltage of the second end of the second triode QX2 when the second triode QX2 is turned on can be adjusted by adjusting the resistance value of the fourth resistor RX7, so as to ensure that the second triode QX2 can be turned on normally when the turn-on condition of the second triode QX2 is met, and the voltage of the second end of the second triode QX2 is within the tolerable voltage range.

[0040] In one embodiment, the signal enable terminal is the receive data pin RXD. It can be understood that in the universal asynchronous receiver-transmitter (UART) communication, two UARTs communicate directly with each other, and data flows from the TX pin (transmit data pin) of the UART responsible for sending to the RX pin (receive data pin) of the UART responsible for receiving. Therefore, when one of the UARTs sends data, the other UART will receive data from the receive data pin and then output it to the chip through level conversion.

[0041] In one embodiment, the signal output terminal is the chip pin RXD_MSP. It can be understood that when the UART responsible for receiving information receives data, it will receive the signal from the receiving data pin, and then through the level conversion, that is, through the first transistor QX1 and the second transistor QX2, the level is converted and then the data is transmitted to the chip through the chip pin.

[0042] The present disclosure also provides a communication system, including the UART receiving circuit 10 of any one of the above embodiments. When the communication system adopts the UART receiving circuit 10, when the UART is not communicating, the first transistor QX1 and the second transistor QX2 can be used to isolate the circuit to ensure that the circuit interface has no voltage output to the outside.

[0043] Compared with the prior art, the present invention has at least the following advantages:

[0044] 1. According to the conduction characteristics of the transistor, when the universal asynchronous receiver / transmitter UART is not communicating, the voltage division of the first resistor RX6 and the second resistor RX8 cannot reach the conduction condition of the first transistor QX1. At this time, there is no voltage output at the signal output end, and then the UART receiving circuit 10 plays an isolation role in the absence of communication to protect the chip.

[0045] 2. When UART communicates, the UART receiving circuit 10 continuously turns on and off the first transistor QX1 and the second transistor QX2, and the chip continuously recognizes and receives high and low levels to realize the reception of data commands. The external high voltage can be converted into a voltage value that the chip can withstand when recognizing a high level through the first transistor QX1 and the second transistor QX2, thereby having better safety performance and avoiding the risk of external short circuit.

[0046] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A UART receiving circuit (10), characterized in that: include: An enabling circuit (100) comprises a first transistor (QX1), a first resistor (RX6) and a second resistor (RX8), wherein a first end of the first resistor (RX6) is used to connect to a signal enabling end, a second end of the first resistor (RX6) is respectively connected to a control end of the first transistor (QX1) and a first end of the second resistor (RX8), a second end of the second resistor (RX8) is connected to a second end of the first transistor (QX1), and the second end of the first transistor (QX1) is grounded; A level conversion circuit (200) comprises a second triode (QX2), a third resistor (RX4) and a fourth resistor (RX7), wherein a first end of the second triode (QX2) is connected to a reference power supply, a first end of the third resistor (RX4) is connected to a first end of the second triode (QX2), a second end of the third resistor (RX4) is respectively connected to a control end of the second triode (QX2) and a first end of the first triode (QX1), a second end of the second triode (QX2) is connected to a first end of the fourth resistor (RX7), a second end of the second triode (QX2) is also used to connect to a signal output end, and a second end of the fourth resistor (RX7) is grounded.

2. The UART receiving circuit (10) according to claim 1, characterized in that: The enabling circuit (100) further comprises a fifth resistor (RX5), a first end of the fifth resistor (RX5) being connected to a second end of the third resistor (RX4), and a second end of the fifth resistor (RX5) being connected to a first end of the first transistor (QX1).

3. The UART receiving circuit (10) according to claim 2, characterized in that: The fifth resistor (RX5) is a variable resistor.

4. The UART receiving circuit (10) according to claim 1, characterized in that: At least one of the first resistor (RX6) and the second resistor (RX8) is a variable resistor.

5. The UART receiving circuit (10) according to claim 1, characterized in that: The third resistor (RX4) is a variable resistor.

6. The UART receiving circuit (10) according to claim 1, characterized in that: The fourth resistor (RX7) is a variable resistor.

7. The UART receiving circuit (10) according to claim 1, characterized in that: The first transistor (QX1) is an NPN transistor; and / or, The second transistor (QX2) is a PNP transistor.

8. The UART receiving circuit (10) according to claim 1, characterized in that: The signal enable terminal is a receive data pin (RXD).

9. The UART receiving circuit (10) according to claim 1, characterized in that: The signal output terminal is a chip pin (RXD_MSP).

10. A communication system, characterized in that: The invention comprises the UART receiving circuit (10) as claimed in any one of claims 1 to 9.

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