Array substrate and display panel
By providing the first sub-part of the conductive auxiliary layer between the buffer layer and the semiconductor layer, the problem of insufficient conduction processing in traditional thin film transistors is solved, and the open-state current and display effect are improved.
Patent Information
- Application Number
- CN202421739297.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-22
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-07-22
AI Technical Summary
In the thin film transistor with a traditional top gate structure, the light shielding layer design causes a segment difference between the channel part and the conductor part, affecting the conductionization process, resulting in a decrease in the open-state current of the thin film transistor, and affecting the display effect.
By providing a first sub-part of the conductive auxiliary layer between the buffer layer and the semiconductor layer, the conductive performance of the semiconductor layer is enhanced, thereby improving the open-state current of the thin film transistor.
The open-state current of thin film transistors is improved, the display effect is improved, and the light and dark fringes are reduced.
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Figure CN222827581U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art
[0002] In order to prepare a high-performance display panel, a high-performance array substrate is required. The array substrate includes a plurality of thin film transistors. In a conventional top-gate thin film transistor, the semiconductor layer includes a connected channel portion and a conductor portion. In order to reduce leakage current, a light shielding layer is usually provided under the channel portion.
[0003] However, the design of the light shielding layer raises the channel part, resulting in a step difference between the channel part and the conductor part. In the process of manufacturing the array substrate, when the conductor part is subjected to conductorization, a portion of the conductor part that is not parallel to the plane where the substrate is located cannot be fully subjected to conductorization, which reduces the on-state current of the thin film transistor and affects the display effect.
[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content
[0005] The purpose of the present application is to provide an array substrate and a display panel, which can increase the on-state current of a thin film transistor, thereby improving the display effect.
[0006] To solve the above problems, the technical solution of this application is as follows:
[0007] The present application proposes a display panel, comprising:
[0008] substrate;
[0009] A light shielding layer, disposed on one side of the substrate;
[0010] A buffer layer, disposed on one side of the substrate and covering the light shielding layer, wherein the buffer layer comprises a first buffer portion, and the first buffer portion is disposed on a side of the light shielding layer;
[0011] a conductive auxiliary layer, comprising a first sub-portion, wherein the first sub-portion is disposed on a side of the first buffer portion away from the light shielding layer; and
[0012] A thin film transistor is arranged on a side of the buffer layer away from the substrate, and comprises a semiconductor layer. The semiconductor layer is arranged on a side of the buffer layer away from the substrate and covers at least the first sub-portion.
[0013] In one embodiment of the present application, the buffer layer further includes a second buffer portion and a third buffer portion; the second buffer portion is disposed on a side of the light shielding layer away from the substrate and connected to the first buffer portion; the third buffer portion is disposed on one side of the substrate and connected to the first buffer portion;
[0014] The semiconductor layer includes a channel portion and a conductor portion; the channel portion is arranged on a side of the second buffer portion away from the substrate; the conductor portion is connected to the channel portion, and at least a portion of the conductor portion covers the first sub-portion.
[0015] In one embodiment of the present application, the conductive auxiliary layer further includes a second sub-portion, the second sub-portion is disposed on a side of the third buffer portion away from the substrate, and the second sub-portion is connected to the first sub-portion;
[0016] Wherein, at least a portion of the conductor portion covers the first sub-portion and the second sub-portion.
[0017] In one embodiment of the present application, the conductor portion includes:
[0018] a first sub-segment, disposed on a side of the first sub-portion away from the first buffer portion, the first sub-segment being connected to the channel portion; and
[0019] The second sub-segment is arranged at a side of the second sub-portion away from the third buffer portion, and the second sub-segment is connected to the first sub-segment.
[0020] In one embodiment of the present application, the conductive auxiliary layer further includes a third sub-portion, the third sub-portion is disposed on a side of the second buffer portion away from the light shielding layer, and the third sub-portion is connected to the first sub-portion;
[0021] Wherein, at least a portion of the conductor portion covers the first sub-portion, the second sub-portion, and the third sub-portion.
[0022] In one embodiment of the present application, the conductor portion includes:
[0023] A first subsection, disposed on a side of the first subsection away from the first buffer section;
[0024] A second sub-section is provided at a side of the second sub-portion away from the third buffer portion; and
[0025] a third subsection, arranged at a side of the third subsection away from the second buffer section;
[0026] The first sub-segment connects the second sub-segment and the third sub-segment, and the third sub-segment is connected to the channel portion.
[0027] In one embodiment of the present application, the angle formed by the extension direction of the first sub-portion and the plane where the substrate is located is in the range of 20 degrees to 70 degrees; and / or,
[0028] The thickness of the conductive auxiliary layer is in the range of 100 angstroms to 1000 angstroms.
[0029] In one embodiment of the present application, the conductive auxiliary layer includes a metal layer; or,
[0030] The conductive auxiliary layer includes a metal oxide layer.
[0031] In one embodiment of the present application, the thin film transistor further includes:
[0032] A gate insulating layer, disposed on a side of the semiconductor layer away from the substrate;
[0033] A gate, disposed on a side of the gate insulating layer away from the substrate;
[0034] an interlayer dielectric layer, disposed on a side of the buffer layer away from the substrate and covering the gate, the gate insulating layer and the semiconductor layer;
[0035] a source electrode, a portion of which is disposed on a side of the interlayer dielectric layer away from the substrate, and another portion of which passes through the interlayer dielectric layer and is connected to the semiconductor layer; and
[0036] A drain electrode, a portion of which is disposed on a side of the interlayer dielectric layer away from the substrate, and another portion of which passes through the interlayer dielectric layer and is connected to the semiconductor layer.
[0037] The present application proposes a display panel, comprising an array substrate, wherein the array substrate comprises a substrate, a light-shielding layer, a buffer layer, a conductive auxiliary layer and a thin film transistor; the light-shielding layer is arranged on one side of the substrate; the buffer layer is arranged on one side of the substrate and covers the light-shielding layer, the buffer layer comprises a first buffer portion, the first buffer portion is arranged on the side of the light-shielding layer; the conductive auxiliary layer comprises a first sub-portion, the first sub-portion is arranged on a side of the first buffer portion away from the light-shielding layer; the thin film transistor is arranged on a side of the buffer layer away from the substrate, the thin film transistor comprises a semiconductor layer, the semiconductor layer is arranged on a side of the buffer layer away from the substrate and at least covers the first sub-portion.
[0038] In the present application, the semiconductor layer on the side of the first buffer away from the side of the light shielding layer is a part that is not fully conductive. The present application enhances the conductivity of the semiconductor layer by arranging the first sub-portion of the conductive auxiliary layer between the first buffer and the semiconductor layer, thereby increasing the on-state current of the thin film transistor and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 is a schematic diagram of a conventional array substrate;
[0040] Figure 2 is a schematic diagram of a first embodiment of an array substrate of the present application;
[0041] Figure 3 is a schematic diagram of a second embodiment of an array substrate of the present application;
[0042] Figure 4 is a schematic diagram of a third embodiment of an array substrate of the present application;
[0043] Figure 5 It is a schematic diagram of a fourth embodiment of the array substrate of the present application. DETAILED DESCRIPTION
[0044] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.
[0045] See also Figure 1 , a conventional array substrate 100a includes a substrate 10a, a light shielding layer 20a, a buffer layer 30a and a thin film transistor 50a. The light shielding layer 20a is disposed on one side of the substrate 10a. The buffer layer 30a is disposed on one side of the substrate 10a and covers the light shielding layer 20a. The buffer layer 30a includes a first buffer portion 31a, which is disposed on the side of the light shielding layer 20a. The thin film transistor 50a includes a semiconductor layer 51a. A portion of the semiconductor layer 51a covers the first buffer portion 31a.
[0046] In the conventional array substrate 100a, since the angle formed by the extension direction of the first buffer portion 31a and the plane where the substrate 10a is located is greater than 0 degrees, during the process of conducting the semiconductor layer 51a, the conductorization of the part of the semiconductor layer 51a disposed on the first buffer portion 31a is insufficient, so that the impedance of the part of the semiconductor layer 51a disposed on the first buffer portion 31a is relatively large, resulting in a decrease in the on-state current of the thin film transistor 50a, and the appearance of light and dark stripes (Mura phenomenon) during the display of the display panel, which affects the display effect.
[0047] The present application proposes a display panel, which may be a liquid crystal display panel (LCD) or an organic light emitting diode (OLED) display panel. The display panel includes an array substrate 100 .
[0048] See also Figure 2, the present application proposes an array substrate 100. The array substrate 100 of the present application includes a substrate 10, a light shielding layer 20, a buffer layer 30, a conductive auxiliary layer 40 and a thin film transistor 50. The light shielding layer 20 is arranged on one side of the substrate 10. The buffer layer 30 is arranged on one side of the substrate 10 and covers the light shielding layer 20. The buffer layer 30 includes a first buffer portion 31, and the first buffer portion 31 is arranged on the side of the light shielding layer 20. The conductive auxiliary layer 40 includes a first sub-portion 41, and the first sub-portion 41 is arranged on the side of the first buffer portion 31 away from the light shielding layer 20. The thin film transistor 50 is arranged on the side of the buffer layer 30 away from the substrate 10. The thin film transistor 50 includes a semiconductor layer 51, and the semiconductor layer 51 is arranged on the side of the buffer layer 30 away from the substrate 10 and at least covers the first sub-portion 41.
[0049] In the present application, the semiconductor layer 51 on the side of the first buffer portion 31 away from the side of the light shielding layer 20 is a part that is not sufficiently conductive. In the present application, the first sub-portion 41 of the conductive auxiliary layer 40 is arranged between the first buffer portion 31 and the semiconductor layer 51, so as to enhance the conductivity of the semiconductor layer 51, thereby increasing the on-state current of the thin film transistor 50 and improving the display effect.
[0050] Optionally, the thin film transistor 50 further includes a gate insulating layer 54, a gate 55, an interlayer dielectric layer 56, a source 57 and a drain 58. The gate insulating layer 54 is disposed on a side of the semiconductor layer 51 away from the substrate 10. The gate 55 is disposed on a side of the gate insulating layer 54 away from the substrate 10. The interlayer dielectric layer 56 is disposed on a side of the buffer layer 30 away from the substrate 10, and covers the gate 55, the gate insulating layer 54 and the semiconductor layer 51. A portion of the source 57 is disposed on a side of the interlayer dielectric layer 56 away from the substrate 10, and another portion of the source 57 passes through the interlayer dielectric layer 56 to connect to the semiconductor layer 51. A portion of the drain 58 is disposed on a side of the interlayer dielectric layer 56 away from the substrate 10, and another portion of the drain 58 passes through the interlayer dielectric layer 56 to connect to the semiconductor layer 51.
[0051] Optionally, any one conductive auxiliary layer 40 is only connected to the conductor portion 53 of the semiconductor layer 51 of one thin film transistor 50; and any one conductive auxiliary layer 40 is only electrically connected to one of the source 57 or the drain 58 of one thin film transistor 50. This prevents short circuits and improves the stability of the array substrate 100.
[0052] Optionally, the conductive auxiliary layer 40 includes at least one metal layer. The material of the metal layer includes at least one of aluminum, titanium, copper, iron, and molybdenum. In the design where the conductive auxiliary layer 40 includes a metal layer, the conductive performance of the semiconductor layer 51 can be enhanced, thereby increasing the on-state current of the thin film transistor 50 and improving the display effect.
[0053] Optionally, the conductive auxiliary layer 40 includes at least one metal oxide layer. The material of the metal oxide layer includes indium tin oxide. In the design that the conductive auxiliary layer 40 includes the metal oxide layer, on the one hand, the conductive performance of the semiconductor layer 51 can be enhanced, the on-state current of the thin film transistor 50 can be increased, and the display effect can be improved. On the other hand, indium tin oxide is a transparent film layer, which can increase the transmittance of the array substrate 100, thereby improving the display effect.
[0054] Optionally, the angle α between the plane where the sidewall of the light shielding layer 20 is located and the plane where the substrate 10 is located is in the range of 20 degrees to 70 degrees. The angle α formed by the extension direction of the first sub-portion 41 and the plane where the substrate 10 is located is a value among 20 degrees, 25 degrees, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, and 70 degrees.
[0055] Optionally, the angle β formed by the extension direction of the first sub-portion 41 and the plane where the substrate 10 is located is in the range of 20 degrees to 70 degrees. The angle β formed by the extension direction of the first sub-portion 41 and the plane where the substrate 10 is located is a value of 20 degrees, 25 degrees, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, and 70 degrees.
[0056] In the process of forming the conductive auxiliary layer 40, a continuous metal layer or metal oxide layer will first be formed on the buffer layer 30. Among them, the part of the continuous metal layer or metal oxide layer located on the first buffer part 31 forms an angle β with the plane where the substrate 10 is located. The continuous metal layer or metal oxide layer is etched. After the etching is completed, the metal layer located on the first buffer part 31 cannot be completely etched due to the weak etching effect, thereby forming the conductive auxiliary layer 40. The extension direction of the metal layer located on the second buffer part 32 and the third buffer part 33 is parallel to the substrate 10, and the etching effect is strong, so it is completely etched away. In this embodiment, the conductive auxiliary layer 40 is formed without the use of an additional mask, which can reduce production costs and save a mask process.
[0057] Correspondingly, as the angle α between the plane where the sidewall of the light shielding layer 20 is located and the plane where the substrate 10 is located increases, when the etching conditions remain unchanged, the thickness of the conductive auxiliary layer 40 formed after etching also increases. In the present application, the thickness of the conductive auxiliary layer 40 after etching is in the range of 50% to 95% of the thickness of the metal layer or metal oxide layer before etching.
[0058] Optionally, the thickness of the conductive auxiliary layer 40 is in the range of 100 angstroms to 1000 angstroms. The thickness of the conductive auxiliary layer 40 is one of 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, and 1000 angstroms.
[0059] Optionally, when the etching conditions remain unchanged, as the angle β formed by the extension direction of the first sub-portion 41 and the plane where the substrate 10 is located increases, the thickness of the conductive auxiliary layer 40 also increases. The increase in the thickness of the conductive auxiliary layer 40 can further improve the conductivity of the conductor portion 53 of the semiconductor layer 51.
[0060] Optionally, the buffer layer 30 further includes a second buffer portion 32 and a third buffer portion 33. The second buffer portion 32 is disposed on a side of the light shielding layer 20 away from the substrate 10 and connected to the first buffer portion 31. The third buffer portion 33 is disposed on a side of the substrate 10 and connected to the first buffer portion 31. The semiconductor layer 51 includes a channel portion 52 and a conductor portion 53. The channel portion 52 is disposed on a side of the second buffer portion 32 away from the substrate 10. The conductor portion 53 is connected to the channel portion 52, and at least a portion of the conductor portion 53 covers the first sub-portion 41.
[0061] The first sub-section 41 is stacked with the insufficiently conductive portion of the conductor section 53 , thereby reducing the impedance of the conductor section 53 , enhancing the conductivity of the semiconductor layer 51 , increasing the on-state current of the thin film transistor 50 , and improving the display effect.
[0062] Optional, see Figure 2 In the first embodiment of the present application, the conductor portion 53 includes a first sub-segment 531 and a second sub-segment 532. The first sub-segment 531 is disposed on a side of the first sub-portion 41 away from the first buffer portion 31, and the first sub-segment 531 is connected to the channel portion 52. The second sub-segment 532 is disposed on a side of the second sub-portion 42 away from the third buffer portion 33, and the second sub-segment 532 is connected to the first sub-segment 531.
[0063] In the first embodiment of the present application, the impedance of the first sub-segment 531 is relatively large because the first sub-segment 531 is an insufficiently conductive portion of the conductor portion 53. In this embodiment, the first sub-segment 41 of the conductive auxiliary layer 40 is stacked with the first sub-segment 531 to reduce the impedance of the conductor portion 53, enhance the conductivity of the semiconductor layer 51, increase the on-state current of the thin film transistor 50, and improve the display effect.
[0064] Optional, see Figure 3In the second embodiment of the present application, the conductor portion 53 includes a first sub-segment 531, a second sub-segment 532, and a third sub-segment 533. The first sub-segment 531 is disposed on a side of the first sub-portion 41 away from the first buffer portion 31. The second sub-segment 532 is disposed on a side of the second sub-portion 42 away from the third buffer portion 33. The third sub-segment 533 is disposed on a side of the third sub-portion 43 away from the second buffer portion 32. The first sub-segment 531 connects the second sub-segment 532 and the third sub-segment 533, and the third sub-segment 533 is connected to the channel portion 52.
[0065] In the second embodiment of the present application, the impedance of the first sub-segment 531 is relatively large because the first sub-segment 531 is an insufficiently conductive portion of the conductor portion 53. In this embodiment, the first sub-segment 41 of the conductive auxiliary layer 40 is stacked with the first sub-segment 531 to reduce the impedance of the conductor portion 53, enhance the conductivity of the semiconductor layer 51, increase the on-state current of the thin film transistor 50, and improve the display effect.
[0066] Optional, see Figure 4 In the third embodiment of the present application, the conductor portion 53 includes a first sub-segment 531, a second sub-segment 532, and a third sub-segment 533. The first sub-segment 531 is disposed on a side of the first sub-portion 41 away from the first buffer portion 31. The second sub-segment 532 is disposed on a side of the second sub-portion 42 away from the third buffer portion 33. The third sub-segment 533 is disposed on a side of the third sub-portion 43 away from the second buffer portion 32. The first sub-segment 531 connects the second sub-segment 532 and the third sub-segment 533, and the third sub-segment 533 is connected to the channel portion 52.
[0067] The conductive auxiliary layer 40 includes a first sub-portion 41 and a second sub-portion 42. The first sub-portion 41 is disposed on a side of the first buffer portion 31 away from the light shielding layer 20. The second sub-portion 42 is disposed on a side of the third buffer portion 33 away from the substrate 10. The second sub-portion 42 is connected to the first sub-portion 41. At least part of the conductor portion 53 covers the first sub-portion 41 and the second sub-portion 42.
[0068] Optionally, the first sub-segment 531 covers the first sub-portion 41 , and the second sub-segment 532 covers the second sub-portion 42 .
[0069] In the third embodiment of the present application, the impedance of the first sub-segment 531 is relatively large because the first sub-segment 531 is an insufficiently conductive portion of the conductor portion 53. In this embodiment, the first sub-segment 41 of the conductive auxiliary layer 40 is stacked with the first sub-segment 531 to reduce the impedance of the conductor portion 53, enhance the conductivity of the semiconductor layer 51, increase the on-state current of the thin film transistor 50, and improve the display effect.
[0070] At the same time, in the third embodiment, the second sub-section 42 and the second sub-segment 532 are stacked, thereby reducing the impedance of the second sub-segment 532, further reducing the impedance of the conductor portion 53, enhancing the conductive properties of the semiconductor layer 51, further increasing the on-state current of the thin film transistor 50, and improving the display effect.
[0071] Optional, see Figure 5 In the fourth embodiment of the present application, the conductor portion 53 includes a first sub-segment 531, a second sub-segment 532, and a third sub-segment 533. The first sub-segment 531 is disposed on a side of the first sub-portion 41 away from the first buffer portion 31. The second sub-segment 532 is disposed on a side of the second sub-portion 42 away from the third buffer portion 33. The third sub-segment 533 is disposed on a side of the third sub-portion 43 away from the second buffer portion 32. The first sub-segment 531 connects the second sub-segment 532 and the third sub-segment 533, and the third sub-segment 533 is connected to the channel portion 52.
[0072] The conductive auxiliary layer 40 includes a first sub-portion 41, a second sub-portion 42 and a third sub-portion 43. The first sub-portion 41 is disposed on a side of the first buffer portion 31 away from the light shielding layer 20. The second sub-portion 42 is disposed on a side of the third buffer portion 33 away from the substrate 10. The second sub-portion 42 is connected to the first sub-portion 41. The third sub-portion 43 is disposed on a side of the second buffer portion 32 away from the light shielding layer 20. The third sub-portion 43 is connected to the first sub-portion 41.
[0073] Optionally, the first sub-segment 531 covers the first sub-portion 41 , the second sub-segment 532 covers the second sub-portion 42 , and the third sub-segment 533 covers the third sub-portion 43 .
[0074] In the fourth embodiment of the present application, the impedance of the first sub-segment 531 is relatively large because the first sub-segment 531 is an insufficiently conductive portion of the conductor portion 53. In this embodiment, the first sub-segment 41 of the conductive auxiliary layer 40 is stacked with the first sub-segment 531 to reduce the impedance of the conductor portion 53, enhance the conductivity of the semiconductor layer 51, increase the on-state current of the thin film transistor 50, and improve the display effect.
[0075] At the same time, in the fourth embodiment, the second sub-section 42 and the second sub-segment 532 are stacked, thereby reducing the impedance of the second sub-segment 532, thereby further reducing the impedance of the conductor portion 53, enhancing the conductive properties of the semiconductor layer 51, further increasing the on-state current of the thin film transistor 50, and improving the display effect.
[0076] At the same time, in the fourth embodiment, the third sub-section 43 and the third sub-segment 533 are stacked, thereby reducing the impedance of the third sub-segment 533, further reducing the impedance of the conductor portion 53, enhancing the conductive properties of the semiconductor layer 51, further increasing the on-state current of the thin film transistor 50, and improving the display effect.
[0077] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.
Claims
1. An array substrate, characterized in that: include: substrate; A light shielding layer, disposed on one side of the substrate; A buffer layer, disposed on one side of the substrate and covering the light shielding layer, wherein the buffer layer comprises a first buffer portion, and the first buffer portion is disposed on a side of the light shielding layer; A conductive auxiliary layer, comprising a first sub-portion, wherein the first sub-portion is arranged on a side of the first buffer portion away from the light shielding layer; as well as A thin film transistor is arranged on a side of the buffer layer away from the substrate, and comprises a semiconductor layer. The semiconductor layer is arranged on a side of the buffer layer away from the substrate and covers at least the first sub-portion.
2. The array substrate according to claim 1, characterized in that: The buffer layer further includes a second buffer portion and a third buffer portion; the second buffer portion is disposed on a side of the light shielding layer away from the substrate and connected to the first buffer portion; the third buffer portion is disposed on one side of the substrate and connected to the first buffer portion; The semiconductor layer includes a channel portion and a conductor portion; the channel portion is arranged on a side of the second buffer portion away from the substrate; the conductor portion is connected to the channel portion, and at least a portion of the conductor portion covers the first sub-portion.
3. The array substrate according to claim 2, characterized in that: The conductive auxiliary layer further includes a second sub-portion, the second sub-portion is arranged on a side of the third buffer portion away from the substrate, and the second sub-portion is connected to the first sub-portion; Wherein, at least a portion of the conductor portion covers the first sub-portion and the second sub-portion.
4. The array substrate according to claim 3, characterized in that: The conductor portion comprises: a first sub-segment, disposed on a side of the first sub-portion away from the first buffer portion, the first sub-segment being connected to the channel portion; and The second sub-segment is arranged at a side of the second sub-portion away from the third buffer portion, and the second sub-segment is connected to the first sub-segment.
5. The array substrate according to claim 3, characterized in that: The conductive auxiliary layer further includes a third sub-portion, the third sub-portion is arranged on a side of the second buffer portion away from the light shielding layer, and the third sub-portion is connected to the first sub-portion; Wherein, at least a portion of the conductor portion covers the first sub-portion, the second sub-portion, and the third sub-portion.
6. The array substrate according to claim 5, characterized in that: The conductor portion comprises: A first subsection, disposed on a side of the first subsection away from the first buffer section; A second sub-section is provided at a side of the second sub-portion away from the third buffer portion; and a third subsection, arranged at a side of the third subsection away from the second buffer section; The first sub-segment connects the second sub-segment and the third sub-segment, and the third sub-segment is connected to the channel portion.
7. The array substrate according to claim 1, wherein: The angle formed by the extension direction of the first sub-portion and the plane where the substrate is located is in the range of 20 degrees to 70 degrees; and / or, The thickness of the conductive auxiliary layer is in the range of 100 angstroms to 1000 angstroms.
8. The array substrate according to any one of claims 1 to 7, characterized in that: The conductive auxiliary layer includes a metal layer; or, The conductive auxiliary layer includes a metal oxide layer.
9. The array substrate according to any one of claims 1 to 7, characterized in that: The thin film transistor further comprises: A gate insulating layer, disposed on a side of the semiconductor layer away from the substrate; A gate, disposed on a side of the gate insulating layer away from the substrate; an interlayer dielectric layer, disposed on a side of the buffer layer away from the substrate and covering the gate, the gate insulating layer and the semiconductor layer; a source electrode, a portion of which is disposed on a side of the interlayer dielectric layer away from the substrate, and another portion of which passes through the interlayer dielectric layer and is connected to the semiconductor layer; and A drain electrode, a portion of which is disposed on a side of the interlayer dielectric layer away from the substrate, and another portion of which passes through the interlayer dielectric layer and is connected to the semiconductor layer.
10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.