Transient current suppression module
By integrating multiple diodes in the transient voltage suppression module and forming a series structure, the problem of insufficient current resistance of existing TVS diodes is solved, and better high-current transient suppression and clamp voltage control are achieved.
Patent Information
- Application Number
- CN202421700559.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-18
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-07-18
AI Technical Summary
The existing transient voltage suppression (TVS) diodes have weak current resistance during reverse breakdown, which is prone to damage due to current exceeding the load range, which leads to circuit failure.
A transient current suppression module is designed to form a series structure by integrating multiple diodes on a P++ semiconductor substrate, including first, second, third and diode modules, and connecting wires to form a series structure to improve the conduction ability and current resistance after reverse breakdown.
It realizes better control of clamp voltage, enhances the ability to suppress high current transients, improves the module's current resistance, and reduces the risk of diode damage.
Smart Images
Figure CN222827583U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a transient current suppression module. Background Art
[0002] The ESD phenomenon is caused by the electrostatic field between objects. When the charge moves under the action of Coulomb force in the electric field, the charge transfer occurs. This electrostatic discharge can be caused by the electrostatic field generated between two objects, or by the resistance between the conductor and the grounding system. When enough static charge accumulates on the surface of an object, when it touches or approaches an object with a different electric potential, the charge will flow rapidly, generating transient current, thus causing the ESD phenomenon. Especially in integrated circuits, the ESD phenomenon can cause damage to the circuit, so it is necessary to protect the circuit from ESD.
[0003] In the prior art, a commonly used ESD protection measure is to use a transient voltage suppressor (TVS) diode. When an ESD phenomenon occurs, the TVS diode undergoes reverse breakdown, and its working impedance can be reduced to an extremely low conduction value, thereby allowing a large current to pass through while clamping the voltage to a predetermined level. However, when reverse breakdown occurs, the diode's current resistance is relatively weak. If the current passing through the diode at this time exceeds its carrying range, it is easy to cause damage to the diode, thereby causing circuit failure. Utility Model Content
[0004] In view of the above-mentioned deficiencies of the related prior art, the present application provides a transient current suppression module, which is easier to control the clamping voltage, has better large current transient suppression capability, and has strong practicality.
[0005] In order to achieve the above purpose, the utility model adopts the following technologies:
[0006] A transient current suppression module comprises: a P++ semiconductor substrate, a first diode, a second diode and a third diode module.
[0007] An N-epitaxial layer is provided on the top surface of the P++ semiconductor substrate, and a plurality of first P++ isolation wells are provided in the N-epitaxial layer along its length direction, and one end of the N-epitaxial layer is located in the P++ semiconductor substrate; the first diode includes a first N+ region provided in the N-epitaxial layer and located between two first P++ isolation wells; there are a plurality of second diodes, which are connected in series with each other, including a first P+ region provided in the N-epitaxial layer and located between two first P++ isolation wells, and second N+ regions are provided on both sides of the first P+ region, and the two second N+ regions of the first second diode and the first P+ region of the second diode are connected through conductive wires. The second N+ regions of the last second diode are connected to a first P++ isolation well through a wire; the third diode module is arranged between the first diode and the second diode, including an N++ buried layer located in the N-epitaxial layer and at least a part of which is located in the P++ semiconductor substrate, the N++ buried layer is located between the two first P++ isolation wells, and a plurality of N++ wells are arranged on the top surface, and a second P+ region is also arranged between two adjacent N++ wells; the first N+ region is connected to the second P+ region through a wire, and the first P+ region is simultaneously connected to a plurality of N++ wells through a wire, and one of the N++ wells is provided with a VDD port.
[0008] Furthermore, it also includes a fourth diode located between the first diode and the second diode, the fourth diode includes a second P++ isolation well arranged between the two first P++ isolation wells, a third P+ region with one end located in the P++ semiconductor substrate is provided in the second P++ isolation well, a third N+ region is provided at the other end of the third P+ region, and the first P+ region closest to the third diode module is also connected to the third N+ region through a wire.
[0009] Furthermore, a GND terminal is provided at the bottom of the P++ semiconductor substrate.
[0010] Furthermore, the number of the second diodes is 8 to 9.
[0011] Furthermore, the first N+ region is provided with an IO port.
[0012] Furthermore, a dielectric layer is disposed on the top surface of the N-epitaxial layer.
[0013] The beneficial effects of the utility model are:
[0014] By adding multiple diodes in series and combining them with the TVS diode and integrating them into a module, the superposition of their forward conduction turn-on voltage is achieved, making it easier to control the clamping voltage. The diode has a greater current resistance than reverse breakdown and has better large current transient suppression capability. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present invention.
[0016] Figure 1 This is a cross-sectional view of the overall structure of an embodiment of the present application.
[0017] Figure 2 Schematic diagram of the circuit structure of an embodiment of the present application.
[0018] Figure 3 An overall structural cross-sectional view of an additional fourth diode is provided for the embodiment of the present application.
[0019] Figure 4 This is a schematic diagram of the circuit structure after adding a fourth diode in the embodiment of the present application. DETAILED DESCRIPTION
[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the utility model clearer, the implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings, but the embodiments described in the utility model are only part of the embodiments of the utility model, rather than all the embodiments.
[0021] like Figure 1~Figure 4 As shown, this example provides a transient current suppression module, including: a P++ semiconductor substrate 1, a first diode 2, a second diode 3, and a third diode module 4.
[0022] An N-epitaxial layer 11 is provided on the top surface of the P++ semiconductor substrate 1, and a plurality of first P++ isolation wells 12 are provided in the N-epitaxial layer 11 along its length direction, and one end of the N-epitaxial layer 11 is located in the P++ semiconductor substrate 1; the first diode 2 includes a first N+ region 21 provided in the N-epitaxial layer 11 and located between two first P++ isolation wells 12; there are a plurality of second diodes 3, which are connected in series with each other, including a first P+ region 31 provided in the N-epitaxial layer 11 and located between two first P++ isolation wells 12, and second N+ regions 32 are provided on both sides of the first P+ region 31, and the two second N+ regions 32 of the first second diode 3 and the first P+ region 31 of the second diode 3 are connected by wires The two second N+ regions 32 of the last second diode 3 are connected to a first P++ isolation well 12 through a wire; the third diode module 4 is arranged between the first diode 2 and the second diode 3, and includes an N++ buried layer 41 located in the N-epitaxial layer 11 and at least a part of which is located in the P++ semiconductor substrate 1, the N++ buried layer 41 is located between the two first P++ isolation wells 12, and a plurality of N++ wells 42 are arranged on the top surface, and a second P+ region 43 is also arranged between two adjacent N++ wells 42; the first N+ region 21 is connected to the second P+ region 43 through a wire, and the first P+ region 31 is simultaneously connected to a plurality of N++ wells 42 through a wire, wherein one of the N++ wells 42 is provided with a VDD port,
[0023] Specifically, the N++ buried layer 41 and the P++ semiconductor substrate 1 constitute the fifth diode 44, and the second P+ region 43, the N-epitaxial layer 11 and the N++ well 42 constitute the sixth diode 45, then the third diode module 4 consists of one fifth diode 44 and two sixth diodes 45. In fact, when the number of N++ wells 42 exceeds 3, the number of sixth diodes 45 can be multiple, then the third diode module 4 consists of one fifth diode 44 and more than two sixth diodes 45, and if the number of N++ wells 42 is only 1, the number of sixth diodes 45 is 1, then the third diode module 4 consists of one fifth diode 44 and one sixth diode 45, thereby realizing the superposition of multiple diodes and occupying less circuit area.
[0024] Specifically, it also includes a fourth diode 5 located between the first diode 2 and the second diode 3. The fourth diode 5 includes a second P++ isolation well 51 arranged between the two first P++ isolation wells 12. The second P++ isolation well 51 is provided with a third P+ region 52 with one end located in the P++ semiconductor substrate 1, and the other end of the third P+ region 52 is provided with a third N+ region 53. The first P+ region 31 closest to the third diode module 4 is also connected to the third N+ region 53 through a wire. The structure of the fourth diode is a TVS diode. By reintroducing the TVS diode, the protection effect of the entire module against static electricity can be further improved, and the range of allowing large current to pass is also increased, thereby improving the current resistance of the module.
[0025] Specifically, the number of the second diodes 3 is 8 to 9, which is sufficient to provide electrostatic protection for the circuit and ensure a relatively large range for large current to pass through.
[0026] Specifically, a GND terminal is provided at the bottom of the P++ semiconductor substrate 1 to achieve grounding.
[0027] Specifically, the first N+ region 21 is provided with an IO port, the reverse breakdown voltage of the third diode module 4 is relatively high, and the voltage at which the plurality of second diodes 3 connected in series are turned on is relatively low. At this time, the diodes connected in series are turned on, allowing a large current to pass through and maintaining a relatively low clamping voltage;
[0028] When ESD occurs at the VDD interface input port, the reverse breakdown voltage of the first diode 2 and the third diode module 4 is high, and the voltage of the multiple second diodes 3 connected in series is low. At this time, the diodes in series are turned on, allowing large current to pass through and maintaining a relatively low clamping voltage.
[0029] Specifically, a dielectric layer 13 is further disposed on the top surface of the N-epitaxial layer 11. The material of the dielectric layer may be silicon dioxide, doped or undoped silicon glass, etc., to achieve electrical isolation and avoid short circuit.
[0030] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A transient current suppression module, characterized in that: include: A P++ semiconductor substrate (1), a top surface of which is provided with an N-epitaxial layer (11), a plurality of first P++ isolation wells (12) are provided in the N-epitaxial layer (11) along its length direction, and one end of the N-epitaxial layer (11) is located in the P++ semiconductor substrate (1); A first diode (2) comprising a first N+ region (21) provided in an N-epitaxial layer (11) and located between two first P++ isolation wells (12); There are a plurality of second diodes (3) which are connected in series, and include a first P+ region (31) disposed in the N-epitaxial layer (11) and located between two first P++ isolation wells (12), second N+ regions (32) are respectively disposed on both sides of the first P+ region (31), the two second N+ regions (32) of the first second diode (3) are connected to the first P+ region (31) of the next second diode (3) via a wire, and the two second N+ regions (32) of the last second diode (3) are connected to a first P++ isolation well (12) via a wire; A third diode module (4) is arranged between the first diode (2) and the second diode (3), comprising an N++ buried layer (41) located in the N-epitaxial layer (11) and at least a portion of which is located in the P++ semiconductor substrate (1), the N++ buried layer (41) being located between two first P++ isolation wells (12), and a plurality of N++ wells (42) being arranged on the top surface, and a second P+ region (43) being arranged between two adjacent N++ wells (42); The first N+ region (21) is connected to the second P+ region (43) through a wire, and the first P+ region (31) is simultaneously connected to a plurality of N++ wells (42) through a wire, wherein one of the N++ wells (62) is provided with a VDD port.
2. The transient current suppression module according to claim 1, characterized in that: The invention also comprises a fourth diode (5) located between the first diode (2) and the second diode (3); the fourth diode (5) comprises a second P++ isolation well (51) located between the two first P++ isolation wells (12); a third P+ region (52) having one end located in the P++ semiconductor substrate (1) is provided in the second P++ isolation well (51); a third N+ region (53) is provided at the other end of the third P+ region (52); and the first P+ region (31) closest to the third diode module (4) is also connected to the third N+ region (53) via a wire.
3. The transient current suppression module according to claim 1, characterized in that: A GND terminal is provided at the bottom of the P++ semiconductor substrate (1).
4. The transient current suppression module according to claim 1, characterized in that: The number of the second diodes (3) is 8 to 9.
5. The transient current suppression module according to claim 1, characterized in that: The first N+ region (21) is provided with an IO port.
6. The transient current suppression module according to claim 1, characterized in that: A dielectric layer (13) is also provided on the top surface of the N-epitaxial layer (11).