Safety AND gate circuit
By designing a simplified safety and gate circuit, using the first control module, the second control module, the buffer, the inverter, the isolation circuit and the differential amplifier, the problem of increasing fault points caused by circuit complexity in the prior art is solved, and higher signal safety and reliability are achieved.
Patent Information
- Application Number
- CN202421506181.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-06-27
AI Technical Summary
The existing safety and gate circuit structure is too complex, which can easily lead to an increase in fault points, affecting the safety and reliability of the signal.
A simplified safety and gate circuit is designed, including a first control module, a second control module, a buffer, an inverter, a first isolation circuit, a second isolation circuit and a differential amplifier, through which the same pulse control signals are outputted to reduce circuit complexity and fault points.
By simplifying the circuit structure, the number of fault points is reduced, the signal safety and reliability are improved, and the circuit complexity and power consumption are reduced.
Smart Images
Figure CN222868911U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power electronics, in particular to a safety AND gate circuit. Background Art
[0002] The signal system is the eyes and ears of the rail transit transportation system and a powerful tool to ensure operational safety and improve transportation efficiency. Therefore, the rail transit signal system has relatively high safety requirements. At present, safety AND gate circuits are widely used in signal systems to ensure the safety of output signals.
[0003] An existing safety AND gate circuit includes two isolated boost converter circuits, an oscillator, an isolated boost transducer circuit, and an isolated feedback circuit. The oscillator is used to perform a logical "AND" on the outputs of the two CPUs, and the safety AND gate circuit is used to control the relay to improve safety. However, the circuit structure is too complicated, which easily leads to an increase in fault points. Utility Model Content
[0004] The utility model provides a safety AND gate circuit with a simple circuit structure and can reduce fault points.
[0005] In a first aspect, the utility model provides a safety AND gate circuit, comprising a first control module, a second control module, a buffer, an inverter, a first isolation circuit, a second isolation circuit and a differential amplifier;
[0006] The first control module and the second control module are connected to the input end of the buffer and the input end of the inverter respectively, the output end of the buffer is connected to the first input end of the differential amplifier through the first isolation circuit, the output end of the inverter is connected to the second input end of the differential amplifier through the second isolation circuit, and the output end of the differential amplifier is used to connect to the safety relay;
[0007] The first control module and the second control module are used to output the same pulse control signal.
[0008] Through the above method, the circuit structure is simple and the number of failure points can be reduced.
[0009] In a feasible design, the safety AND gate circuit also includes a first sampling feedback module and a second sampling feedback module, the input ends of the first sampling feedback module and the second sampling feedback module are both connected to the output end of the differential amplifier, the output end of the first sampling feedback module is connected to the first control module through the first isolation circuit, and the output end of the second sampling feedback module is connected to the second control module through the second isolation circuit.
[0010] In a feasible design, the differential amplifier includes an input stage circuit, a bias circuit and an output stage circuit;
[0011] The input stage circuit includes a common collector composite differential amplifier circuit and an active load circuit. The common collector composite differential amplifier circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The active load circuit includes a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor and a third resistor. The first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are connected together and connected to the bias circuit. The control ends of the first transistor and the third transistor are respectively connected to the first input end and the second input end of the differential amplifier. The second ends of the first transistor and the third transistor are respectively connected to the control ends of the second transistor and the fourth transistor. The second ends of the second transistor and the fourth transistor are respectively connected to the first ends of the fifth transistor and the sixth transistor. The control ends of the fifth transistor and the sixth transistor are both connected to a negative power supply through the third resistor. The second ends of the fifth transistor and the sixth transistor are respectively connected to the negative power supply through the first resistor and the second resistor. The first end of the sixth transistor is connected to the output stage circuit. The control end of the sixth transistor is connected to the second end of the seventh transistor. The first end and the control end of the seventh transistor are both connected to a positive power supply.
[0012] In a feasible design, the bias circuit includes two mirror constant current sources, and the two mirror constant current sources include an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; the second ends of the eighth transistor, the ninth transistor, the twelfth transistor, and the thirteenth transistor and the first ends of the tenth transistor and the eleventh transistor are all connected to the positive power supply; the first end of the eighth transistor is connected to the first end of the first transistor, the control end of the eighth transistor and the control end of the ninth transistor are both connected to the first end of the ninth transistor, and the first end of the ninth transistor is connected to the control end of the tenth transistor through the fourth resistor; the first end of the thirteenth transistor is connected to the output stage circuit, the control end of the thirteenth transistor and the control end of the twelfth transistor are both connected to the first end of the twelfth transistor, and the first end of the twelfth transistor is connected to the control end of the eleventh transistor through the seventh resistor; the second ends of the tenth transistor and the eleventh transistor are connected to the negative power supply through the fifth resistor and the sixth resistor respectively.
[0013] In a feasible design, the output stage circuit includes a complementary push-pull amplifier circuit and an overload protection circuit, the complementary push-pull amplifier circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, and the overload protection circuit includes a first diode, a tenth resistor and an eleventh resistor;
[0014] The control end of the fifteenth transistor and the control end of the seventeenth transistor are both connected to the control end of the sixth transistor, the control end of the fifteenth transistor is connected to the first end of the thirteenth transistor, the first end of the fifteenth transistor and the first end of the sixteenth transistor are both connected to the positive power supply, the second end of the fifteenth transistor is connected to the control end of the sixteenth transistor, and the second end of the sixteenth transistor is connected to the output end of the differential amplifier through the tenth resistor; the second end of the eighteenth transistor is connected to the negative power supply, the control end of the eighteenth transistor is connected to the first end of the seventeenth transistor, the first end of the eighteenth transistor and the second end of the seventeenth transistor are both connected to the output end of the differential amplifier through the eleventh resistor, the first end of the first diode is connected to the connection point of the tenth resistor and the eleventh resistor, and the second end of the first diode is connected to the control end of the seventeenth transistor.
[0015] In a feasible design, the output stage circuit further includes a multiplication circuit, and the multiplication circuit includes a fourteenth transistor, an eighth resistor and a ninth resistor; the control end of the fifteenth transistor is connected to the control end of the sixth transistor through the fourteenth transistor;
[0016] The control end of the fourteenth transistor is connected to the second end of the first diode, the second end of the fourteenth transistor is connected to the control end of the sixth transistor, the first end of the fourteenth transistor is connected to the control end of the fifteenth transistor, the eighth resistor and the ninth resistor are connected in series between the first end and the second end of the fourteenth transistor, and the series connection point is connected to the control end of the fourteenth transistor.
[0017] In a feasible design, the first diode is a bidirectional diode;
[0018] Alternatively, the first diode includes a first unidirectional diode and a second unidirectional diode, and the first unidirectional diode and the second unidirectional diode are connected in reverse parallel.
[0019] In a feasible design, the eighth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, and the seventeenth transistor are PNP transistors, and the other transistors are NPN transistors.
[0020] In a feasible design, the first sampling feedback module includes two voltage-dividing resistors connected in series, the two voltage-dividing resistors are connected in series between the input end of the first sampling feedback module and a reference ground, and the series connection point of the two voltage-dividing resistors is connected to the output end of the first sampling feedback module;
[0021] The second sampling feedback module includes two voltage-dividing resistors connected in series between the input terminal of the second sampling feedback module and a reference ground, and a series connection point of the two voltage-dividing resistors is connected to the output terminal of the second sampling feedback module.
[0022] In a feasible design, the buffer includes a nineteenth transistor, a twelfth resistor, a thirteenth resistor and a first capacitor; the control end of the nineteenth transistor is connected to the input end of the buffer, the first end of the nineteenth transistor is connected to the positive power supply through the twelfth resistor, the second end of the nineteenth transistor is connected to the output end of the buffer, the thirteenth resistor and the first capacitor are connected in parallel between the second end of the nineteenth transistor and the reference ground; the nineteenth transistor is an NPN transistor.
[0023] In a feasible design, the inverter includes a twentieth transistor, a fourteenth resistor, a fifteenth resistor and a second capacitor; the control end of the twentieth transistor is connected to the input end of the inverter, the first end of the twentieth transistor is connected to the positive power supply through the fourteenth resistor, the first end of the twentieth transistor is connected to the output end of the inverter, the fifteenth resistor and the second capacitor are connected in parallel between the second end of the twentieth transistor and the reference ground; the twentieth transistor is an NPN transistor.
[0024] In a feasible design, the safety AND gate circuit also includes the safety relay. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of a safety AND gate circuit provided by an embodiment of the utility model;
[0026] Figure 2 A schematic diagram of the structure of a buffer provided by an embodiment of the utility model;
[0027] Figure 3 A schematic diagram of the structure of an inverter provided by an embodiment of the utility model;
[0028] Figure 4 Another schematic diagram of the structure of the safety AND gate circuit provided by the embodiment of the utility model;
[0029] Figure 5A schematic diagram of the structure of a first sampling feedback module and a second sampling feedback module provided in an embodiment of the utility model;
[0030] Figure 6 A schematic diagram of the structure of a first isolation circuit and a second isolation circuit provided in an embodiment of the utility model;
[0031] Figure 7 A schematic diagram of the structure of a differential amplifier provided in an embodiment of the utility model;
[0032] Figure 8 A schematic diagram of the structure of a mirror image constant current source provided by an embodiment of the utility model;
[0033] Fig. 9 Another structural schematic diagram of the differential amplifier provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0034] The safety AND gate circuit provided by the utility model is specifically introduced below in conjunction with the accompanying drawings.
[0035] See also Figure 1 , Figure 1 A schematic diagram of a safety AND gate circuit provided by an embodiment of the utility model is shown in FIG. Figure 1 As shown, the safety and gate circuit may include a first control module (in Figure 1 Indicated as CPU1), the second control module (in Figure 1 denoted as CPU2), a buffer, an inverter, a first isolation circuit, a second isolation circuit and a differential amplifier.
[0036] In the safety AND gate circuit, the first control module and the second control module can be connected to the input end of the buffer and the input end of the inverter respectively, the output end of the buffer is connected to the first input end of the differential amplifier through the first isolation circuit, the output end of the inverter is connected to the second input end of the differential amplifier through the second isolation circuit, and the output end of the differential amplifier is used to connect to the safety relay.
[0037] The first control module and the second control module are used to output the same pulse control signal. Here, the same pulse control signal means that their waveform, amplitude, phase and frequency are the same. The two pulse control signals are synchronized. The pulse control signal can be a pulse width modulation (PWM) signal.
[0038] A safety relay (also called a safety relay) may include a normally open contact and a normally closed contact, and the normally open contact and the normally closed contact will not be closed at the same time. The normally open contact of the safety relay provides a dry contact output (such as Figure 1The dry contact output 1 and dry contact output 2 in the safety relay are connected to the safety relay, and the normally closed contact can be detected by the CPU. When the signal received by the safety relay meets its driving requirements, the safety relay can be driven, its normally open contact is closed, and the normally closed contact is disconnected. Correspondingly, when the signal received by the safety relay does not meet its driving requirements, the safety relay cannot be driven, its normally open contact is disconnected, and the normally closed contact is closed. The state of this relay is the corresponding safety side.
[0039] See also Figure 2 , Figure 2 A schematic diagram of a structure of a buffer provided by an embodiment of the utility model, as shown in Figure 2 As shown, the buffer may include a nineteenth transistor (such as Figure 2 Q19 in), the twelfth resistor (such as Figure 2 R12 in), the thirteenth resistor (such as Figure 2 R13 in) and the first capacitor (such as Figure 2 The control terminal of the nineteenth transistor can be connected to the input terminal of the buffer (in Figure 2 The first end of the nineteenth transistor is connected to the positive power supply (such as Figure 2 The second end of the nineteenth transistor is connected to the output end of the buffer (in Figure 2 The thirteenth resistor and the first capacitor are connected in parallel between the second end of the nineteenth transistor and the reference ground. Here, the nineteenth transistor can be an NPN-type triode. In the present utility model, when any transistor is a triode, the control end of the transistor is the base of the triode, the first end of the transistor is the collector of the triode, and the second end of the transistor is the emitter of the triode. Any transistor in the present utility model can also be other types of semiconductor devices, such as insulated gate bipolar transistors (IGBT), etc., which are not limited here. These transistors are exemplified as triodes in the present utility model.
[0040] like Figure 2 As shown, the buffer can be composed of transistor Q19, resistors R12, R13 and capacitor C1. The PWM signal output by CPU1 is input from the base of transistor Q19 and output from the emitter of Q19. Since the output signal of the buffer changes with the input signal, the amplitude and phase remain consistent. Therefore, after the PWM signal output by CPU1 passes through the buffer, the amplitude and phase remain unchanged.
[0041] See also Figure 3 , Figure 3 A schematic diagram of the structure of an inverter provided by an embodiment of the utility model is shown in FIG. Figure 3As shown, the inverter may include a twentieth transistor (such as Figure 3 Q20 in), the fourteenth resistor (such as Figure 3 R14 in), the fifteenth resistor (such as Figure 3 R15 in) and the second capacitor (such as Figure 3 The control terminal of the twentieth transistor is connected to the input terminal of the inverter (such as Figure 3 Ui in the figure), the first end of the twentieth transistor is connected to the positive power supply (such as Figure 3 The first end of the twentieth transistor is connected to the output end of the inverter (such as VCC in Figure 3 The fifteenth resistor and the second capacitor are connected in parallel between the second end of the twentieth transistor and the reference ground; the twentieth transistor can be an NPN transistor. Then the control end, the first end, and the second end of the twentieth transistor are the base, the collector, and the emitter of the transistor respectively.
[0042] like Figure 3 As shown in FIG. 1 , the inverter is composed of transistor Q20, resistors R14, R15 and capacitor C2. The PWM signal output by CPU2 is input from the base of transistor Q20 and output from the collector of Q20. Since the inverter can make the output signal 180° out of phase with the input signal, the PWM signal output by CPU2 remains unchanged in amplitude and changes in phase by 180° after passing through the inverter.
[0043] Then, CPU1 and CPU2 normally output the same PWM signal, which, after passing through the buffer and the inverter, forms a group of signals with equal amplitude and opposite phase, and then passes through the first isolation circuit and the second isolation circuit, and is sent to the two input ends of the differential amplifier. After being amplified by the differential amplifier, it can be sent to the input end of the safety relay. If the driving requirements of the safety relay can be met, the normally open contact of the safety relay can be driven to close. If at least one of CPU1 and CPU2 fails, the signal received by the input end of the safety relay cannot drive it, the normally open contact of the safety relay is disconnected, and the safety relay is directed to the safety side.
[0044] In the present invention, by providing a buffer and an inverter, the signals outputted by CPU1 and CPU2 can maintain the same delay during the transmission process, thus avoiding the occurrence of competition risk.
[0045] In a possible implementation manner, the safety AND gate circuit may further include the safety relay.
[0046] See also Figure 4 , Figure 4 Another schematic diagram of the structure of the safety AND gate circuit provided by the embodiment of the utility model is shown. Figure 4As shown, the above-mentioned safety and gate circuit can also include a first sampling feedback module and a second sampling feedback module, the input ends of the first sampling feedback module and the second sampling feedback module are both connected to the output end of the differential amplifier, the output end of the first sampling feedback module is connected to the first control module through the first isolation circuit, and the output end of the second sampling feedback module is connected to the second control module through the second isolation circuit. In this way, the first sampling feedback module and the second sampling module can sample and obtain the output of the differential amplifier, and feed back the sampling results to the first control module and the second control module respectively. When the feedback result indicates that the output result of the differential amplifier is abnormal, the first control module and the second control module can stop outputting the pulse control signal to further improve safety.
[0047] In a possible implementation, the first sampling feedback module may include two voltage-dividing resistors connected in series between an input terminal of the first sampling feedback module and a reference ground, and a series connection point of the two voltage-dividing resistors is connected to an output terminal of the first sampling feedback module.
[0048] The second sampling feedback module may include two voltage-dividing resistors connected in series between the input terminal of the second sampling feedback module and a reference ground, and a series connection point of the two voltage-dividing resistors is connected to the output terminal of the second sampling feedback module.
[0049] That is to say, the above two sampling feedback modules can use two series-connected voltage-dividing resistors, connect the two series-connected voltage-dividing resistors to the output end of the differential amplifier, and use the form of resistor voltage division so that the feedback signal is sent back to CPU1 and CPU2 through the sampling of one of the voltage-dividing resistors. Figure 5 As shown, Figure 5 The structure of any sampling feedback module is shown, Uo represents the output end of the differential amplifier, two voltage-dividing resistors Ra and Rb are connected in series between the output end of the differential amplifier and the reference ground, and the sampling feedback module obtains the voltage of the voltage-dividing resistor Ra by sampling, and can correspondingly obtain the output of the differential amplifier, obtain the feedback signal, and output the feedback signal to CPU1 and CPU2 through the isolation circuit.
[0050] The first isolation circuit and the second isolation circuit may be isolation circuits with the same structure. Figure 6 The structure of any isolation circuit in the utility model is shown, such as Figure 6 As shown, the isolation circuit may be composed of an optocoupler isolator U1, resistors Rc, Rd, Re and capacitor C3. The optocoupler isolator U1 may include eight pins 1 to 8. The connection relationship of each component is as shown in FIG. Figure 6As shown, VCC represents the power supply voltage of the optocoupler isolator. After photoelectric conversion, the optocoupler isolator can isolate the PWM signal output by the inverter and buffer from the differential amplifier, and can also isolate the feedback signal output by each sampling feedback module from each control module (referring to CPU1 and CPU2), thereby reducing interference.
[0051] In the utility model, the function of the safety AND gate is realized by a buffer, an inverter, a first isolation circuit, a second isolation circuit, a differential amplifier, a first sampling feedback module, a second sampling feedback module and a safety relay. By setting a differential amplifier in the circuit, the circuit input impedance can be increased and the signal anti-interference ability can be improved. There is no need to set up many modules, the overall circuit structure is simple, the power consumption is low, the reliability is high, and the number of fault points can be reduced.
[0052] The structure of the differential amplifier in the safety AND gate circuit is introduced in detail below.
[0053] See also Figure 7 , Figure 7 A schematic diagram of a differential amplifier provided in an embodiment of the utility model is shown in FIG. Figure 7 As shown, the differential amplifier may include an input stage circuit, a bias circuit and an output stage circuit.
[0054] The input stage circuit may include a common collector composite differential amplifier circuit and an active load circuit, wherein the common collector composite differential amplifier circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor (such as Figure 7 Q1, Q2, Q3 and Q4 in the figure), the active load circuit includes a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor and a third resistor (such as Figure 7 Q5, Q6, Q7, R1, R2 and R3 in FIG. 1 ). In which, taking these transistors as triodes as an example, the control end, the first end and the second end of these transistors may refer to the base, the collector and the emitter of the triode respectively. Q1 to Q7 may be NPN type triodes.
[0055] In the input stage circuit, the first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are connected together and connected to the bias circuit, the control ends of the first transistor and the third transistor are respectively connected to the first input end and the second input end of the differential amplifier, the second ends of the first transistor and the third transistor are respectively connected to the control ends of the second transistor and the fourth transistor, the second ends of the second transistor and the fourth transistor are respectively connected to the first ends of the fifth transistor and the sixth transistor, and the control ends of the fifth transistor and the sixth transistor are both connected to the negative power supply (referring to Figure 7The second ends of the fifth transistor and the sixth transistor are connected to the negative power supply through the first resistor and the second resistor respectively, and the first end of the sixth transistor is connected to the output stage circuit; the control end of the sixth transistor is connected to the second end of the seventh transistor, and the first end and the control end of the seventh transistor are both connected to the positive power supply (referring to Figure 7 VCC+ in the power supply.
[0056] like Figure 7 As shown, in the input stage circuit of the differential amplifier, Q1, Q2, Q3, and Q4 form a common collector composite differential amplifier circuit. The differential mode signals Ui1 and Ui2 generated by CPU1 and CPU2 are respectively input by the base of Q1 and Q3 through the buffer and the inverter. After amplification, they are output by the collector of Q6 in a single-ended form to the base of Q17 in the output stage circuit; Q5, Q6, and Q7 in the active load circuit constitute the active load of Q2 and Q4. In order to ensure that the active load is completely symmetrical, R1 and R2 are both 1KΩ, and in order to reduce the static current, R3 is 50KΩ. Since the active load is completely symmetrical, the common mode rejection ratio is greatly improved. The role of Q7 is only to provide a stable bias current to Q5 and Q6 to ensure that Q5 and Q6 work in a balanced manner.
[0057] like Figure 7 As shown, the bias circuit of the differential amplifier may include two mirror constant current sources, and the two mirror constant current sources include an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor (such as Figure 7 , Q8, Q9, Q10, Q11, Q12, Q13, R4, R5, R6 and R7 in FIG. 1 ). Taking these transistors as triodes as an example, Q10 and Q11 may be NPN triodes, and Q8, Q9, Q12 and Q13 may be PNP triodes.
[0058] In the bias circuit, the second ends of the eighth transistor, the ninth transistor, the twelfth transistor, and the thirteenth transistor and the first ends of the tenth transistor and the eleventh transistor are all connected to a positive power supply; the first end of the eighth transistor is connected to the first end of the first transistor, the control end of the eighth transistor and the control end of the ninth transistor are both connected to the first end of the ninth transistor, and the first end of the ninth transistor is connected to the control end of the tenth transistor through a fourth resistor; the first end of the thirteenth transistor is connected to the output stage circuit, the control end of the thirteenth transistor and the control end of the twelfth transistor are both connected to the first end of the twelfth transistor, and the first end of the twelfth transistor is connected to the control end of the eleventh transistor through a seventh resistor; the second ends of the tenth transistor and the eleventh transistor are connected to a negative power supply through a fifth resistor and a sixth resistor, respectively.
[0059] In this bias circuit, transistors Q8, Q9, Q10, Q11, Q12, Q13 and resistors R4, R5, R6, R7 constitute the bias circuit of the input stage circuit and the output stage circuit, which mainly consists of two sets of mirror constant current sources composed of Q8, Q9, Q10 and Q11, Q12, Q13 to provide a stable static operating point for the transistor.
[0060] The following takes a set of mirror image constant current sources composed of Q8, Q9, Q10, R4, and R5 as an example to explain the working principle of the bias circuit. The structure of the mirror image constant current source composed of these devices can be simplified as follows: Figure 8 shown.
[0061] In this mirror image constant current source, Q8 and Q9 are transistors with the same process, structure and material, and their currents are symmetrical and equal. Figure 8 As shown, I B8 =I B9 =I B , I C8 =I C9 =I C , ignoring Q10 and R5, we can calculate I R4 =(VCC-U BE ) / R4, according to the shunt relationship:
[0062] I R4 =I C9 +2I B =I C9 +(2I C / β)=I C9 (1+2 / β),
[0063] When β>>2,
[0064] I R4 =I C9 =(VCC-U BE ) / R4,
[0065] And I C8 =I C9 =I C , so I R4 =I C8 =(VCC-U BE ) / R4,
[0066] I R4 As the reference current, I C8 As output current, it supplies other amplifier stages. R4 OK, I C8 Then it was determined that I R4 Stable, I C8 It also stabilizes, I C8 with IR4 Become a mirror relationship, the output current I C8 Only determined by the reference current I R4 .
[0067] like Figure 8 As shown, Q10 and R5 act as a micro-current source. R4 =I C8 =(VCC-U BE ) / R4, if bias current I is required C8 When the voltage is as small as uA level, the resistance of R4 must be increased, which inevitably increases the static power consumption; when Q10 and R5 are added, the resistance of R5 only needs to be controlled at KΩ to meet the requirement. In this way, the static power consumption can be reduced.
[0068] like Figure 7 As shown, the output stage circuit in the differential amplifier may include a complementary push-pull amplifier circuit and an overload protection circuit, and the complementary push-pull amplifier circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor (as shown in FIG. Figure 7 Q15, Q16, Q17 and Q18 in the overload protection circuit, the overload protection circuit includes a first diode, a tenth resistor and an eleventh resistor (such as Figure 7 D1, R10 and R11 in FIG. 1 ). Taking these transistors as triodes for example, Q15, Q16 and Q18 can be NPN triodes, and Q17 can be PNP triode. The output of the differential amplifier is Figure 7 Uo in represents VCC+ and VCC- respectively represent the positive power supply and negative power supply of the differential amplifier.
[0069] The first diode D1 may be a bidirectional diode. Alternatively, the first diode D1 may include a first unidirectional diode and a second unidirectional diode, and the first unidirectional diode and the second unidirectional diode are connected in reverse parallel. The utility model takes the first diode D1 as a bidirectional diode as an example.
[0070] In the output stage circuit, the control end of the fifteenth transistor and the control end of the seventeenth transistor are both connected to the control end of the sixth transistor in the input stage circuit, the control end of the fifteenth transistor is connected to the first end of the thirteenth transistor in the bias circuit, the first end of the fifteenth transistor and the first end of the sixteenth transistor are both connected to the positive power supply, the second end of the fifteenth transistor is connected to the control end of the sixteenth transistor, and the second end of the sixteenth transistor is connected to the output end of the differential amplifier through the tenth resistor; the second end of the eighteenth transistor is connected to the negative power supply, the control end of the eighteenth transistor is connected to the first end of the seventeenth transistor, the first end of the eighteenth transistor and the second end of the seventeenth transistor are both connected to the output end of the differential amplifier through the eleventh resistor, the first end of the first diode is connected to the connection point of the tenth resistor and the eleventh resistor, and the second end of the first diode is connected to the control end of the seventeenth transistor.
[0071] like Figure 7 As shown in FIG. 1 , in the output stage circuit, transistors Q15, Q16, Q17, and Q18 form a complementary push-pull amplifier circuit. Complementary components such as R15 and R17 are turned on in turn to improve the circuit stability.
[0072] like Figure 7 As shown in the output stage circuit, resistors R10, R11 and diode D1 form an overload protection circuit. In normal operation, diode D1 is not conducting. When compound tubes Q15 and Q16 are conducting (Q17 and Q18 are off) and the conducting current is too large, it will cause U R10 increases, making diode D1 conductive, and a current I flows through diode D1. D1 This will affect the current I flowing into the composite tubes Q15 and Q16. B15 The output current of the composite tubes Q15 and Q16 can be limited by current shunting. Similarly, when Q17 and Q18 are turned on (Q15 and Q16 are turned off) and the on-current is too large, it will cause U R11 increases, making diode D1 conductive, and a current I flows through diode D1. D1 This will affect the current I flowing into the composite tubes Q17 and Q18. B17 The current is shunted, thereby limiting the output current of the compound tubes Q17 and Q18, achieving the overload protection function.
[0073] In a possible implementation, Fig. 9 As shown, the output stage circuit in the differential amplifier may further include a multiplication circuit, the multiplication circuit including a fourteenth transistor, an eighth resistor and a ninth resistor (such as Fig. 9 Q14, R8 and R9 in FIG. 1 ). Q14 can be an NPN transistor.
[0074] In the output stage circuit, the control end of the fifteenth transistor is connected to the control end of the sixth transistor in the input stage circuit through the fourteenth transistor; the control end of the fourteenth transistor is connected to the second end of the first diode, the second end of the fourteenth transistor is connected to the control end of the sixth transistor, the first end of the fourteenth transistor is connected to the control end of the fifteenth transistor, the eighth resistor and the ninth resistor are connected in series between the first end and the second end of the fourteenth transistor, and the series connection point is connected to the control end of the fourteenth transistor.
[0075] like Fig. 9 As shown, in the output stage circuit, transistor Q14 and resistors R8 and R9 constitute a Ube multiplier circuit.
[0076] By setting the resistance values of resistors R8 and R9 to suitable values, the voltage of Uce of Q14 can be just a multiple of Ube of Q15 (or Q17), that is, a multiple of 0.7. In static state, it is used to set a suitable operating point so that the composite tubes Q15, Q16, Q17, and Q18 are close to the on state, thereby eliminating crossover distortion.
[0077] In the utility model, by utilizing the characteristics of the differential amplifier to realize a two-out-of-two safety AND gate circuit, the common mode suppression capability is strong and common cause failure can be avoided. Compared with other types of safety AND gate circuits, the safety AND gate circuit has the characteristics of high safety, reliable performance, stable circuit, etc., and can greatly simplify the circuit structure and reduce the number of fault points.
[0078] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0079] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.
Claims
1. A safety AND gate circuit, characterized in that: It includes a first control module, a second control module, a buffer, an inverter, a first isolation circuit, a second isolation circuit and a differential amplifier; The first control module and the second control module are connected to the input end of the buffer and the input end of the inverter respectively, the output end of the buffer is connected to the first input end of the differential amplifier through the first isolation circuit, the output end of the inverter is connected to the second input end of the differential amplifier through the second isolation circuit, and the output end of the differential amplifier is used to connect to the safety relay; The first control module and the second control module are used to output the same pulse control signal.
2. The safety AND gate circuit according to claim 1, characterized in that: The safety AND gate circuit also includes a first sampling feedback module and a second sampling feedback module, wherein the input ends of the first sampling feedback module and the second sampling feedback module are both connected to the output end of the differential amplifier, the output end of the first sampling feedback module is connected to the first control module through the first isolation circuit, and the output end of the second sampling feedback module is connected to the second control module through the second isolation circuit.
3. The safety AND gate circuit as claimed in claim 2, characterized in that: The differential amplifier comprises an input stage circuit, a bias circuit and an output stage circuit; The input stage circuit includes a common collector composite differential amplifier circuit and an active load circuit. The common collector composite differential amplifier circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The active load circuit includes a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor and a third resistor. The first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are connected together and connected to the bias circuit. The control ends of the first transistor and the third transistor are respectively connected to the first input end and the second input end of the differential amplifier. The second ends of the first transistor and the third transistor are respectively connected to the control ends of the second transistor and the fourth transistor. The second ends of the second transistor and the fourth transistor are respectively connected to the first ends of the fifth transistor and the sixth transistor. The control ends of the fifth transistor and the sixth transistor are both connected to a negative power supply through the third resistor. The second ends of the fifth transistor and the sixth transistor are respectively connected to the negative power supply through the first resistor and the second resistor. The first end of the sixth transistor is connected to the output stage circuit. The control end of the sixth transistor is connected to the second end of the seventh transistor. The first end and the control end of the seventh transistor are both connected to a positive power supply.
4. The safety AND gate circuit as claimed in claim 3, characterized in that: The bias circuit includes two mirror constant current sources, which include an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; the second ends of the eighth transistor, the ninth transistor, the twelfth transistor and the thirteenth transistor and the first ends of the tenth transistor and the eleventh transistor are all connected to the positive power supply; the first end of the eighth transistor is connected to the first end of the first transistor, the control end of the eighth transistor and the control end of the ninth transistor are both connected to the first end of the ninth transistor, and the first end of the ninth transistor is connected to the control end of the tenth transistor through the fourth resistor; the first end of the thirteenth transistor is connected to the output stage circuit, the control end of the thirteenth transistor and the control end of the twelfth transistor are both connected to the first end of the twelfth transistor, and the first end of the twelfth transistor is connected to the control end of the eleventh transistor through the seventh resistor; the second ends of the tenth transistor and the eleventh transistor are connected to the negative power supply through the fifth resistor and the sixth resistor respectively.
5. The safety AND gate circuit as claimed in claim 4, characterized in that: The output stage circuit includes a complementary push-pull amplifier circuit and an overload protection circuit, the complementary push-pull amplifier circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, and the overload protection circuit includes a first diode, a tenth resistor and an eleventh resistor; The control end of the fifteenth transistor and the control end of the seventeenth transistor are both connected to the control end of the sixth transistor, the control end of the fifteenth transistor is connected to the first end of the thirteenth transistor, the first end of the fifteenth transistor and the first end of the sixteenth transistor are both connected to the positive power supply, the second end of the fifteenth transistor is connected to the control end of the sixteenth transistor, and the second end of the sixteenth transistor is connected to the output end of the differential amplifier through the tenth resistor; the second end of the eighteenth transistor is connected to the negative power supply, the control end of the eighteenth transistor is connected to the first end of the seventeenth transistor, the first end of the eighteenth transistor and the second end of the seventeenth transistor are both connected to the output end of the differential amplifier through the eleventh resistor, the first end of the first diode is connected to the connection point of the tenth resistor and the eleventh resistor, and the second end of the first diode is connected to the control end of the seventeenth transistor.
6. The safety AND gate circuit as claimed in claim 5, characterized in that: The output stage circuit further includes a multiplication circuit, which includes a fourteenth transistor, an eighth resistor and a ninth resistor; the control end of the fifteenth transistor is connected to the control end of the sixth transistor through the fourteenth transistor; The control end of the fourteenth transistor is connected to the second end of the first diode, the second end of the fourteenth transistor is connected to the control end of the sixth transistor, the first end of the fourteenth transistor is connected to the control end of the fifteenth transistor, the eighth resistor and the ninth resistor are connected in series between the first end and the second end of the fourteenth transistor, and the series connection point is connected to the control end of the fourteenth transistor.
7. The safety AND gate circuit as claimed in claim 5, characterized in that: The first diode is a bidirectional diode; Alternatively, the first diode includes a first unidirectional diode and a second unidirectional diode, and the first unidirectional diode and the second unidirectional diode are connected in reverse parallel.
8. The safety AND gate circuit as claimed in claim 7, characterized in that: The eighth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, and the seventeenth transistor are PNP transistors, and the other transistors are NPN transistors.
9. The safety AND gate circuit as claimed in claim 8, characterized in that: The first sampling feedback module includes two voltage-dividing resistors connected in series, the two voltage-dividing resistors are connected in series between an input terminal of the first sampling feedback module and a reference ground, and a series connection point of the two voltage-dividing resistors is connected to an output terminal of the first sampling feedback module; The second sampling feedback module includes two voltage-dividing resistors connected in series between the input terminal of the second sampling feedback module and a reference ground, and a series connection point of the two voltage-dividing resistors is connected to the output terminal of the second sampling feedback module.
10. The safety AND gate circuit according to any one of claims 3 to 9, characterized in that: The buffer includes a nineteenth transistor, a twelfth resistor, a thirteenth resistor and a first capacitor; the control end of the nineteenth transistor is connected to the input end of the buffer, the first end of the nineteenth transistor is connected to the positive power supply through the twelfth resistor, the second end of the nineteenth transistor is connected to the output end of the buffer, the thirteenth resistor and the first capacitor are connected in parallel between the second end of the nineteenth transistor and the reference ground; the nineteenth transistor is an NPN transistor.
11. The safety AND gate circuit according to claim 10, characterized in that: The inverter includes a twentieth transistor, a fourteenth resistor, a fifteenth resistor and a second capacitor; the control end of the twentieth transistor is connected to the input end of the inverter, the first end of the twentieth transistor is connected to the positive power supply through the fourteenth resistor, the first end of the twentieth transistor is connected to the output end of the inverter, the fifteenth resistor and the second capacitor are connected in parallel between the second end of the twentieth transistor and the reference ground; the twentieth transistor is an NPN transistor.
12. The safety AND gate circuit according to claim 11, characterized in that: The safety AND gate circuit also includes the safety relay.