Ferroelectric field effect transistor device and integrated chip

Abstract

The embodiment of the utility model relates to a ferroelectric field effect transistor (FeFET) device and an integrated chip, and the device comprises a ferroelectric structure which comprises a ferroelectric layer and an anti-ferroelectric layer; the gate structure is arranged along the first surface of the anti-ferroelectric layer, so that the gate structure is separated from the ferroelectric layer by the anti-ferroelectric layer; an oxide semiconductor disposed along a first surface of the ferroelectric layer such that the ferroelectric layer separates the oxide semiconductor from the anti-ferroelectric layer; the source electrode region and the drain electrode region are arranged on the oxide semiconductor, and the gate structure extends in the side direction on the anti-ferroelectric layer between the source electrode region and the drain electrode region; and an interlayer separating the ferroelectric layer from the anti-ferroelectric layer.

Description

Technical Field

[0001] The embodiments of the utility model relate to a ferroelectric field effect transistor device and an integrated chip. Background Art

[0002] Many of today's electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data when power is applied and can also store data in the absence of power. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal–oxide–semiconductor (CMOS) logic fabrication processes. Utility Model Content

[0003] According to one embodiment of the utility model, a ferroelectric field effect transistor (FeFET) device includes: a ferroelectric structure, including a ferroelectric layer and an antiferroelectric layer; a gate structure, arranged along a first surface of the antiferroelectric layer, so that the antiferroelectric layer separates the gate structure from the ferroelectric layer; an oxide semiconductor, arranged along a first surface of the ferroelectric layer, so that the ferroelectric layer separates the oxide semiconductor from the antiferroelectric layer; a source region and a drain region, arranged on the oxide semiconductor, wherein the gate structure extends laterally on the antiferroelectric layer between the source region and the drain region; and an interlayer, separating the ferroelectric layer from the antiferroelectric layer.

[0004] According to one embodiment of the utility model, an integrated chip includes: a semiconductor substrate; a conductive gate structure arranged on the semiconductor substrate; an antiferroelectric layer arranged on the conductive gate structure; an interlayer, the interlayer having a lower surface directly in contact with the upper surface of the antiferroelectric layer; a ferroelectric layer having a lower surface directly in contact with the upper surface of the interlayer; an oxide semiconductor arranged on the ferroelectric layer, the oxide semiconductor including a channel region directly located on the conductive gate structure; and a source region and a drain region, which are arranged on the oxide semiconductor and are laterally spaced apart from each other by a length corresponding to the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1Cross-sectional views of some embodiments of ferroelectric field effect transistor (FeFET) devices having a ferroelectric / antiferroelectric hybrid layer are shown.

[0007] Figure 2 A close-up view of some embodiments of multi-grain crystal structures of ferroelectric or antiferroelectric layers is shown.

[0008] Figure 3 A cross-sectional view of an integrated circuit is shown, wherein a FeFET device is disposed intermediate adjacent metal layers of an interconnect structure of the integrated circuit.

[0009] Figure 4 A cross-sectional view of an integrated circuit is shown in which a FeFET device has a gate structure with a height corresponding to the gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) on the integrated circuit.

[0010] Figure 5 A cross-sectional view of an integrated circuit is shown in which a FeFET device has a gate structure corresponding to a doped region in a substrate of the integrated circuit.

[0011] Figure 6 A perspective view of an integrated circuit including a FeFET device as part of a three-dimensional memory array is shown.

[0012] Figure 7 An exemplary schematic diagram of a FeFET memory circuit having a memory array including FeFET devices each having a ferroelectric / antiferroelectric mixed layer is shown.

[0013] Figure 8 A graph showing gate voltage versus drain current for a FeFET device according to some embodiments is shown.

[0014] Figures 9 to 15 Cross-sectional views showing some embodiments of methods of forming an integrated chip including a ferroelectric / antiferroelectric hybrid layer.

[0015] Fig.16 Flowchart illustrating some embodiments of a method of forming an integrated chip including a FeFET device having a ferroelectric / antiferroelectric hybrid layer. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the utility model. The specific examples of components and configurations described below are for simplifying the disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the disclosure may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of a component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] A ferroelectric field-effect transistor (FeFET) device is a type of ferroelectric device that includes a ferroelectric material disposed between a conductive gate structure and a channel region, wherein the channel region is disposed between a source region and a drain region. During operation of a FeFET device, application of a gate voltage to the gate structure generates an electric field that establishes a dipole moment in the ferroelectric material. Depending on the value of the gate voltage, the direction of the dipole moment (e.g., polarization) may be in one of a variety of discrete directions. Because the threshold voltage of a FeFET device (e.g., the minimum gate-to-source voltage that forms a conductive path between the source region and the drain region) is dependent on the polarization in the ferroelectric material, different polarizations effectively split the threshold voltage of the FeFET device into different values ​​corresponding to different data states. When the gate voltage / electric field is removed, the polarization state persists.

[0019] A ferroelectric device including a ferroelectric dominant lattice structure has only one positive polarization state and only one negative polarization state (two states total), which can be used to store one bit in a single memory cell. In contrast, a ferroelectric device including an antiferroelectric dominant lattice structure has two positive polarization states and two negative polarization states (four states total), which can be used to store two digital bits in a single memory cell. Thus, the use of antiferroelectric dominant materials can enable twice the amount of data to be stored in the same footprint, thereby reducing memory size and / or increasing data storage density, compared to a memory cell made of only ferroelectric dominant materials.

[0020] One method for making a ferroelectric device with an antiferroelectrically dominated lattice structure is to increase the percentage of dopants in the ferroelectric material. For example, for hafnium zirconium oxide (HZO) (e.g., Hf 1-x Zr x O) ferroelectric devices, increasing the Zr mole / dopant concentration (e.g., x) to greater than 70% can achieve a tetragonal lattice structure with antiferroelectric properties. This makes the HZO formulation more complex and may result in uneven Hf / Zr distribution in the HZO film. In addition, Zr-rich HZO exhibits a strong wake-up effect, in which the polarization increases over time as the number of write / read electric field cycles increases. The wake-up effect has a negative impact on durability and leads to unstable performance. In addition, ferroelectric devices with high Zr dopant concentrations may suffer from undesirable current leakage, which ultimately degrades the performance and / or stability of the FeFET device. Such current leakage may occur due to device fatigue, such as device aging, and / or may occur due to defects generated over time during polarization switching. For example, if there are a large number of oxygen defects in the oxide semiconductor and / or ferroelectric film, this may lead to a potential pathway for device breakdown.

[0021] Thus, in summary, various embodiments of the present disclosure are directed to an integrated chip having a FeFET device including a ferroelectric structure, the ferroelectric structure including a ferroelectric layer and an antiferroelectric layer with improved durability properties. Specifically, the ferroelectric layer exhibits a dominant orthorhombic crystalline structure, which exhibits ferroelectric properties, and the antiferroelectric layer exhibits a dominant tetragonal crystalline structure, which exhibits antiferroelectric properties. The interlayer separates the ferroelectric layer from the antiferroelectric layer and enhances the growth of tetragonal crystalline grains in the antiferroelectric layer. The interlayer is also used to suppress current leakage, for example, by promoting the formation of large grains in the ferroelectric structure, thereby helping to suppress current leakage due to defects.

[0022] Figure 1 A cross-sectional view of a ferroelectric field effect transistor (FeFET) device 100 according to some embodiments is shown. The FeFET device 100 includes a ferroelectric structure 104 disposed between an oxide semiconductor 106 and a conductive gate structure 102. A source region 108 and a drain region 109 are also disposed on the oxide semiconductor 106, and the source region 108 and the drain region 109 are separated from the ferroelectric structure 104 by the oxide semiconductor 106. Figure 1 In the illustrated embodiment, the gate structure 102 extends the entire channel length (e.g., in a range from 3 nanometers (nm) to 100 nanometers) between the source region 108 and the drain region 109, but in other embodiments, the gate structure 102 may only partially extend laterally between the source region 108 and the drain region 109. A cap structure 116 (e.g., which may include silicon dioxide and / or a high-k dielectric material (e.g., HfO2, Al2O3, TiO2)) may reside on the oxide semiconductor 106 and may have sidewalls aligned with the outer sidewalls of the oxide semiconductor 106. The cap structure 116 may have a thickness of 10 angstroms to 200 angstroms. A dielectric structure 118 (e.g., a silicon dioxide layer or a low-k dielectric layer) may surround the cap structure 116 and the oxide semiconductor 106.

[0023] In some embodiments, the oxide semiconductor 106 includes one or more of indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide, indium tungsten oxide (IWO), indium tungsten zinc oxide, indium zinc oxide (IZO), zinc oxide, and / or Sn-doped oxide semiconductor materials. In some cases, the oxide semiconductor 106 includes In x Ga y Znz MO, where M may be Ti, Al, Ag, W, Ce, or Sn; and x, y, and z are each in a range between 0 and 1. The gate structure 102, source region 108, and drain region 109 may each have a thickness between 50 angstroms and 500 angstroms and may include a metal, such as tantalum nitride (TaN), titanium (Ti), tungsten (W), titanium nitride (TiN), molybdenum, copper, gold, zinc, aluminum, or the like. In various embodiments, the gate structure 102 corresponds to a word line of a FeRAM device (see, e.g., further discussed herein). Figure 7 ).

[0024] Compared to related FeFET devices that include only a single ferroelectric layer, Figure 1 The ferroelectric structure 104 shown includes a ferroelectric layer 110 exhibiting ferroelectric properties and an antiferroelectric layer 112 exhibiting antiferroelectric properties. The interlayer 114 separates the ferroelectric layer 110 from the antiferroelectric layer 112 and serves to prevent crystal growth between the ferroelectric layer 110 and the antiferroelectric layer 112, while inducing larger crystalline growth on either side of the interlayer 114, which can help reduce current leakage.

[0025] The ferroelectric layer 110 may include hafnium oxide (eg, Hf 1-x Zr x O or similar materials), and the antiferroelectric layer 112 may also include hafnium oxide (eg, Hf 1-y Zr y O), where x and y are molar concentrations of Zr and are different from each other. In some cases, x is less than 0.70, which can provide a homogenous Zr distribution through the HZO lattice and reduce the wake-up effect. For example, x can be in the range between 0 and 0.5, and y can be in the range between 0.5 and 1. The ferroelectric layer 110 can be thicker than the antiferroelectric layer 112, can have the same thickness as the antiferroelectric layer 112, or can be thinner than the antiferroelectric layer 112.

[0026] The ferroelectric layer 110 may have a lattice that is oriented differently than the lattice of the antiferroelectric layer 112. For example, the ferroelectric layer 110 may have a predominantly orthorhombic crystal lattice, while the antiferroelectric layer 112 has a predominantly tetragonal crystal lattice. Thus, the ferroelectric layer has a first percentage of tetragonal crystal lattice per unit volume, and the antiferroelectric layer has a second percentage of tetragonal crystal lattice per unit volume, wherein the second percentage is greater than the first percentage. Furthermore, the ferroelectric layer 110 may be an orthorhombic crystal lattice of greater than 50% per unit volume, an orthorhombic crystal lattice of greater than 70% per unit volume, or even an orthorhombic crystal lattice of greater than 90% per unit volume; and the antiferroelectric layer 112 may have a tetragonal crystal lattice of greater than 50% per unit volume, a tetragonal crystal lattice of greater than 70% per unit volume, or even a tetragonal crystal lattice of greater than 90% per unit volume. In one case, the percentage of orthorhombic crystal lattice per unit volume in the ferroelectric layer 110 is greater than the percentage of tetragonal crystal lattice per unit volume in the antiferroelectric layer 112. For example, in some instances, the ratio of the percentage of orthorhombic crystals per unit volume in the ferroelectric layer 110 to the percentage of tetragonal crystals per unit volume in the antiferroelectric layer 112 is in a range of 15:1 to 25:1. Such a ratio of crystalline lattice structures can help provide ferroelectric and antiferroelectric properties.

[0027] In some cases, the interlayer 114 comprises: a metal oxide, such as titanium oxide, aluminum oxide, magnesium oxide, hafnium oxide, or indium oxide; or a metal, such as titanium, platinum, gold, or nickel. In some cases, the interlayer has a 1×10 -6 Meter (m) / Kelvin (K) to 1×10 -4 The interlayer 114 may have a thickness of less than 1 nanometer, which promotes high-quality crystal growth on the surface of the interlayer 114.

[0028] The interlayer 114 provides a break between the crystal lattice of the ferroelectric layer 110 and the crystal lattice of the antiferroelectric layer 112, and promotes the dominant phase transition of the ferroelectric structure 104 from the orthorhombic phase to the tetragonal phase. By appropriately introducing the interlayer 114, antiferroelectric properties are induced in the ferroelectric structure 104 without increasing the Zr doping level. Therefore, compared to other methods with high Zr doping (where Hf (1-x) Zr x O is greater than 0.7), less than 70% Zr doping can be used for the ferroelectric structure 104, so the dopant distribution is more uniform and the wake-up effect is reduced. Therefore, the stability of the ferroelectric structure can be improved due to better ferroelectric durability.

[0029] Furthermore, in some examples, due to the presence of the interlayer 114, the ferroelectric layer 110 and / or the antiferroelectric layer 112 can have a maximum grain width and / or an average grain size greater than 20 microns, which can be significantly larger than conventional grain sizes and can help reduce current leakage along grain boundaries within the ferroelectric structure 104. Figure 2 ( Figure 2 1 ) shows a close-up view of a crystalline structure 200 corresponding to a ferroelectric layer 110 or an antiferroelectric layer 112, the crystalline structure 200 being composed of junction cores 202 separated by grain boundaries 204. As indicated by line 206, a maximum grain size width can be measured from one edge of a grain 202a to another edge of the grain 202a using a straight line (206) through the grain, which yields a maximum width measurement of the grain 202a. Again, in some cases, such maximum grain size width represented by line 206 can be greater than 20 microns. In other cases, the crystalline structure 200 can have an average grain size greater than 20 microns. This average grain size can be measured by selecting a center point 208 on the grain 202b and then measuring the distance (e.g., radius) along an outwardly extending line 210 until the edge of the grain 202b is reached, and measuring additional distances from the center point 208 using additional outwardly extending lines in this manner until a representative number of lines are reached, and then averaging the distances of these lines and multiplying by two to find the approximate grain size (e.g., diameter) of the grain 202b. This process can be repeated for other grains, and the average grain size of the entire ferroelectric layer 110 and / or the entire antiferroelectric layer 112 can be determined.

[0030] although Figure 1 The ferroelectric structure 104 has been shown in the context of a FeFET device 100, however it should be understood that the ferroelectric structure 104 may also be included in other devices such as, for example, a metal-ferroelectric-metal (MFM) capacitor structure. In addition, in some cases, the orientation of the ferroelectric layer 110 and the orientation of the antiferroelectric layer 112 may be "flipped" so that the ferroelectric layer 110 is closer to the gate structure 102 and the antiferroelectric layer 112 is closer to the oxide semiconductor 106.

[0031] Figures 3 to 6 Several examples are shown of how the FeFET device 100 may be included as part of an integrated circuit along with other devices and interconnect (eg, wiring) structures.

[0032] Figure 3Some embodiments of an integrated circuit 300 are shown including a semiconductor substrate 302 having an interconnect structure 304 thereon, and wherein the FeFET device 100 is arranged between adjacent metal lines in the interconnect structure 304. The semiconductor substrate 302 may be embodied as a single crystal silicon substrate, a semiconductor on insulator (SOI) substrate, or some other semiconductor substrate.

[0033] A semiconductor device including a plurality of device terminals is disposed in and / or on the substrate. In the example shown, the semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET) 305, but in other examples, the semiconductor device may be another active device (e.g., a bipolar junction transistor (BJT), a FinFET or a junction FET (JFET), etc.), a passive device (e.g., a diode, a resistor, or a capacitor, etc.). The MOSFET 305 shown includes a source region 306 and a drain region 308, both of which have a first conductivity type. A channel region 310 separates the source region 306 from the drain region 308 and has a second conductivity type opposite to the first conductivity type. A conductive gate electrode 312 is disposed on the channel region 310, and the conductive gate electrode 312 may include doped polysilicon or metal. A gate dielectric 314, which may be made of silicon dioxide or a high-k dielectric material, separates the gate electrode 312 from the channel region 310. Sidewall spacers 315, which may be made of, for example, silicon nitride, are disposed on the outer edges of the gate electrode 312. A dielectric layer 316, such as silicon dioxide or a low-k dielectric, is disposed on the gate electrode 312 and the source and drain regions 306, 308. A contact 318, made of a metal, such as tungsten, copper, aluminum, titanium, nickel, and / or tantalum, extends vertically from the source and drain regions 306, 308, and the gate electrode 312 through the dielectric layer 316 and through the etch stop layer 320.

[0034] The interconnect structure 304 includes a first metal layer 322, a second metal layer 324, and a third metal layer 326 and higher metal layers (not shown). Each of these metal layers may include metal lines extending into the plane of the page and / or extending across the page to connect semiconductor devices (e.g., MOSFET 305) to each other, thereby achieving a desired circuit configuration. Vias (e.g., vias 328, 329) extend in a vertical direction through one or more of the stacked multiple interlayer dielectric (ILD) layers 330a-330b and extend between adjacent metal layers to couple metal layers at different heights to each other. In some embodiments, the stacked multiple ILD layers 330a-330b may include one or more of silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, and the like. In various embodiments, one or more etch stop layers 332a-332b may include carbides (e.g., silicon carbide, silicon oxycarbide, or similar carbides), nitrides (e.g., silicon nitride, silicon oxynitride, or similar nitrides), or the like. Metal layers and vias typically include metals and may include copper, aluminum, tantalum, and / or titanium, among others.

[0035] exist Figure 3In the example shown, a ferroelectric field effect transistor (FeFET) device 100 is disposed between a first metal layer 322 and a second metal layer 324. However, in other embodiments, the FeFET device 100 may be located between other (e.g., higher) metal layers. The FeFET device 100 includes a ferroelectric structure 104 disposed between an oxide semiconductor 106 and a gate structure 102. A source region 108 and a drain region 109 are also disposed on the oxide semiconductor 106 and separated from the ferroelectric structure 104 by the oxide semiconductor 106. A cap structure 116 may be disposed on the oxide semiconductor 106, and an ILD layer (e.g., a dielectric layer 316) may surround the cap structure 116 and the oxide semiconductor 106. In some embodiments, due to the thickness of the FeFET device 100, other areas of the circuit that do not include the FeFET device may have vias (e.g., vias 329) that are extended in height relative to vias (e.g., vias 328) located between other metal layers. Likewise, the FeFET device 100 can provide denser memory storage than other approaches due to the presence of the ferroelectric structure 104, which can include the ferroelectric layer 110, the antiferroelectric layer 112, and the interlayer 114. Furthermore, in some cases, the orientation of the FeFET device 100 can be "flipped" in the vertical direction so that the gate structure 102 is closer to the second metal layer 324 and the cap structure 116 is closer to the first metal layer 322. The ferroelectric layer 110 and the antiferroelectric layer 112 can also be "flipped" in various configurations so that the ferroelectric layer 110 is closer to the gate structure 102 and the antiferroelectric layer 112 is closer to the oxide semiconductor 106 (or vice versa).

[0036] Figure 4 Some embodiments of another integrated circuit 400 are shown including a semiconductor substrate 302 with an interconnect structure 304 thereon and wherein the FeFET device 100 has a gate structure 102 having a height corresponding to the height of a gate electrode 312 of a metal oxide semiconductor field effect transistor (MOSFET) 305 on the integrated circuit.

[0037] exist Figure 4 In the embodiment, as an example, the semiconductor device shown is also shown as MOSFET 305; and for convenience, the features of MOSFET 305 are marked as Figure 3The interconnect structure also includes a first metal layer 322, a second metal layer 324, and a third metal layer 326 and higher metal layers (not shown). Each of these metal layers may include metal lines extending into the plane of the page and / or extending across the page to connect semiconductor devices to each other, thereby achieving a desired circuit configuration. Vias 328, 329 extend through one or more of the multiple ILD layers 330a-330b in a vertical direction and extend between adjacent metal layers to couple metal layers at different heights to each other.

[0038] exist Figure 4 In the example shown, a ferroelectric field effect transistor (FeFET) device 100 is disposed between a first metal layer 322 and a semiconductor substrate 302. The gate electrode 312 of the MOSFET 305 and the gate structure 102 of the FeFET device 100 may have equal thicknesses, and the uppermost surface of the gate structure 102 of the FeFET device 100 may be coplanar with the uppermost surface of the gate electrode 312 of the MOSFET 305. The FeFET device 100 includes a ferroelectric structure 104 disposed between an oxide semiconductor 106 and the gate structure 102. A source region 108 and a drain region 109 are also disposed on the oxide semiconductor 106 and separated from the ferroelectric structure 104 by the oxide semiconductor 106. A cap structure 116 may be disposed on the oxide semiconductor 106, and a dielectric layer 316 may surround the cap structure 116 and the oxide semiconductor 106. The gate dielectric 314 may separate the gate structure 102 of the FeFET from the semiconductor substrate 302. Likewise, due to the presence of the ferroelectric structure 104, which may include the ferroelectric layer 110, the antiferroelectric layer 112, and the interlayer 114, the FeFET device may provide denser memory storage than other approaches.

[0039] Figure 5 Some embodiments of an integrated circuit 500 are shown including a semiconductor substrate 302 with an interconnect structure 304 thereon, and wherein a FeFET device 100 has a gate structure 102 corresponding to a doped region in the semiconductor substrate 302 .

[0040] Figure 6A three-dimensional view of some alternative embodiments of an integrated chip 620 including a FeFET device having a ferroelectric structure 104, the ferroelectric structure 104 including a ferroelectric layer 110 and an antiferroelectric layer 112 separated from each other by an interlayer 114 is shown. The integrated chip 620 includes a lower dielectric layer 602 disposed on a semiconductor substrate 302. A gate structure 102 is disposed on the lower dielectric layer 602, and a dielectric layer 604 is disposed on the gate structure 102. The ferroelectric structure 104 is disposed on the sidewalls of the lower dielectric layer 602, the sidewalls of the gate structure 102, and the sidewalls of the dielectric layer 604. An oxide semiconductor 106 is disposed along the sidewall of the ferroelectric structure 104 facing away from the gate structure 102. A source region 108 and a drain region 109 are disposed on one side of the oxide semiconductor 106, and the source region 108 and the drain region 109 extend perpendicular to the upper surface of the semiconductor substrate 302. The ferroelectric structure 104 includes a ferroelectric layer 110 and an antiferroelectric layer 112 . The ferroelectric layer 110 and the antiferroelectric layer 112 extend perpendicularly to the upper surface of the semiconductor substrate 302 and are separated from each other by an interlayer 114 .

[0041] Figure 7 An exemplary schematic diagram of a FeFET memory circuit 700 is shown having FeFET devices each including a ferroelectric structure including a ferroelectric layer and an antiferroelectric layer separated from each other by an interlayer.

[0042] The FeFET memory circuit 700 includes a FeFET memory array 702, which includes a plurality of FeFET devices 704. 1,1 To 704 n,m The plurality of FeFET devices 704 1,1 To 704 n,m Arranged in columns and / or rows within the FeFET memory array 702. The plurality of FeFET devices 704 within a column 1,x To 704 n,x operatively coupled to word line WL x (x=1 to m). The plurality of FeFET devices 704 x,1 To 704 x,m having a plurality of bit lines BL operably coupled to the bit lines BL along the rows x (x=1 to n) and have respective drains along the rows operably coupled to source lines SL x (x=1 to n) corresponding source. Each FeFET device 704 1,1 To 704 n,m Can have Figures 1 to 6 The structure shown in any one of .

[0043] Word lines WL1 to WL m, bit lines BL1 to BL n and source lines SL1 to SL n coupled to the control circuit 706. In some embodiments, the control circuit 706 includes a circuit coupled to the word lines WL1 to WL m The word line decoder 710 is coupled to the bit lines BL1 to BL n The bit line decoder 708 is coupled to the source lines SL1 to SL n In some embodiments, the control circuit 706 further includes a source line decoder 712 coupled to the bit lines BL1 to BL n or source lines SL1 to SL n In some embodiments, the control circuit 706 further includes a control unit 716 configured to send address information S to the word line decoder 710, the bit line decoder 708 and / or the source line decoder 712. ADR , so that the control circuit 706 can selectively control the plurality of FeFET devices 704 1,1 To 704 n,m One or more of them are accessed.

[0044] For example, during operation, the control unit 716 is configured to provide address information S to the word line decoder 710, the bit line decoder 708, and the source line decoder 712. ADR Based on address information S ADR , the word line decoder 710 is configured to selectively provide word lines WL1 to WL m At the same time, the bit line decoder 708 is configured to selectively apply a bias voltage to the bit lines BL1 to BL n and / or the source line decoder 712 is configured to selectively apply a bias voltage to the source lines SL1 to SL n By applying a bias voltage to word lines WL1 to WL m The selected one of the bit lines BL1 to BL n The selected one and / or source lines SL1 to SL n By applying a bias voltage to a selected one of the plurality of FeFET devices 704, the FeFET storage circuit 700 can be operated to supply power to the plurality of FeFET devices 704. 1,1 To 704 n,m Writing different data states and / or from the plurality of FeFET devices 704 1,1 To 704 n,m Read data status.

[0045] Figure 8A graph 800 is shown that illustrates an exemplary storage margin of a FeFET device. As shown in graph 800, when the FeFET device stores a first data state (e.g., a logic "1"), the FeFET device will have a threshold voltage corresponding to the drain current shown by line 802. When the FeFET device stores a second data state (e.g., a logic "0"), the FeFET device will have a threshold voltage corresponding to the drain current shown by line 804.

[0046] Figures 9 to 15 Cross-sectional views 900 to 1500 of some embodiments of a method of forming an integrated chip including a FeFET device having a polarization enhanced structure are shown. Figures 9 to 15 , however, it should be understood that Figures 9 to 15 The structure disclosed in the method is not limited to this method, but can exist independently as a structure independent of the method.

[0047] like Fig. 9 As shown in the cross-sectional view 900 of , a gate structure 102 is formed. In some embodiments, the gate structure 102 may be formed on a semiconductor substrate 302. In various embodiments, the semiconductor substrate 302 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer and any other type of semiconductor and / or epitaxial layer associated therewith. The gate structure 102 may include one or more conductive materials. In some embodiments, the one or more conductive materials may include and / or may be metals, such as titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, or the like. In various embodiments, the gate structure 102 may be formed by one or more deposition processes (e.g., atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PE-CVD) process, or the like).

[0048] like Fig.10As shown in the cross-sectional view 1000 of , a ferroelectric structure 1002 may be formed on the gate structure 102. The ferroelectric structure 1002 may include a ferroelectric material. In some embodiments, one or more ferroelectric materials may include hafnium oxide, hafnium zinc oxide, or the like. In various embodiments, the ferroelectric structure 1002 may be formed by one or more deposition processes (e.g., an ALD process, a CVD process, a PE-CVD process, or the like). For example, an antiferroelectric layer 112 is formed on the gate structure 102, and an interlayer 114 is formed on the antiferroelectric layer 112. Then, a ferroelectric layer 110 is formed on the interlayer 114. In some embodiments, the antiferroelectric layer 112 and the interlayer 114 are deposited in situ in a deposition chamber, and the ferroelectric layer 110 may also be formed in situ in the deposition chamber as needed. In other cases, the antiferroelectric layer 112 and the interlayer 114 are deposited in situ in a deposition chamber, and then the structure is removed from the deposition chamber prior to forming the ferroelectric layer 110 .

[0049] like Fig.11 As shown in the cross-sectional view 1100 of , an oxide semiconductor layer 1102 is formed on the ferroelectric structure 1002. In some embodiments, one or more oxide semiconductor materials may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc oxide (IZO), zinc oxide (ZnO), or similar materials. In various embodiments, the oxide semiconductor layer 1102 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, or similar process). A cap layer 1104 may be formed on the semiconductor layer. The cap layer 1104 may include silicon dioxide and / or a high dielectric constant dielectric material (e.g., HfO2, Al2O3, TiO2). In various embodiments, the cap layer 1104 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, or similar process).

[0050] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a first patterning process is performed to pattern the top cap layer (eg, Fig.11 The cap layer 1104 shown) and the oxide semiconductor layer (eg, Fig.11 The first patterning process removes the oxide semiconductor layer (eg, Fig.11 Some portions of the oxide semiconductor layer 1102 are formed to form the oxide semiconductor 106, and the cap layer (eg, Fig.11 The top cap layer 1104 is removed to form a top cap structure 116 and expose the upper surface of the gate structure 102. In some embodiments, the first patterning process may also remove a portion of the gate structure 102.

[0051] In some embodiments, the first patterning process may be based on the top cap layer (eg, Fig.11 The first etchant 1202 is selectively exposed to the oxide semiconductor layer and the ferroelectric layer by a first masking structure 1204 on the cap layer 1104 shown. In some embodiments, the first masking structure 1204 may include a photosensitive material (e.g., a photoresist). In other embodiments, the first masking structure 1204 may include a dielectric masking layer (e.g., silicon oxide, silicon dioxide, or a similar material), a hard mask, and / or the like. In some embodiments, the first etchant 1202 may include a dry etchant (e.g., with a fluorine chemistry, a chlorine chemistry, or a similar chemistry). In other embodiments, the first etchant 1202 may include a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, or a similar material).

[0052] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a dielectric layer 1302 is formed on the cap structure and the oxide semiconductor. The dielectric layer 1302 extends along the upper surface and sidewalls of the cap structure and the upper surface and sidewalls of the oxide semiconductor. In various embodiments, the dielectric layer 1302 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, or similar process).

[0053] like Fig.14 As shown in the cross-sectional view 1400 of , a second patterning process is performed to pattern the dielectric layer 1302 to form a dielectric structure 118, and the dielectric structure 118 includes a source contact hole 1402a and a drain contact hole 1402b. In some embodiments, the source contact hole 1402a and the drain contact hole 1402b extend through the dielectric structure 118 and the cap structure 116 to expose the upper surface of the oxide semiconductor 106. In some embodiments, the second patterning process is performed by selectively exposing the dielectric layer 1302 to a second etchant 1406 according to the second masking structure 1404. In some embodiments, the second etchant 1406 may include a dry etchant (e.g., a fluorine chemistry, a chlorine chemistry, or the like).

[0054] like Fig.15As shown in the cross-sectional view 1500 of , a conductive material is formed in the source contact hole 1402a and the drain contact hole 1402b. In some embodiments, the conductive material may include a metal, such as copper, aluminum, tungsten, cobalt, or the like. In some embodiments, the conductive material may be deposited by one or more of a deposition process and a plating process. In some embodiments, a deposition process may be used to form a seed layer of the conductive material, followed by a plating process to fill the source contact hole 1402a and the drain contact hole 1402b. In some embodiments, after the conductive material is formed, a planarization process may be performed to remove excess conductive material from the dielectric layer and form the source region 108 and the drain region 109.

[0055] Fig.16 A flow chart illustrating some embodiments of a method 1600 of forming an integrated chip including a FeFET device with a polarization enhanced structure.

[0056] Although the disclosed method 1600 is shown and described as a series of actions or events in this article, it should be understood that the order in which such actions or events are shown should not be interpreted as having a limiting meaning. For example, some actions may occur in different orders and / or occur simultaneously with other actions or events other than the actions or events shown and / or described herein. In addition, all the actions shown may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions in the actions depicted herein may be implemented in one or more separate actions and / or stages.

[0057] At act 1602, a ferroelectric layer is formed on the conductive gate layer. Fig.10 Cross-sectional view 1000 of some embodiments corresponding to act 1602 is shown.

[0058] At act 1604, an oxide semiconductor layer is formed on the ferroelectric layer, and a cap layer is formed on the oxide semiconductor layer. Fig.11 Cross-sectional view 1100 of some embodiments corresponding to act 1604 is shown.

[0059] At act 1606, one or more patterning processes are performed to remove portions of the cap layer and portions of the ferroelectric structure to expose the oxide semiconductor. Fig.12 Cross-sectional view 1200 of some embodiments corresponding to act 1606 is shown.

[0060] At act 1608, a dielectric layer is formed over the ferroelectric structure and the cap structure. Fig.13 Cross-sectional view 1300 of some embodiments corresponding to act 1608 is shown.

[0061] At action 1610, one or more additional patterning processes are performed to form a source contact hole and / or a drain contact hole extending through the dielectric layer and through the cap structure to expose the oxide semiconductor. Fig.14 Cross-sectional view 1400 of some embodiments corresponding to act 1610 is shown.

[0062] At act 1612, a conductive material is formed within the source contact hole and / or the drain contact hole. Fig.15 Cross-sectional view 1500 of some embodiments corresponding to act 1612 is shown.

[0063] Therefore, in some embodiments, a ferroelectric field effect transistor (FeFET) device includes: a ferroelectric structure, including a ferroelectric layer and an antiferroelectric layer; a gate structure, arranged along a first surface of the antiferroelectric layer, so that the antiferroelectric layer separates the gate structure from the ferroelectric layer; an oxide semiconductor, arranged along a first surface of the ferroelectric layer, so that the ferroelectric layer separates the oxide semiconductor from the antiferroelectric layer; a source region and a drain region, arranged on the oxide semiconductor, wherein the gate structure extends laterally on the antiferroelectric layer between the source region and the drain region; and an interlayer, separating the ferroelectric layer from the antiferroelectric layer.

[0064] In some examples, the ferroelectric layer comprises Hf 1-x Zr x O, and the antiferroelectric layer comprises Hf 1-y Zr y O, where x is different from y.

[0065] In some examples, x is between 0 and 0.5, and y is between 0.5 and 1.

[0066] In some examples, the interlayer comprises a metal oxide or a metal.

[0067] In some examples, the interlayer comprises the metal oxide, and the metal oxide comprises titanium oxide, aluminum oxide, magnesium oxide, hafnium oxide, or indium oxide; or wherein the interlayer comprises the metal, and the metal comprises titanium, platinum, gold, or nickel.

[0068] In some examples, the ferroelectric layer has a first percentage of tetragonal crystal lattice per unit volume, and the antiferroelectric layer has a second percentage of tetragonal crystal lattice per unit volume, the second percentage being greater than the first percentage.

[0069] In some examples, a ratio of a first percentage of orthorhombic crystals per unit volume in the ferroelectric layer to a second percentage of tetragonal crystals per unit volume in the antiferroelectric layer is in a range of 15:1 to 25:1.

[0070] In some examples, at least one of the ferroelectric layer and the antiferroelectric layer is a polycrystalline structure in which a plurality of junction dies are separated from each other by grain boundaries, and the plurality of junction dies have an average grain size greater than 20 microns.

[0071] In some examples, the interlayer has 1×10 -4 Meter / Kelvin (K) to 1×10 -6 Coefficient of thermal expansion in meters per kelvin.

[0072] In some examples, the interlayer has a thickness of less than 1 nanometer.

[0073] In some examples, the oxide semiconductor includes one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide.

[0074] In some examples, the source region is coupled to a source line, the drain region is coupled to a bit line, and the gate structure is coupled to a word line.

[0075] In some examples, the FeFET device further includes a substrate; wherein the gate structure is disposed along a first side of the substrate; and wherein the gate structure is disposed in a vertical direction between the first side of the substrate and the ferroelectric structure.

[0076] In some instances, an integrated chip includes: a semiconductor substrate; a conductive gate structure arranged on the semiconductor substrate; an antiferroelectric layer arranged on the conductive gate structure; an interlayer comprising a metal or a metal oxide, the interlayer having a lower surface directly in contact with an upper surface of the antiferroelectric layer; a ferroelectric layer having a lower surface directly in contact with an upper surface of the interlayer; an oxide semiconductor arranged on the ferroelectric layer, the oxide semiconductor including a channel region directly located on the conductive gate structure; and a source region and a drain region disposed on the oxide semiconductor and laterally spaced apart from each other by a length corresponding to the channel region.

[0077] In some examples, the ferroelectric layer has a first percentage of tetragonal crystal lattice per unit volume, and the antiferroelectric layer has a second percentage of tetragonal crystal lattice per unit volume, the second percentage being greater than the first percentage.

[0078] In some examples, the ferroelectric layer comprises Hf 1-x Zr x O, and the antiferroelectric layer comprises Hf 1-y Zr y O, where x is less than 0.5 and greater than 0, and y is greater than 0.5 and less than 1.

[0079] In some examples, a ferroelectric field effect transistor (FeFET) device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally located between the source region and the drain region. A polarization enhancement structure is disposed on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type different from the first semiconductor type.

[0080] In some instances, a method of forming a FeFET device includes: receiving a substrate; forming a gate structure on the substrate; forming an antiferroelectric layer on the gate structure; forming an interlayer comprising a metal or a metal oxide, the interlayer having a lower surface directly in contact with an upper surface of the antiferroelectric layer; forming a ferroelectric layer, the ferroelectric layer having a lower surface directly in contact with an upper surface of the interlayer; forming an oxide semiconductor layer on the ferroelectric layer; forming a dielectric layer on the oxide semiconductor layer; performing a first patterning process to form a source opening and a drain opening through the dielectric layer to expose the oxide semiconductor layer; and forming a conductive material within the source opening and the drain opening.

[0081] In some examples, the antiferroelectric layer and the interlayer are formed in-situ in a deposition chamber.

[0082] In some examples, the antiferroelectric layer, the interlayer, and the ferroelectric layer are formed in-situ in a deposition chamber.

[0083] In some examples, the oxide semiconductor layer includes indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, or zinc oxide.

[0084] The foregoing summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those with ordinary knowledge in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those with ordinary knowledge in the art can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A ferroelectric field effect transistor device, characterized in that include: A ferroelectric structure, including a ferroelectric layer and an antiferroelectric layer; a gate structure disposed along a first surface of the antiferroelectric layer such that the antiferroelectric layer separates the gate structure from the ferroelectric layer; an oxide semiconductor disposed along the first surface of the ferroelectric layer, such that the ferroelectric layer separates the oxide semiconductor from the antiferroelectric layer; A source region and a drain region are disposed on the oxide semiconductor, wherein the gate structure extends laterally on the antiferroelectric layer between the source region and the drain region; as well as An interlayer separates the ferroelectric layer from the antiferroelectric layer.

2. The ferroelectric field effect transistor device of claim 1, wherein the source region is coupled to a source line, the drain region is coupled to a bit line, and the gate structure is coupled to a word line.

3. The ferroelectric field effect transistor device of claim 1, further comprising: substrate; wherein the gate structure is disposed along a first side of the substrate; and The gate structure is disposed between the first side of the substrate and the ferroelectric structure in a vertical direction.

4. The ferroelectric field effect transistor device of claim 1, further comprising: The top cover structure is disposed on the oxide semiconductor. 5 . The ferroelectric field effect transistor device of claim 4 , wherein the cap structure has sidewalls aligned with outer sidewalls of the oxide semiconductor.

6. The ferroelectric field effect transistor device of claim 4, further comprising: The dielectric structure surrounds the top cover structure and the oxide semiconductor.

7. An integrated chip, characterized in that include: Semiconductor substrate; A conductive gate structure is arranged on the semiconductor substrate; an antiferroelectric layer disposed on the conductive gate structure; an interlayer having a lower surface in direct contact with an upper surface of the antiferroelectric layer; a ferroelectric layer having a lower surface in direct contact with the upper surface of the interlayer; an oxide semiconductor disposed on the ferroelectric layer, the oxide semiconductor including a channel region directly on the conductive gate structure; as well as The source region and the drain region are disposed on the oxide semiconductor and are laterally spaced apart from each other by a length corresponding to the channel region.

8. The integrated chip of claim 7, wherein the source region is coupled to a source line, the drain region is coupled to a bit line, and the conductive gate structure is coupled to a word line.

9. The integrated chip as claimed in claim 7, further comprising: The top cover structure is disposed on the oxide semiconductor. 10 . The integrated chip of claim 9 , wherein the cap structure has sidewalls aligned with outer sidewalls of the oxide semiconductor.

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