High-reliability SiC VDMOSFET structure

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a high-reliability SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure, which comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a sinking layer, a diffusion layer, a P well layer and an N well layer; a doping layer is formed between the sinking layer and the diffusion layer through ion implantation, and both the doping layer and the diffusion layer show weak charge conductivity; the P well layer comprises a first lightly-doped P well, a third lightly-doped P well, a first heavily-doped P well, a second heavily-doped P well, a second lightly-doped P well, a fourth lightly-doped P well and a fifth lightly-doped P well. According to the utility model, the N-doped layer is additionally arranged between the substrate and the epitaxy, the doped layer and the diffusion layer both show weak charge conductivity, and the doping concentration of the doped layer is higher than that of the diffusion layer, so that the semiconductor cannot be broken down easily even if higher drain voltage is accessed to the drain electrode, and meanwhile, the flow of charges in the diffusion layer cannot be hindered; and the charge conduction stability between the metal source electrode and the drain electrode is ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a high-reliability SiC VDMOSFET structure. Background Art

[0002] VDMOSFET is a power device that is developing rapidly at present. It has the characteristics of unique high input impedance, low driving power, high switching speed, excellent frequency characteristics, low noise, good thermal stability, radiation resistance and simple manufacturing process. It is widely used in various fields such as AC transmission, variable frequency power supply, switching voltage stabilizer power supply, etc., and has achieved good results.

[0003] The existing patent discloses a reliability-improved semiconductor device (publication number CN113035933A), including a device body with a cell region in the middle and a terminal protection zone and a cut-off zone at the edge, the device body including a semiconductor substrate with an insulating dielectric layer on the surface, a metal interconnection layer arranged above the insulating dielectric layer, and a protective layer arranged above the metal interconnection layer and extending to the cut-off zone, the metal interconnection layer is connected to the base or gate on the surface of the semiconductor substrate through a first contact hole on the surface of the device body, and a third contact hole with a bottom end extending to the semiconductor substrate is arranged on the surface of the cut-off zone of the device body, and a leakage discharge metal connecting the semiconductor substrate and the metal interconnection layer is arranged in the third contact hole. In the technology disclosed in the patent, since the diode undergoes a reverse recovery process from the on state to the off state during freewheeling, if the reverse recovery characteristics are poor, it will not only affect the switching characteristics of the device, but also cause the problem of increased switching power consumption and decreased circuit efficiency, thereby generating a large reverse peak current that damages the reliability of the device. Summary of the invention

[0004] The main technical problem solved by the utility model is to provide a high-reliability SiC VDMOSFET structure, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a high-reliability SiC VDMOSFET structure includes a plurality of mutually parallel MOS cells, wherein the MOS cells include a sink layer, a diffusion layer, a P-well layer, and an N-well layer;

[0006] Ions are implanted between the deposition layer and the diffusion layer to form a doping layer, the doping layer and the diffusion layer both have weak charge conductivity, and the phosphorus doping concentration of the doping layer is higher than that of the diffusion layer;

[0007] The P-well layer includes a lightly doped P-well 1, a lightly doped P-well 3, a heavily doped P-well 1, a heavily doped P-well 2, a lightly doped P-well 2, a lightly doped P-well 4 and a lightly doped P-well 5;

[0008] The N-well layer includes a lightly doped N-well layer 1, a lightly doped N-well layer 2, a heavily doped N-well layer and a lightly doped N-well layer 3;

[0009] The bottom layer of the MOS cell is ohmically connected to a drain, the top layer of the MOS cell is ohmically connected to a metal source, and a gate is embedded between the base layer of the MOS cell and the metal source.

[0010] Furthermore, the heavily doped P-well one and the lightly doped P-well two between adjacent MOS cells are integrated into one, and the heavily doped P-well two is located between the heavily doped P-well one and the lightly doped P-well two.

[0011] Furthermore, the heavily doped P-well 1, the heavily doped P-well 2 and the lightly doped P-well 3 are arranged horizontally from left to right.

[0012] Furthermore, the lightly doped P-well three, the lightly doped P-well four and the lightly doped P-well five all have weak charge conductivity, and the lightly doped P-well three, the lightly doped P-well four and the lightly doped P-well five are arranged vertically in an up-and-down manner.

[0013] Furthermore, when the gate is connected to a gate voltage, a charge channel is formed inside the lightly doped P-well 1 near the gate.

[0014] Furthermore, the top of the heavily doped P-well 2 protrudes upward and is embedded in the heavily doped N-well layer, wherein the heavily doped N-well layer is in an 'L' shape.

[0015] Furthermore, the lightly doped N-well layer 1, the lightly doped N-well layer 2 and the heavily doped N-well layer are arranged and distributed in a left-right lateral direction.

[0016] Furthermore, the doped layer, the diffused layer, the lightly doped N-well layer one and the lightly doped N-well layer two are doped with low concentration of phosphorus ions by ion implantation; the lightly doped P-well three, the lightly doped P-well five and the lightly doped P-well four are doped with low concentration of boron ions by ion implantation; the heavily doped P-well one and the heavily doped P-well two are doped with high concentration of boron ions by ion implantation.

[0017] Furthermore, an oxide layer is deposited between the gate and the base layer of the MOS cell.

[0018] Furthermore, when a voltage is applied to the gate, a depletion layer of the JFET region is formed inside the diffusion layer, and the JFET region in a single MOS cell is formed between two lightly doped P wells four.

[0019] The beneficial effects of the high reliability SiC VDMOSFET structure of the utility model are:

[0020] 1. The utility model adds an N-doped layer between the substrate and the epitaxy. Since both the doped layer and the diffusion layer have weak charge conductivity and the doping concentration of the doped layer is higher than that of the diffusion layer, the semiconductor will not be easily broken down when the drain is connected to a higher drain voltage, and the flow of charges in the diffusion layer will not be hindered, thereby ensuring the charge conduction stability between the metal source and the drain.

[0021] 2. The utility model divides the P-well layer into regions with gradually increasing doping concentrations, and the regions all show weak charge conductivity, which can effectively constrain the movement of charges, thereby ensuring that charge drifts and forms a charge channel only in a lightly doped P-well region. This can greatly reduce the intensity of the independent electric field formed inside the P-well layer, thereby reducing the total amount of parasitic charges under the influence of the independent electric field.

[0022] 3. The utility model can reduce the charge concentration injected into the drift region during the freewheeling period by setting up a laterally arranged variable concentration P well between adjacent MOS cells, accelerate the speed at which the charge is swept out of the drift region during the reverse recovery process, improve the charge storage effect of the PN junction, and solve the problems of increased switching power consumption and reduced device reliability caused by poor reverse recovery characteristics of MOS semiconductors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] Figure 1 It is a schematic diagram of the structure of a single MOS cell in the utility model;

[0025] Figure 2 It is a partial schematic diagram of a single MOS cell in the utility model.

[0026] In the figure: 1. drain; 2. substrate layer; 3. doping layer; 4. diffusion layer; 5. metal source; 6. gate; 7. trench; 8. lightly doped N-well layer 1; 9. lightly doped N-well layer 2; 10. heavily doped N-well layer; 11. lightly doped N-well layer 3; 12. lightly doped P-well 1; 13. lightly doped P-well 3; 14. heavily doped P-well 1; 15. heavily doped P-well 2; 16. lightly doped P-well 2; 17. lightly doped P-well 4; 18. lightly doped P-well 5; 19. charge channel; 20. oxide layer; 21. JFET region. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0028] like Figure 1-2As shown, according to one aspect of the utility model, a high-reliability SiC VDMOSFET structure is provided, comprising a plurality of mutually parallel MOS cells, the MOS cells comprising a sink layer 2, a diffusion layer 4, a P-well layer and an N-well layer. Ions are implanted between the sink layer 2 and the diffusion layer 4 to form a doping layer 3, the doping layer 3 and the diffusion layer 4 both exhibit weak charge conductivity, and the phosphorus doping concentration of the doping layer 3 is higher than the phosphorus doping concentration of the diffusion layer 4 (such as Figure 1 As shown), ions are implanted between the substrate layer 2 and the diffusion layer 4 to form a doping layer 3. Since both the doping layer 3 and the diffusion layer 4 have weak charge conductivity, and the doping concentration of the doping layer 3 is higher than that of the diffusion layer 4, the semiconductor will not be easily broken down when the gate is connected to a higher gate voltage, and the flow of charges in the diffusion layer 4 will not be hindered.

[0029] The P-well layer includes a lightly doped P-well 12, a lightly doped P-well 3 13, a heavily doped P-well 14, a heavily doped P-well 2 15, a lightly doped P-well 2 16, a lightly doped P-well 4 17 and a lightly doped P-well 5 18. Dividing the P-well layer into several levels can effectively reduce the intensity of the internal independent electric field that appears after a charge channel 19 is formed inside the P-well layer.

[0030] The N-well layer includes a lightly doped N-well layer 1 8, a lightly doped N-well layer 2 9, a heavily doped N-well layer 10 and a lightly doped N-well layer 3 11. The design of dividing the N-well layer into left and right lateral arrangements can suppress the influence of the gate electric field on the charges in the N-well layer and ensure that all the charges in the N-well layer flow into the interior of the metal source 5.

[0031] The bottom layer of the MOS cell is ohmically connected to a drain 1 , the top layer of the MOS cell is ohmically connected to a metal source 5 , and a gate 6 is embedded between the base layer of the MOS cell and the metal source 5 .

[0032] In this embodiment, the heavily doped P well 1 14 and the lightly doped P well 2 16 between adjacent MOS cells are integrated, and the heavily doped P well 2 15 is located between the heavily doped P well 1 14 and the lightly doped P well 2 16 (eg, Figure 2 As shown), the heavily doped P-well 15 can increase the charge flow barrier inside the P-well layer, so that the charges inside the P-well layer are difficult to move to the P-well layer of the adjacent MOS cell under the influence of the gate electric field.

[0033] In this embodiment, the heavily doped P well 1 14, the heavily doped P well 2 15 and the lightly doped P well 2 16 are arranged horizontally from left to right, the lightly doped P well 3 13, the lightly doped P well 4 17 and the lightly doped P well 5 18 are all weakly charged and conductive, and the lightly doped P well 3 13, the lightly doped P well 4 17 and the lightly doped P well 5 18 are arranged vertically from top to bottom (such as Figure 1As shown in the figure, the P-well layer is divided into lightly-doped P-well three 13, lightly-doped P-well five 18 and lightly-doped P-well four 17 with gradually increasing doping concentrations, and these regions all show weak charge conductivity, which can effectively restrain the movement of charges, thereby ensuring that charge drift occurs only in the lightly-doped P-well one 12 region and a charge channel 19 is formed, which can greatly reduce the intensity of the independent electric field formed inside the P-well layer.

[0034] In the present embodiment, when the gate 6 is connected to the gate voltage, a charge channel 19 is formed inside the lightly doped P-well 12 near the gate 6, and the top of the heavily doped P-well 2 15 protrudes upward and is embedded in the heavily doped N-well layer 10, wherein the heavily doped N-well layer 10 is in an "L" shape, and the lightly doped N-well layer 1 8, the lightly doped N-well layer 2 9 and the heavily doped N-well layer 10 are arranged horizontally from left to right (such as Figure 2 As shown in FIG. 1 , the lightly doped P-well 12 is designed to be upwardly protruding and embedded in the heavily doped N-well layer 10, which can greatly reduce the resistance of the charge channel 19 between the diffusion layer 4 and the heavily doped N-well layer 10.

[0035] In this embodiment, the doping layer 3 is doped with 4.1 to 5×10 15 mol / cm 3 Phosphorus;

[0036] Diffusion layer 4 is doped with 6.4~7×10 15 mol / cm 3 The phosphorus element has a doping concentration in the doping layer 4 that is higher than that in the diffusion layer 4 .

[0037] Among them, the lightly doped P well 313 is doped with 2.3~4.1×10 15 mol / cm 3 Boron element;

[0038] Lightly doped P well 518 doped with 4.2~6.5×10 15 mol / cm 3 Boron element;

[0039] Lightly doped P well 17 doped with 7.3~8×10 15 mol / cm 3 Boron element, so that the doping concentration gradually increases between the lightly doped P well three 13, the lightly doped P well five 18 and the lightly doped P well four 17. Among them, the lightly doped N well layer 18 is doped with 7.8-9.5×10 15 mol / cm 3 Phosphorus;

[0040] The lightly doped N-well layer 29 is doped with 2.3~4.3×10 15 mol / cm 3The phosphorus element has a doping concentration that gradually decreases between the lightly-doped N-well layer 1 8 and the lightly-doped N-well layer 2 9 .

[0041] Among them, the heavily doped P well-14 is doped with 1.5~2×10 18 mol / cm 3 Boron element;

[0042] Heavily doped P-well II 15 doped with 6.7~8.2×10 18 mol / cm 3 The doping concentration of the boron element increases gradually from the heavily doped P well 14 to the heavily doped P well 2 15 .

[0043] In this embodiment, an oxide layer 20 is deposited between the gate 6 and the base layer of the MOS cell. When a voltage is applied to the gate 6, a depletion layer of a JFET region 21 is formed inside the diffusion layer 4. The JFET region 21 in a single MOS cell is formed between two lightly doped P wells 17. The JFET region 21 can control the amount of charge conducted between the metal source 5 and the drain 1 in the semiconductor.

[0044] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A high reliability SiC VDMOSFET structure, characterized in that: It comprises a plurality of mutually parallel MOS cells, wherein the MOS cells comprise a sink layer (2), a diffusion layer (4), a P-well layer and an N-well layer; Ions are implanted between the deposition layer (2) and the diffusion layer (4) to form a doping layer (3), the doping layer (3) and the diffusion layer (4) both exhibit weak charge conductivity, and the phosphorus doping concentration of the doping layer (3) is higher than the phosphorus doping concentration of the diffusion layer (4); The P-well layer includes a lightly doped P-well 1 (12), a lightly doped P-well 3 (13), a heavily doped P-well 1 (14), a heavily doped P-well 2 (15), a lightly doped P-well 2 (16), a lightly doped P-well 4 (17) and a lightly doped P-well 5 (18); The N-well layer comprises a lightly doped N-well layer 1 (8), a lightly doped N-well layer 2 (9), a heavily doped N-well layer (10) and a lightly doped N-well layer 3 (11); The bottom layer of the MOS cell is ohmically connected to a drain (1), the top layer of the MOS cell is ohmically connected to a metal source (5), and a gate (6) is embedded between the base layer of the MOS cell and the metal source (5).

2. The high reliability SiC VDMOSFET structure according to claim 1, characterized in that: The heavily doped P well one (14) and the lightly doped P well two (16) between adjacent MOS cells are integrated into one, and the heavily doped P well two (15) is located between the heavily doped P well one (14) and the lightly doped P well two (16).

3. The high reliability SiC VDMOSFET structure according to claim 1, characterized in that: The heavily doped P well 1 (14), the heavily doped P well 2 (15) and the lightly doped P well 2 (16) are arranged in a left-right lateral distribution.

4. The high reliability SiC VDMOSFET structure according to claim 1, characterized in that: The lightly doped P-well three (13), the lightly doped P-well four (17) and the lightly doped P-well five (18) all have weak charge conductivity, and the lightly doped P-well three (13), the lightly doped P-well four (17) and the lightly doped P-well five (18) are arranged in an up-and-down longitudinal arrangement.

5. The high reliability SiC VDMOSFET structure according to claim 1, characterized in that: When the gate (6) is connected to a gate voltage, a charge channel (19) is formed inside the lightly doped P well (12) near the gate (6).

6. The high reliability SiC VDMOSFET structure according to claim 5, characterized in that: The top of the heavily doped P well 2 (15) protrudes upward and is embedded in the heavily doped N well layer (10), wherein the heavily doped N well layer (10) is in an 'L' shape.

7. The high reliability SiC VDMOSFET structure according to claim 6, characterized in that: The lightly doped N well layer 1 (8), the lightly doped N well layer 2 (9) and the heavily doped N well layer (10) are arranged and distributed in a left-right lateral manner.

8. The high reliability SiC VDMOSFET structure according to any one of claims 1 to 7, characterized in that: The doping layer (3), the diffusion layer (4), the lightly doped N well layer 1 (8) and the lightly doped N well layer 2 (9) are doped with low concentration phosphorus ions by ion implantation; The lightly doped P-well three (13), the lightly doped P-well five (18) and the lightly doped P-well four (17) are doped with low concentrations of boron ions by ion implantation; the heavily doped P-well one (14) and the heavily doped P-well two (15) are doped with high concentrations of boron ions by ion implantation.

9. The high reliability SiC VDMOSFET structure according to claim 1, characterized in that: An oxide layer (20) is deposited between the gate (6) and the base layer of the MOS cell.

10. The high reliability SiC VDMOSFET structure according to claim 1, characterized in that: When a voltage is applied to the gate (6), a depletion layer of a JFET region (21) is formed inside the diffusion layer (4), and the JFET region (21) in a single MOS cell is formed between two lightly doped P wells (17).

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