1553B data conversion circuit based on SDIO bus

Abstract

The utility model discloses a 1553B data conversion circuit based on an SDIO bus, comprising a main control unit and an interface unit, the main control unit is composed of a CPU chip, the interface unit comprises an FPGA chip, a 1Mbps 1553B transmit-receive module and a 4Mbps 1553B transmit-receive module, and the FPGA chip is respectively connected with the CPU chip, the 1Mbps 1553B transmit-receive module and the 4Mbps 1553B transmit-receive module. According to the utility model, data at two transmission rates of 1Mbps and 4Mbps can be processed and converted, a 1553B data interaction function of 1Mbps and 4Mbps can be realized, and the 1553B data conversion device is suitable for an avionics system with two data transmission rates of 1Mbps and 4Mbps.

Description

Technical Field

[0001] The utility model belongs to the field of circuit design, and more specifically, it relates to a 1553B data conversion circuit based on the SDIO bus. Background Art

[0002] 1553B data is a communication protocol data used in aircraft electronic systems. It was first developed by the US Department of Defense. Due to its high reliability, high real-time performance, and high security, 1553B data is widely used in the electronic systems of fighter jets, civilian aircraft, and other transportation vehicles. The traditional 1553B data transmission rate is 1 Mbps. As the amount of interaction information between terminals in avionics systems is increasing day by day, the 1 Mbps data transmission rate cannot meet the needs of some high-speed data applications. With the development of science and technology, a 4 Mbps data transmission rate has gradually been widely used. Data with different transmission rates cannot communicate directly due to inconsistent clocks, which greatly affects data interaction between different devices. Therefore, how to convert and interact data with transmission rates of 1 Mbps and 4 Mbps is an urgent problem we need to solve at present. Summary of the Utility Model

[0003] The purpose of the utility model is to overcome the deficiencies in the prior art and provide a 1553B data conversion circuit based on the SDIO bus, which can process and convert data with transmission rates of 1 Mbps and 4 Mbps, and can realize the 1553B data interaction function of 1 Mbps and 4 Mbps.

[0004] The purpose of the utility model is achieved through the following technical solutions.

[0005] The 1553B data conversion circuit based on the SDIO bus of the utility model includes a main control unit and an interface unit. The main control unit is composed of a CPU chip. The interface unit includes an FPGA chip, a 1553B transceiver module with a rate of 1 Mbps, and a 1553B transceiver module with a rate of 4 Mbps. The FPGA chip is respectively connected to the CPU chip, the 1553B transceiver module with a rate of 1 Mbps, and the 1553B transceiver module with a rate of 4 Mbps.

[0006] Further, the CPU chip is connected to the FPGA chip through an SDIO bus interface and a GPIO interface.

[0007] Further, both the 1553B transceiver module with a rate of 1 Mbps and the 1553B transceiver module with a rate of 4 Mbps are connected to the FPGA chip through data sending pins, data receiving pins, data sending enable pins, and data receiving enable pins.

[0008] Further, the 1 Mbps 1553B transceiver module and the 4 Mbps 1553B transceiver module are connected to the same block of the FPGA chip, and are connected to the CPU chip in different blocks of the FPGA chip.

[0009] Further, the model of the CPU chip is M300, the model of the FPGA chip is JFMK50, the model of the 1 Mbps 1553B transceiver module is MD001ECCAT, and the model of the 4 Mbps 1553B transceiver module is MD004ECCAT.

[0010] Compared with the prior art, the beneficial effects brought by the technical solution of the present utility model are as follows:

[0011] (1) The 1553B data conversion circuit based on the SDIO bus designed by the present utility model can achieve data communication between devices with two transmission rates of 1 Mbps and 4 Mbps, providing greater flexibility and compatibility for data interaction in avionics systems.

[0012] (2) All the devices selected by the present utility model are low-power devices, with the characteristics of high performance, high integration, and high reliability. They can automatically convert 1553B data with two transmission rates of 1 Mbps and 4 Mbps, are applicable to complex avionics systems, and are convenient for operators to use.

[0013] (3) The 1553B data conversion circuit based on the SDIO bus designed by the present utility model can be used as an independent functional module in the original avionics system. Compared with redesigning an avionics system that can be compatible with multiple 1553B data transmission rates, it has the advantages of being economical, efficient, easy to maintain, and expandable. Description of the Drawings

[0014] Figure 1 is the principle block diagram of the 1553B data conversion circuit based on the SDIO bus of the present utility model.

[0015] Figure 2 is the schematic circuit diagram of the main control unit in the present utility model.

[0016] Figure 3 is the schematic circuit diagram of the interface unit in the present utility model. Detailed Embodiments

[0017] The present utility model will be further described below with reference to the drawings.

[0018] As Figure 1As shown, the utility model is based on the 1553B data conversion circuit of SDIO bus, including a main control unit and an interface unit, the main control unit includes a CPU chip, the interface unit includes an FPGA chip, a 1Mbps 1553B transceiver module, and a 4Mbps 1553B transceiver module, the FPGA chip is respectively connected to the CPU chip, the 1Mbps 1553B transceiver module, and the 4Mbps 1553B transceiver module.

[0019] The CPU chip is used to process and convert 1Mbps and 4Mbps 1553B data, and send or receive 1Mbps or 4Mbps 1553B data to the FPGA chip through a set of SDIO bus interfaces and 4 GPIO interfaces of the CPU. The FPGA chip is used to connect the CPU and the 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module, mainly to realize the reception and transmission of 1Mbps and 4Mbps 1553B data. The 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module are used to send or receive 1Mbps or 4Mbps 1553B data to an external avionics system.

[0020] Specifically, the CPU chip is connected to the FPGA chip through a set of SDIO bus interfaces and 4 GPIO interfaces. The 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module are connected to the FPGA chip through the data transmission pin TX, the data reception pin RX, the data transmission enable pin TXINH, and the data reception enable pin RXEN. The 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module are connected to the same block (BANK) of the FPGA chip, and are connected to the CPU chip in different blocks of the FPGA chip. The CPU chip, the 1Mbps 1553B transceiver module, and the 4Mbps 1553B transceiver module are all connected to avoid BANK0 and BANK1 of the FPGA chip.

[0021] (1) Main control unit

[0022] The CPU chip of the main control unit is a high-performance heterogeneous processor of the M300 model. The M300 is a domestically produced microcontroller with low power consumption, excellent computing power, and real-time control. The M300 adopts a unique three-core structure. The main core adopts a high-performance, real-time control core, and the other two cores adopt XBurst2 and XBurst0 structures. The M300 has a rich built-in peripheral interface and can support a variety of data communication modes.

[0023] The main control unit circuit diagram is as follows Figure 2As shown in FIG. 1 , the circuit can realize the transmission and reception of 1553B data at two transmission rates of 1Mbps and 4Mbps between the CPU chip and the FPGA chip. Specifically, the CPU chip (such as Figure 2 The clock pin SDIO_CLK in the SDIO bus of U1D) is connected to the block BANK allocated by the FPGA chip (such as Figure 2 Connect any one of the U2_11P_G1_SRC, U2_12P_G1_MRC, U2_13P_G2_MRC or U2_14P_G2_SRC pins of U2C in the FPGA chip, and connect the control pin SDIO_CMD, the four data pins SDIO_D0 to SDIO_D3, and the four GPIO interfaces GPIO_0 to GPIO_3 to the block BANK allocated by the FPGA chip (such as Figure 2 In U2C), except for U2_11P_G1_SRC, U2_12P_G1_MRC, U2_13P_G2_MRC and U2_14P_G2_SRC, the power pins U2_VCCP_0~U2_VCCP_5 of this bank are all connected to 1.8V power supply.

[0024] The CPU chip uses a set of SDIO bus interfaces and four GPIO interfaces as interfaces for communicating with the FPGA chip, where the operating voltage of the SDIO bus interface and the GPIO interface is 1.8 V. The CPU chip and the FPGA chip control the data transmission and reception status on the SDIO bus through GPIO_0 to GPIO_3, including the data transmission and reception enable status and the data transmission and reception completion status; and send and receive 1553B data to the FPGA chip through SDIO_D0 to SDIO_D3 of the SDIO bus.

[0025] (2) FPGA chip

[0026] The FPGA chip selected is the FPGA model JFMK50. JFMK50 is a low-power, small-size, high-performance FPGA that integrates powerful and flexibly configured programmable resources to implement multiple functions such as input and output interfaces, general digital logic, and clock management.

[0027] The interface processing chip JFMK50 communicates data with the CPU through the SDIO bus and GPIO, and the operating voltage of this circuit is 1.8V; it communicates data with two 1553B transceiver modules through the data transceiver pins TX and RX and the data transceiver enable pins TXINH and RXEN, and the operating voltage of this circuit is 3.3V.

[0028] (3) 1553B transceiver module

[0029] The model of the 1Mbps 1553B transceiver module is MD001ECCAT, and the model of the 4Mbps 1553B transceiver module is MD004ECCAT. The 1553B transceiver module is an integrated package, which integrates a 1553B bus transceiver chip and a bus isolation transformer, and has the advantages of small size, high efficiency and low power consumption.

[0030] The 1553B transceiver module adopts an A and B dual-channel multiplexing structure. The two channels have the same functions and isolation technology is used between the channels to prevent them from interfering with each other. This can effectively ensure the success rate and redundancy rate of data transmission in the 1553B communication system.

[0031] The circuit diagram of the interface unit is as follows: Figure 3 As shown, the operating voltage of the 1553B transceiver module is 3.3V. The FPGA chip realizes data communication with the two 1553B transceiver modules through the data transmission pin TX and the data reception pin RX, and changes the working status of the two 1553B transceiver modules by controlling the high and low levels of the data transmission enable pin TXINH and the data reception enable pin RXEN.

[0032] Specifically, the 1Mbps 1553B transceiver module (see Figure 3 In U3), the A-channel data transmission pin TXA (1M_TX_A_P and 1M_TX_A_N are respectively the positive signal and negative signal of the 1M differential signal data sent by the A-channel), the B-channel data transmission pin TXB (1M_TX_B_P and 1M_TX_B_N are respectively the positive signal and negative signal of the 1M differential signal data sent by the B-channel), the A-channel data receiving pin RXA (1M_RX_A_P and 1M_RX_A_N are respectively the positive signal and negative signal of the 1M differential signal data received by the A-channel), the B-channel data receiving pin RXB (1M_RX_B_P and 1M_RX_B_N are respectively the positive signal and negative signal of the 1M differential signal data received by the B-channel), the A-channel data transmission enable pin TXINHA, the B-channel data transmission enable pin TXINHB, the A-channel data reception enable pin RXENA, and the B-channel data reception enable pin RXENB are respectively connected to the block BANK allocated by the FPGA chip (such as Figure 2 U2E) of different independent I / O pins (such as Figure 3U4_3P_G0_DQS, U4_3N_G0_DQS, U4_4P_G0, U4_4N_G0, U4_5P_G0, U4_5N_G0, U4_6P_G0, U4_6N_G0_VREF, U4_8P_G1, U4_8N_G1, U4_9N_G1_DQS, U4_10P_G1) of U2E, the power pins U4_VCCP_0~U4_VCCP_5 of this bank are all connected to 3.3V power supply. The A-channel data transmission enable pin TXINHA, the B-channel data transmission enable pin TXINHB, the A-channel data reception enable pin RXENA, and the B-channel data reception enable pin RXENB are grounded to GND through resistors R1, R2, R3, and R4 respectively. 1Mbps 1553B transceiver module (see Figure 3 In U3), the A-way power line pin VDDA and the B-way power line pin VDDB are both connected to a 3.3V power supply, the A-way ground line pin GNDA and the B-way ground line pin GNDB are both connected to ground GND, and the A-way output bus pin BUSA and the B-way output bus pin BUSB are used to connect to an external avionics system.

[0033] Similarly, the 4Mbps 1553B transceiver module (see Figure 3 In U4), the A-channel data transmission pin TXA (4M_TX_A_P and 4M_TX_A_N are respectively the positive signal and negative signal of the 4M differential signal data sent by the A-channel), the B-channel data transmission pin TXB (4M_TX_B_P and 4M_TX_B_N are respectively the positive signal and negative signal of the 4M differential signal data sent by the B-channel), the A-channel data receiving pin RXA (4M_RX_A_P and 4M_RX_A_N are respectively the positive signal and negative signal of the 4M differential signal data received by the A-channel), the B-channel data receiving pin RXB (4M_RX_B_P and 4M_RX_B_N are respectively the positive signal and negative signal of the 4M differential signal data received by the B-channel), the A-channel data transmission enable pin TXINHA, the B-channel data transmission enable pin TXINHB, the A-channel data reception enable pin RXENA, and the B-channel data reception enable pin RXENB are respectively connected to the block BANK allocated by the FPGA chip (such as Figure 2 U2E) of different independent I / O pins (such as Figure 3The A-channel data transmission enable pin TXINHA, the B-channel data transmission enable pin TXINHB, the A-channel data reception enable pin RXENA, and the B-channel data reception enable pin RXENB are connected to the ground GND through resistors R5, R6, R7, and R8 respectively. 4Mbps 1553B transceiver module (see Figure 3 In U4), the A-way power line pin VDDA and the B-way power line pin VDDB are both connected to a 3.3V power supply, the A-way ground line pin GNDA and the B-way ground line pin GNDB are both connected to ground GND, and the A-way output bus pin BUSA and the B-way output bus pin BUSB are used to connect to an external avionics system.

[0034] The specific implementation process of the 1553B data conversion circuit based on the SDIO bus of the utility model is as follows:

[0035] After power-on, the default working state of the 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module is to send signals, and reception is prohibited.

[0036] ①Convert 1553B data at 1Mbps to 1553B data at 4Mbps

[0037] When the 1Mbps 1553B transceiver module receives the 1Mbps 1553B data with a transmission rate of 1Mbps input from the external avionics system, it sends the data to the FPGA chip through the data transmission pin TX (including TXA and TXB of U3) of the 1Mbps 1553B transceiver module.

[0038] After receiving the 1553B data sent by the 1Mbps 1553B transceiver module, the FPGA chip controls the data transmission enable pin TXINH (including TXINHA and TXINHB of U4) and the data reception enable pin RXEN (including RXENA and RXENB of U4) of the 4Mbps 1553B transceiver module to high level, thereby changing the working state of the 4Mbps 1553B transceiver module to the receiving signal and prohibiting transmission.

[0039] At the same time, the FPGA chip sends the 1553B data with a transmission rate of 1Mbps received from the 1553B transceiver module through the SDIO bus and GPIO to the CPU chip for data processing and conversion. The CPU chip analyzes, processes, and converts the 1553B data with a transmission rate of 1Mbps, converts it into 1553B data with a transmission rate of 4Mbps, and then sends it to the FPGA chip through the SDIO bus and GPIO.

[0040] After receiving the processed 1553B data with a transmission rate of 4Mbps sent by the CPU chip, the FPGA chip sends the processed and converted data to the 4Mbps 1553B transceiver module whose working state is receiving signal and prohibiting sending through the data receiving pin RX of the 4Mbps 1553B transceiver module (including RXA and RXB of U4), and sends the 1553B data with a transmission rate of 4Mbps to the external aerospace electronic system through the 4Mbps 1553B transceiver module.

[0041] ②Convert 1553B data at 4Mbps to 1553B data at 1Mbps

[0042] After the 4Mbps 1553B transceiver module receives the 1553B data with a transmission rate of 4Mbps input from the external avionics system, it sends the data to the FPGA chip through the data transmission pin TX (including TXA and TXB of U4) of the 4Mbps 1553B transceiver module.

[0043] After receiving the 1553B data sent by the 4Mbps 1553B transceiver module, the FPGA chip controls the data transmission enable pin TXINH (including TXINHA and TXINHB of U3) and the data reception enable pin RXEN (including RXENA and RXENB of U3) of the 1Mbps 1553B transceiver module to high level, thereby changing the working state of the 1Mbps 1553B transceiver module to the receiving signal and prohibiting transmission.

[0044] At the same time, the FPGA chip sends the 1553B data with a transmission rate of 4Mbps received from the 1553B transceiver module at 4Mbps to the CPU chip through the SDIO bus and GPIO for data processing and conversion. The CPU chip analyzes, processes, and converts the 1553B data with a transmission rate of 4Mbps, converts it into 1553B data with a transmission rate of 1Mbps, and then sends it to the FPGA chip through the SDIO bus and GPIO.

[0045] After receiving the processed 1553B data with a transmission rate of 1Mbps sent by the CPU chip, the FPGA chip sends the processed and converted data to the 1Mbps 1553B transceiver module whose working state is receiving signal and prohibiting sending through the data receiving pin RX of the 1Mbps 1553B transceiver module (including RXA and RXB of U3), and sends the 1553B data with a transmission rate of 1Mbps to the external aerospace electronic system through the 1Mbps 1553B transceiver module.

[0046] Although the functions and working processes of the utility model have been described above in conjunction with the accompanying drawings, the utility model is not limited to the above-mentioned specific functions and working processes, and the above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the inspiration of the utility model, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the utility model and the claims, which all fall within the protection of the utility model.

Claims

1. A 1553B data conversion circuit based on SDIO bus, characterized in that: It includes a main control unit and an interface unit. The main control unit is composed of a CPU chip. The interface unit includes an FPGA chip, a 1Mbps 1553B transceiver module, and a 4Mbps 1553B transceiver module. The FPGA chip is connected to the CPU chip, the 1Mbps 1553B transceiver module, and the 4Mbps 1553B transceiver module respectively.

2. The 1553B data conversion circuit based on the SDIO bus according to claim 1, characterized in that: The CPU chip is connected to the FPGA chip via the SDIO bus interface and the GPIO interface.

3. The 1553B data conversion circuit based on the SDIO bus according to claim 1, characterized in that: The 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module are both connected to the FPGA chip via a data transmission pin, a data reception pin, a data transmission enable pin, and a data reception enable pin.

4. The 1553B data conversion circuit based on the SDIO bus according to claim 1, characterized in that: The 1Mbps 1553B transceiver module and the 4Mbps 1553B transceiver module are connected to the same block of the FPGA chip, and are connected to the CPU chip in different blocks of the FPGA chip.

5. The 1553B data conversion circuit based on the SDIO bus according to claim 1, characterized in that: The model of the CPU chip is M300, the model of the FPGA chip is JFMK50, the model of the 1Mbps 1553B transceiver module is MD001ECCAT, and the model of the 4Mbps 1553B transceiver module is MD004ECCAT.

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