Zynq-based multipurpose 3U core module

By designing a multi-purpose 3U core module based on zynq, using a universal gold finger connector and network interface, the problem that the existing 3U PXIe module cannot be seamlessly switched to other modes is solved, and the versatility and flexibility of the module is realized, reducing costs and improving reusability.

CN222914197UActive Publication Date: 2025-05-27成都玖锦科技有限公司
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Patent Information

Application Number
CN202322838407.9
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2023-10-23
Publication Date
2025-05-27
Estimated Expiration
2033-10-23

AI Technical Summary

Technical Problem

After the design of the existing 3U PXIe module can only be inserted into the PXIe chassis for use, and cannot be seamlessly switched to other modes for use, which limits the reusability of the module, resulting in poor reusability of the product in the test and measurement industry and is difficult to reduce costs.

Method used

A multi-purpose 3U core module based on zynq is designed, using a universal gold finger connector, which is connected to the gold finger through the Ethernet port and USB port of the zynq PS end, realizing flexible switching of the module in different modes, and supports use as a PXIe peripheral module or independent functional module.

Benefits of technology

It realizes the versatility and flexibility of the module, can seamlessly switch in different scenarios, reduces product costs, and improves the reusability and applicability of the module.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a multipurpose 3U core module based on zynq, which is characterized in that under the condition that the module conforms to the size specification of a 3U PXIe standard module, a universal golden finger connector is designed, and the golden finger connector is positioned on the same side of a backplane connector of the 3U PXIe module and does not exceed the PCB (Printed Circuit Board) range limited by the size specification of the 3U module. A multifunctional module which can be used as a 3U PXIe peripheral module and can also be used as an independent equipment core module is designed, and the multifunctional module is designed based on zynq, is provided with a standard 3U PXIe peripheral module for use, and also has the capability of independently working only after being externally connected with a power supply.
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Description

Technical Field

[0001] The utility model relates to a 3U PXIe module in the field of testing, and particularly to a multi-purpose 3U core module based on zynq. Background Art

[0002] The 3U PXIe module is a commonly used module specification in the test and measurement industry and is an important part of software-defined instruments. It is widely used and has strong compatibility. The utility model relates to a 3U PXIe core module based on zynq, which can be used as a PXIe peripheral module of a software-defined instrument and can also be used as a core component of a handheld instrument to complete test functions.

[0003] However, after the PXIe module is designed, it can usually only be inserted into a PXIe chassis for use and cannot be seamlessly switched to other modes, which limits the reusability of the module. In the test and measurement industry, it is usually difficult to form large-scale production for a single product, and the cost is difficult to reduce. Therefore, product reuse is an effective means to reduce product costs. Summary of the Utility Model

[0004] The utility model provides a multi-purpose 3U core module based on zynq to solve the defects of the prior art mentioned above.

[0005] Under the size specification of a 3U PXIe standard module, a general-purpose gold finger connector is designed. The position of the gold finger connector is on the same side as the backplane connector of the 3U PXIe module and does not exceed the PCB range defined by the 3U module size specification.

[0006] The Ethernet port of the zynq PS end is connected to the PCIe communication port of the PXIe peripheral socket XP3 through a PCIe to tcp / ip chip. When used as a PXIe peripheral module, this module communicates with the main controller through the TCP / IP protocol; at the same time, the Ethernet port of the zynq PS end is connected to the gold finger after being converted by a LAN PHY chip. When used as an independent functional module, this module can communicate with other external devices through the gold finger through the TCP / IP protocol;

[0007] The USB port of the zynq PS end is connected to a USB HUB chip and then connected to the gold finger through the USB HUB. When used as an independent functional module, this module can be connected to an external USB device through the gold finger;

[0008] Some I / O of the zynq PL end is connected to the gold finger and configured as UART, I2C, LVDS or RGB interfaces. When used as an independent functional module, this module can be connected to a UART and an I2C human engineering input device through the gold finger, and can be connected to a display device with an LVDS or RGB interface through the gold finger.

[0009] The beneficial effects of this application are as follows:

[0010] In view of the above problems, the utility model patent designs a multifunctional module that can be used as a 3U PXIe peripheral module and also as the core module of an independent device. The multi-purpose module is designed based on zynq, has the use of a standard 3U PXIe peripheral module, and also has the ability to work independently after only an external power supply is connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments and, together with the description, are used to explain the principles of the utility model. Other embodiments and many of the intended advantages of the embodiments will be readily apparent as they become better understood by reference to the following detailed description. The other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments read in conjunction with the accompanying drawings:

[0012] Figure 1 is the module design diagram of the utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The following further describes the present application in detail with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the relevant utility model and not for limiting the utility model. Additionally, it should be noted that for the sake of description, only the parts related to the relevant utility model are shown in the drawings.

[0014] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The following will describe the present application in detail with reference to the drawings and embodiments.

[0015] A multi-purpose 3U core module based on zynq according to an embodiment of the present utility model, as Figure 1 shown, the multi-purpose module adopts a design that conforms to the standard 3U PXIe, is designed based on zynq. Under the size specification of the 3U PXIe standard module, a general-purpose gold finger connector is designed at position ⑤ in the figure. The position of the gold finger connector is on the same side as the backplane connector of the 3U PXIe module and does not exceed the PCB range defined by the 3U module size specification.

[0016] The 3U PXIe module is based on the PXI Express bus specification and is equipped with an NVIDIA high-performance GPU, and is used to build a high-performance heterogeneous computing system based on the PXIe platform to meet the requirements of applications such as radar / communication / countermeasure, high-speed signal processing, high-performance computing, artificial intelligence processing, and visual simulation.

[0017] This 3U PXIe module provides a variety of different performance and power consumption options, adding parallel computing capabilities to the PXIe system, and can well support NI's latest PXIe Gen3×8 chassis, and is backward compatible with previous generation products. Taking advantage of the high throughput of the latest 3UPXIe bus, the 3UPXIe module can transmit and process up to 6GB / s of real-time data per second, eliminating the need to configure GPU computing servers and data transmission equipment, greatly simplifying the system architecture and reducing system costs. With a portable PXIe reinforced chassis, you can easily build a portable high-performance test and simulation system for the field.

[0018] The Ethernet port on the zynq PS side is transferred to the PCIe communication port of the PXIe peripheral socket XP3 through the PCIe to TCP / IP chip ①. When used as a PXIe peripheral module, this module communicates with the main controller through the TCP / IP protocol; at the same time, the Ethernet port on the zynq PS side is converted through the LAN PHY chip ② and connected to the gold finger ⑤. When used as an independent functional module, this module can communicate with other external devices through the gold finger ⑤ through the TCP / IP protocol;

[0019] The USB port on the zynq PS end is connected to the USB HUB chip③, and connected to the gold finger⑤ through the USB HUB. When used as an independent functional module, this module can connect to external USB devices through the gold finger;

[0020] Some IOs on the zynq PL side are connected to the gold finger ⑤ and configured as UART, I2C, LVDS or RGB interface ④. When used as an independent functional module, this module can be connected to UART, I2C ergonomic input devices through the gold finger, and connected to LVDS or RGB interface display devices through the gold finger.

[0021] Data cannot be held up at one end during transmission, and can be sent immediately, whether it is 1 byte or 1K bytes;

[0022] The zynq PL side interface is a FIFO interface;

[0023] Data transmission process from zynq PS to zynq PL:

[0024] The data transmission from zynq PS to zynq PL is relatively simple and can be completed using axi_datamover provided by vivado. The details include:

[0025] Query the remaining data storage length (in bytes) from the zynq PL end;

[0026] Set the zynq PL end DMA data transfer start address by writing registers;

[0027] Set the DMA data transfer length (in bytes) at the Zynq PL side by writing to the register.

[0028] Start the DMA transfer at the Zynq PL side by writing to the register.

[0029] Query whether the DMA at the Zynq PL side has completed data transfer by reading the register.

[0030] Data transfer process from Zynq PL to Zynq PS:

[0031] The data transfer from Zynq PL to Zynq PS is relatively more complex. It is found that the built-in axi_datamover test in Vivado is sometimes not normal. Therefore, a module is rewritten according to the interface protocol of the built-in axi_datamover in Vivado, specifically including:

[0032] Query the length of the data to be transferred (in bytes) by reading the register.

[0033] Set the start address of the DMA data transfer at the Zynq PL side by writing to the register.

[0034] Set the data transfer length (in bytes) by writing to the register.

[0035] Start the data transfer by writing to the register.

[0036] Query whether the DMA at the Zynq PL side has completed data transfer by reading the register.

[0037] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "set", "install", "connect", "connection", "fix" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood through specific situations.

[0038] Although the embodiments of the present utility model have been shown and described, for those of ordinary skill in the art, it can be understood that various equivalent changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and spirit of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalent scope.

Claims

1. A multi-purpose 3U core module based on Zynq, It is characterized in that The module is designed with a gold finger connector in accordance with the size specification of the 3U PXIe standard module. The gold finger connector is located on the same side as the 3U PXIe module backplane connector and does not exceed the PCB range specified by the 3U module size specification. The Ethernet port on the zynq PS side is connected to the gold finger connector after conversion by the LAN PHY chip. When used as an independent functional module, this module can communicate with other external devices through the gold finger connector via the TCP / IP protocol; The USB port on the zynq PS side is connected to the USB HUB chip, and then connected to the gold finger connector through the USB HUB. When used as an independent functional module, this module can connect to external USB devices through the gold finger connector; Some IOs on the zynq PL side are connected to the gold finger connector and configured as UART, I2C, LVDS or RGB interfaces. When used as an independent functional module, this module can be connected to UART, I2C ergonomic input devices through the gold finger connector, and to display devices with LVDS or RGB interfaces through the gold finger connector.

2. A multi-purpose 3U core module based on zynq according to claim 1, It is characterized in that The Ethernet port on the zynq PS side is transferred to the PCIe communication port of the PXIe peripheral socket XP3 through a PCIe to TCP / IP chip. When used as a PXIe peripheral module, this module communicates with the main controller through the TCP / IP protocol.