Packaging structure

Abstract

The utility model provides a packaging structure. The packaging structure comprises a first chip; the second chip is arranged above the first chip, and the second chip is a back power supply chip; the third chip is arranged above the second chip; the bending part comprises a first part arranged between the first chip and the second chip; wherein the bending part forms a heat dissipation path of the packaging structure. The stacked packaging structure has the advantages that the heat dissipation capability of the stacked packaging structure is improved, and the interference of heat concentration caused by insufficient heat dissipation on signals in the packaging structure is reduced; and the signal line and the power supply line are arranged in mutually isolated channels, so that the interference of the power supply line on signals is avoided.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing, and more particularly, to a packaging structure. Background Art

[0002] With the development of packaging technology and the miniaturization trend of packaging structures, the application of package-on-package (POP) structures has become increasingly widespread. At the same time, in order to achieve better performance, Intel has developed backside power delivery chips, which have significantly improved the chip usage efficiency, with the cell utilization exceeding 90%.

[0003] However, although these technologies have achieved the miniaturization of the packaging structure, they have also reduced the heat dissipation area of the packaging structure, resulting in insufficient heat dissipation. Among them, the backside power delivery chips are usually located in the middle of the stacked structure, which makes the heat concentrate between the back of the backside power delivery chip and the underlying chip and difficult to dissipate. This heat concentration can interfere with the signals in the packaging structure and affect the product performance. In addition, the existing package-on-package structures also have problems such as signal lines and power supply lines crossing each other, and the power supply lines interfering with the signals.

[0004] Figure 1 The schematic diagram of the first prior art packaging structure is shown. As Figure 1 shown, the solid line with an arrow represents the transmission direction of the supply current along the power supply circuit, and the dashed line with an arrow represents the transmission direction of the signal along the signal circuit. The first prior art packaging structure includes an electronic component 101, a first chip 102, a second chip 103, and a molding layer 104. The electronic component 101 is disposed above the first chip 102, the first chip 102 is disposed above the second chip 103, and the molding layer 104 covers the second chip 103. It can be seen that the paths of the supply current and the signal transmission intersect, so the supply current will interfere with the signal.

[0005] Figure 2 The schematic diagram of the second prior art packaging structure is shown. As Figure 2As shown, the solid line with an arrow represents the transmission direction of the power supply current along the power supply circuit, and the dashed line with an arrow represents the transmission direction of the signal along the signal circuit. The second prior art package structure includes a first chip 201, a second chip 202, a third chip 203, a first dielectric layer 204, and a second dielectric layer 205. The third chip 203 is disposed on the second dielectric layer 205, and the first dielectric layer 204 covers the third chip 203. The first chip 201 and the second chip 202 are respectively disposed above the first dielectric layer 204. It can be seen that there is an intersection in the paths of the power supply current and the signal transmission. Therefore, the power supply current will interfere with the signal.

[0006] Figure 3 FIG. shows a schematic diagram of a third prior art package structure. As Figure 3 shown, the solid line with an arrow represents the transmission direction of the power supply current along the power supply circuit, and the dashed line with an arrow represents the transmission direction of the signal along the signal circuit. The third prior art package structure includes a first chip 301, a second chip 302, a third chip 303, a substrate 304, and a molding compound layer 305. The third chip 303, the second chip 302, the first chip 301, and the substrate 304 are stacked in sequence from top to bottom, and the molding compound layer 305 covers the third chip 303, the second chip 302, and the first chip 301. It can be seen that there is an intersection in the paths of the power supply current and the signal transmission and there is no heat dissipation structure between the chips. Therefore, the concentration of the power supply current and heat will interfere with the signal.

[0007] In summary, there is a need in the art to provide a package structure that can overcome the defects of the prior art. Summary of the Invention

[0008] The present application provides a package structure that can solve the problems of the prior art. The object of the present application is achieved by the following technical solutions.

[0009] An embodiment of the present application provides a package structure, which includes: a first chip; a second chip disposed above the first chip, and the second chip is a back-side power supply chip; a third chip disposed above the second chip; a bending member, and the bending member includes a first portion disposed between the first chip and the second chip; wherein, the bending member forms a heat dissipation path of the package structure.

[0010] In some optional embodiments, according to the package structure provided by the above embodiment of the present application, the bending member further includes a second portion and a third portion, and the first portion, the second portion, and the third portion are connected in sequence.

[0011] In some optional embodiments, according to the package structure provided by the above embodiment of the present application, the second chip and the third chip are disposed face to face.

[0012] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein the packaging structure further includes a molding layer, the molding layer covers the sides of the first chip, the second chip and the third chip, a second portion is located outside the molding layer, and a separation space is formed between the second portion and the molding layer.

[0013] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein the packaging structure further includes a substrate, the substrate is disposed under the first chip, and in the cross - sectional direction, the width of the molding layer is different from the width of the substrate.

[0014] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein the packaging structure further includes a heat - dissipating component, a third portion is disposed above the third chip, and the heat - dissipating component is disposed above the third portion.

[0015] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein in the cross - sectional direction, the width of the heat - dissipating component is greater than the width of the third chip.

[0016] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein the heat - dissipation path extends from the first portion on the back of the second chip through the second portion to the third portion on the back of the third chip.

[0017] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein a plurality of first through - holes are provided on the first chip, a plurality of second through - holes are provided on the second chip, and each first through - hole is respectively aligned with a second through - hole.

[0018] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein a plurality of third through - holes are provided on the first portion, each first through - hole is respectively connected to a second through - hole through a third through - hole, and each group of mutually - connected first through - holes, second through - holes and third through - holes respectively forms a communication channel.

[0019] In some alternative embodiments, a packaging structure is provided according to the above - mentioned one embodiment of the present application, wherein the packaging structure further includes a power - supply circuit and a signal circuit, and the power - supply circuit and the signal circuit are respectively disposed in different communication channels.

[0020] The advantages of the packaging structure according to the embodiment of the present application are as follows: the heat - dissipation capacity of the stacked packaging structure is improved, and the interference of the heat concentration caused by insufficient heat - dissipation to the signals in the packaging structure is reduced; the signal lines and the power - supply lines are disposed in mutually - isolated channels, avoiding the interference of the power - supply lines to the signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non - limiting embodiments of the present application with reference to the accompanying drawings.

[0022] Figure 1 A schematic diagram showing the packaging structure of a first prior art is shown;

[0023] Figure 2 A schematic diagram showing the packaging structure of a second prior art is shown;

[0024] Figure 3 A schematic diagram showing the packaging structure of a third prior art is shown;

[0025] Figure 4 A side - view schematic diagram of the packaging structure according to an embodiment of the present application is shown;

[0026] Figure 5 is shown as Figure 4 A schematic diagram of the bending member of the packaging structure according to an embodiment of the present application as shown;

[0027] Figure 6 is shown as Figure 4 A top - view schematic diagram of the packaging structure according to an embodiment of the present application as shown;

[0028] Figure 7 is shown as Figure 4 A schematic diagram of the part labeled A in the packaging structure according to an embodiment of the present application as shown;

[0029] Figure 8 A schematic diagram of the manufacturing process of the packaging structure according to an embodiment of the present application is shown.

[0030] Reference numerals and component names: 1 - first chip, 2 - second chip, 3 - third chip, 4 - bending component, 5 - substrate, 6 - encapsulation layer, 7 - heat dissipation component, 8 - separation space, 9 - electrical connection component, 11 - first circuit, 12 - first through hole, 21 - second circuit, 22 - second through hole, 31 - third circuit, 41 - first part, 42 - second part, 43 - third part, 44 - third through hole, 101 - electronic component, 102 - first chip, 103 - second chip, 104 - encapsulation layer, 201 - first chip, 202 - second chip, 203 - third chip, 204 - first dielectric layer, 205 - second dielectric layer, 301 - first chip, 302 - second chip, 303 - third chip, 304 - substrate, 305 - encapsulation layer, 901 - third chip, 902 - second chip, 902a - second through hole, 903 - bending component, 903a - third through hole, 904 - heat dissipation component, 905 - electrical connection component, 906 - encapsulation layer, 907 - first chip, 907a - first through hole, 907b - first circuit, 908 - separation space, 909 - substrate. Detailed implementation manners

[0031] The following describes the detailed implementation manners of the present application in combination with the accompanying drawings and embodiments. Through the content recorded in this specification, those skilled in the art can clearly and completely understand the technical solution of the present application, the technical problems solved, and the technical effects produced. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. In addition, for the convenience of description, only the parts related to the present application are shown in the drawings.

[0032] It should be easily understood that the meanings of "on...", "above...", and "over..." in the present application should be interpreted in the broadest sense, so that "on..." not only means "directly on something", but also means "on something" including intermediate components or layers between the two.

[0033] In addition, for the convenience of description, spatial relative terms such as "under...", "beneath...", "lower part", "above...", "upper part", etc. may be used herein to describe the relationship between one element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptive terms used herein can be interpreted accordingly.

[0034] It should be noted that the structures, ratios, sizes, etc. shown in the accompanying drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation conditions of the present application. Therefore, they do not have substantial technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the efficacy that the present application can produce and the purpose that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present application. At the same time, terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope of implementation of the present application. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope that the present application can implement.

[0035] As used herein, the term "layer" refers to a portion of a material that includes a region having a certain thickness. The layer can extend over the entire underlying or overlying structure, or can have an extent less than the extent of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers and can have the same or different materials.

[0036] As used herein, the term "electrical connector" can be a pad or a bump. Among them, the bump can be, for example, a gold bump (usually rectangular, gold), a solder bump (usually circular, copper plus tin), or a pillar bump (usually columnar octagonal or polygonal, copper plus tin or lead plus tin).

[0037] In addition, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0038] Figure 4 A side view schematic diagram of a packaging structure according to an embodiment of the present application is shown. Figure 5 As shown in Figure 4 A schematic diagram of a bending member of a packaging structure according to an embodiment of the present application is shown. Figure 6 As shown in Figure 4 A top view schematic diagram of a packaging structure according to an embodiment of the present application is shown.Figure 7 shows the part labeled A in the encapsulation structure according to an embodiment of the present application as Figure 4 shown in the schematic diagram. As Figures 4 to 7 shown, the encapsulation structure includes: a first chip 1; a second chip 2 disposed above the first chip 1, and the second chip 2 is a back-powered chip; a third chip 3 disposed above the second chip 2; a bending member 4, and the bending member 4 includes a first portion 41 disposed between the first chip 1 and the second chip 2; wherein, the bending member 4 forms a heat dissipation path of the encapsulation structure, and the heat dissipation path is used to guide the heat accumulated between the first chip 1 and the second chip 2 to the outside of the encapsulation structure.

[0039] In some alternative embodiments, for the encapsulation structure provided according to the above-mentioned one embodiment of the present application, the bending member 4 is made of a bendable material with good thermal conductivity, including but not limited to polyimide film (PI film, Polyimide Film), liquid crystal polymer (LCP, Liquid Crystal Polymer).

[0040] In some alternative embodiments, for the encapsulation structure provided according to the above-mentioned one embodiment of the present application, the bending member 4 further includes a second portion 42 and a third portion 43, and the first portion 41, the second portion 42 and the third portion 43 are connected in sequence, that is, both ends of the second portion 42 are respectively connected to the third portion 43 of the first portion 41.

[0041] In some alternative embodiments, for the encapsulation structure provided according to the above-mentioned one embodiment of the present application, the second chip 2 and the third chip 3 are disposed face to face.

[0042] In some alternative embodiments, for the encapsulation structure provided according to the above-mentioned one embodiment of the present application, the encapsulation structure further includes a molding compound layer 6, and the molding compound layer 6 covers the sides of the first chip 1, the second chip 2 and the third chip 3, and the second portion 42 is located outside the molding compound layer 6, and a separation space 8 is formed between the second portion 42 and the molding compound layer 6.

[0043] In some alternative embodiments, for the encapsulation structure provided according to the above-mentioned one embodiment of the present application, the encapsulation structure further includes a substrate 5, and the substrate 5 is disposed below the first chip 1. In the cross-sectional direction, the width of the molding compound layer 6 is different from the width of the substrate 5.

[0044] In some alternative embodiments, for the encapsulation structure provided according to the above-mentioned one embodiment of the present application, the encapsulation structure further includes a heat dissipation component 7, the third portion 43 is disposed above the third chip 3, and the heat dissipation component 7 is disposed above the third portion 43.

[0045] In some alternative embodiments, there is provided a packaging structure according to the above-described one embodiment of the present application, wherein in the cross-sectional direction, the width of the heat dissipation component 7 is greater than the width of the third chip 3.

[0046] In some alternative embodiments, there is provided a packaging structure according to the above-described one embodiment of the present application, wherein the heat dissipation path extends from a first portion 41 between the back surfaces of the first chip 1 and the second chip 2 to a third portion 43 on the back surface of the third chip 3 via a second portion 42, and the first portion 41 is in contact with both the back surface of the first chip 1 and the back surface of the second chip 2 simultaneously. After the heat dissipated by the first chip 1 and the second chip 2 is absorbed by the first portion 41, it can be conducted along the heat dissipation path through the second portion 42 to the third portion 43, and then the heat is dissipated to the outside of the packaging structure from the third portion 43, thereby avoiding heat concentration between the first chip 1 and the second chip 2, and further avoiding interference with the electrical signals between the chips caused by heat concentration.

[0047] In some alternative embodiments, there is provided a packaging structure according to the above-described one embodiment of the present application, wherein a plurality of first through-holes 12 are provided on the first chip 1, and a plurality of second through-holes 22 are provided on the second chip 2, and each first through-hole 12 is aligned with a corresponding second through-hole 22 respectively.

[0048] In some alternative embodiments, there is provided a packaging structure according to the above-described one embodiment of the present application, wherein a plurality of third through-holes 44 are provided on the first portion 41, and each first through-hole 12 is connected to a second through-hole 22 through a corresponding third through-hole 44, and each set of mutually connected first through-holes 12, second through-holes 22, and third through-holes 44 forms a communication channel respectively.

[0049] In some alternative embodiments, there is provided a packaging structure according to the above-described one embodiment of the present application, wherein the packaging structure further includes a power supply circuit and a signal circuit, and the power supply circuit and the signal circuit are respectively arranged in different communication channels. Each power supply circuit is electrically connected to any two or more of the first chip 1, the second chip 2, the third chip 3, and the substrate 5, and each signal circuit is electrically connected to any two or more of the first chip 1, the second chip 2, the third chip 3, and the substrate 5. In one embodiment, the power supply circuit and the signal circuit are respectively made of a conductive material and are adhesively disposed on the inner side of the communication channel; the power supply circuit and the signal circuit can adopt other conductive structures commonly used in packaging structures, including but not limited to conductive posts, conductive wires, etc.

[0050] In some alternative embodiments, there is provided a packaging structure according to the above-described one embodiment of the present application, as Figure 4 shown Figure 4The solid line with an arrow therein exemplarily represents the transmission direction of the power supply current along the power supply circuit, and the dashed line with an arrow exemplarily represents the transmission direction of the signal along the signal circuit. It can be seen that the power supply current and the signal are respectively transmitted between the chips of the stacked structure through different communication channels, thereby avoiding the interference of the power supply current on the signal.

[0051] In some alternative embodiments, according to the packaging structure provided by the above-mentioned one embodiment of the present application, wherein the first chip 1 includes a plurality of first circuits 11 and a plurality of electrical connectors 9, the second chip 2 includes a plurality of second circuits 21 and a plurality of electrical connectors 9, the third chip 3 includes a plurality of third circuits 31 and a plurality of electrical connectors 9, the second circuit 21 is disposed on a side of the second chip 2 facing the third chip 3, the third circuit 31 is disposed on a side of the third chip 3 facing the second chip 2, the second chip 2 and the third chip 3 are connected to each other through the electrical connector 9, the first circuit 11 is disposed on a side of the first chip 1 facing the substrate 5, the first chip 1 is connected to the substrate 5 through the electrical connector 9, both ends of each communication channel are respectively provided with the first circuit 11 and the second circuit 21, both ends of each power supply circuit are respectively connected to the first circuit 11 and the second circuit 21, and the signal circuit.

[0052] In some alternative embodiments, according to the packaging structure provided by the above-mentioned one embodiment of the present application, wherein the front side of the first chip 1 refers to the side of the first chip 1 where the first circuit 11 is provided, and the back side of the first chip 1 refers to the other side of the first chip 1 opposite to the side where the first circuit 11 is provided; the front side of the second chip 2 refers to the side of the second chip 2 where the second circuit 21 is provided, and the back side of the second chip 2 refers to the other side of the second chip 2 opposite to the side where the second circuit 21 is provided; the front side of the third chip 3 refers to the side of the third chip 3 where the third circuit 31 is provided, and the back side of the third chip 3 refers to the other side of the third chip 3 opposite to the side where the third circuit 31 is provided.

[0053] Figure 8 Shows a schematic diagram of the manufacturing process of the packaging structure according to an embodiment of the present application. As Figure 8 shown, the manufacturing process of the packaging structure includes multiple steps:

[0054] Step 9001: Dispose the second chip 902 on the upper side near one end of the bending member 903, dispose the heat dissipation member 904 on the lower side near the other end of the bending member 903, and dispose the third chip 901 on the second chip 902 in a face-to-face manner; wherein, the third chip 901 and the second chip 902 are electrically connected through the electrical connector 905, the second chip 902 is provided with a plurality of second through holes 902a, the bending member 903 is provided with a plurality of third through holes 903a, and each second through hole 902a is respectively aligned with a third through hole 903a;

[0055] Step 9002: Wrap the third chip 901 and the second chip 902 with the molding encapsulation layer 906;

[0056] Step 9003: Flip the product made in Step 9002, and dispose the first chip 907 on the upper side of one end of the bending component 903 where the second chip 902 is disposed. The back surface of the first chip 907 faces the bending component 903. A plurality of first through holes 907a are provided on the 907, and each first through hole 907a is respectively aligned with a third through hole 903a;

[0057] Step 9004: Wrap the first chip 907 with the molding encapsulation layer 906;

[0058] Step 9005: Grind the molding encapsulation layer 906 wrapping the first chip 907 to expose the first circuit 907a at the top end of the first chip 907;

[0059] Step 9006: Dispose the electrical connection member 905 on the first circuit 907a;

[0060] Step 9007: Flip the product made in Step 9006, bend the bending component 903, so that one end where the heat dissipation component 904 is disposed is located above the third chip 901 and the bending component 903 contacts the back surface of the third chip 901. A separation space 908 is formed between the bent bending component 903 and the side of the molding encapsulation layer 906; and

[0061] Step 9008: Dispose the product made in Step 9007 on the substrate 909 to form a packaged product.

[0062] The advantages of the packaging structure according to the embodiment of the present application are as follows: the heat dissipation capacity of the stacked packaging structure is improved, and the interference of the heat concentration caused by insufficient heat dissipation to the signals in the packaging structure is reduced; the signal lines and the power supply lines are disposed in mutually isolated channels, avoiding the interference of the power supply lines to the signals.

[0063] Although the present application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to limit the present application. Those skilled in the art will clearly understand that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the scope of protection of the present application as defined by the claims. Due to variables in the manufacturing process and so on, there may be differences between the technical reproduction in the present application and the actual device. There may be other embodiments of the present application not specifically described. The specification and the drawings should be regarded as illustrative rather than restrictive, and modifications can be made in accordance with the purpose and spirit of the present application, all of which are within the scope of protection of the claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be recombined, subdivided, or arranged to form equivalent methods without departing from the disclosure of the present application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present application.

Claims

1. A packaging structure, characterized in that: include: First chip; A second chip is arranged above the first chip, and the second chip is a back side power supply chip; A third chip is arranged above the second chip; A bending component, the bending component comprising a first portion, a second portion and a third portion, the first portion being arranged between the first chip and the second chip, the first portion, the second portion and the third portion being connected in sequence, and the third portion being arranged above the third chip; a heat dissipation component, the heat dissipation component being arranged above the third portion; The bending component forms a heat dissipation path of the packaging structure, the width of the heat dissipation component is greater than the width of the third chip, and the heat dissipation path extends from the first part on the back side of the second chip through the second part to the third part on the back side of the third chip.

2. The packaging structure according to claim 1, characterized in that: The second chip and the third chip are arranged face to face.

3. The packaging structure according to claim 1, characterized in that: The packaging structure further includes a molding layer, which covers the side surfaces of the first chip, the second chip and the third chip. The second portion is located outside the molding layer, and a separation space is formed between the second portion and the molding layer.

4. The packaging structure according to claim 3, characterized in that: The packaging structure further includes a substrate, which is disposed below the first chip. In a cross-sectional direction, a width of the molding layer is different from a width of the substrate.

5. The packaging structure according to claim 1, characterized in that: The first chip is provided with a plurality of first through holes, the second chip is provided with a plurality of second through holes, and each of the first through holes is aligned with one of the second through holes.

6. The packaging structure according to claim 5, characterized in that: The first part is provided with a plurality of third through holes, each of the first through holes is communicated with the second through hole through one of the third through holes, and each group of the first through holes, the second through holes and the third through holes that are communicated with each other forms a communication channel.

7. The packaging structure according to claim 6, characterized in that: The packaging structure further includes a power supply circuit and a signal circuit, and the power supply circuit and the signal circuit are respectively arranged in different communication channels.

8. The packaging structure according to claim 1, characterized in that: The first portion is in contact with a back side of the first chip and a back side of the second chip at the same time.

9. The packaging structure according to claim 7, characterized in that: Each of the power supply circuits is electrically connected to any two or more of the first chip, the second chip, the third chip and the substrate, and each of the signal circuits is electrically connected to any two or more of the first chip, the second chip, the third chip and the substrate.

10. The packaging structure according to claim 7, characterized in that: The power supply circuit and the signal circuit are arranged in close contact inside the communication channel.

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