Semiconductor etching device

Abstract

The embodiment of the utility model discloses a semiconductor etching device, and the device comprises an etching chamber which is used for etching a wafer; the vacuum chamber is connected with the etching chamber; the vacuum chamber is used for providing a vacuum environment for the wafer; the loading interlocking chamber is connected with the vacuum chamber; the loading interlocking chamber is used for unloading the etched wafer from the vacuum chamber; the purification chamber is used for purifying the etched wafer so as to remove residual etching by-products on the surface of the etched wafer; wherein the position of the purification chamber comprises at least one of the connecting position of the vacuum chamber and the etching chamber, the interior of the vacuum chamber and the connecting position of the vacuum chamber and the loading interlocking chamber.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a semiconductor etching device. Background Art

[0002] With the continuous improvement of the performance of semiconductor devices and the rapid development of semiconductor technology, more stringent requirements are put forward for semiconductor manufacturing process conditions. Currently, the industry mostly controls the waiting time (Queue Time, Q-time) of adjacent stations to avoid the influence of the clean room environment on key stations due to excessive waiting time.

[0003] In the semiconductor manufacturing process, by strictly controlling the Q-time between the current station (for example, the etching process) and the next station, the probability of the wafer being oxidized or contaminated can be reduced, and the product yield can be improved. However, strictly controlling the Q-time will lead to technical problems such as low equipment utilization rate and difficulty in maximizing production capacity. Therefore, how to extend the Q-Time has become a technical problem that needs to be solved urgently. Summary of the Utility Model

[0004] Embodiments of the present disclosure provide a semiconductor etching device, including:

[0005] An etching chamber for etching a wafer;

[0006] A vacuum chamber connected to the etching chamber; the vacuum chamber is used to provide a vacuum environment for the wafer;

[0007] A load interlock chamber connected to the vacuum chamber; the load interlock chamber is used to unload the etched wafer from the vacuum chamber;

[0008] A purification chamber for purifying the etched wafer to remove residual etching by-products on the surface of the etched wafer; wherein, the position of the purification chamber includes at least one of the connection between the vacuum chamber and the etching chamber, inside the vacuum chamber, and the connection between the vacuum chamber and the load interlock chamber.

[0009] In some embodiments, the semiconductor etching device includes a plurality of the load interlock chambers; wherein, at least one of the plurality of load interlock chambers is provided with the purification chamber at the connection with the vacuum chamber.

[0010] In some embodiments, the semiconductor etching device includes a plurality of the etching chambers; wherein, at least one of the plurality of etching chambers is provided with the purification chamber at the connection with the vacuum chamber.

[0011] In some embodiments, the vacuum chamber includes a receiving space with a preset height; wherein, the purification chamber is located within the receiving space.

[0012] In some embodiments, the preset height is greater than the height of the purification chamber.

[0013] In some embodiments, the semiconductor etching apparatus further includes:

[0014] A purification gas supply component, the purification gas supply component is connected to the purification chamber; wherein, the purification gas supply component is configured to supply purification gas to the purification chamber.

[0015] In some embodiments, the semiconductor etching apparatus further includes:

[0016] An injection component, the injection component is located within the purification chamber; wherein, the injection component is configured to inject the purification gas provided into the purification chamber onto the surface of the wafer that has completed etching.

[0017] In some embodiments, the semiconductor etching apparatus further includes:

[0018] An air extraction component, the air extraction component is connected to the purification chamber; wherein, the air extraction component is configured to extract the purification gas carrying the etching by-products.

[0019] In some embodiments, the purification gas includes an inert gas.

[0020] In some embodiments, the semiconductor etching apparatus further includes:

[0021] A wafer cassette loading component, the wafer cassette loading component is connected to the loading interlock chamber; the wafer cassette loading component is configured to load a wafer cassette; the wafer cassette is configured to carry a plurality of wafers to be etched;

[0022] The loading interlock chamber is configured to load the plurality of wafers to be etched carried by the wafer cassette into the vacuum chamber.

[0023] In the embodiments of the present disclosure, by providing a purification chamber at least at one of the connection between the vacuum chamber and the etching chamber, inside the vacuum chamber, and the connection between the vacuum chamber and the loading interlock chamber, the purification chamber can purify the wafer that has completed etching in a vacuum environment, thereby removing the etching by-products remaining on the surface of the wafer that has completed etching, avoiding the contact reaction of the etching by-products with air, and further extending the Q-time of the wafer to the next station and reducing the generation of defects on the wafer surface, which is beneficial to improving the product yield and performance. Description of the Drawings

[0024] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0025] Figure 1 is a schematic diagram of a semiconductor etching device shown according to an exemplary embodiment.

[0026] Figure 2 is a schematic diagram of residues existing on the surface of a wafer shown according to an exemplary embodiment.

[0027] Figure 3 is a schematic diagram of by-products formed on the surface of a wafer shown according to an exemplary embodiment.

[0028] Figure 4 is a schematic diagram of a semiconductor etching device shown according to an embodiment of the present disclosure. Detailed implementation manners

[0029] To facilitate understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0030] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some well-known technical features are not described; that is, not all features of the actual embodiments can be described here, and the well-known functions and structures are not described in detail.

[0031] Generally, the terms can be understood at least in part from their use in the context. For example, at least in part depending on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage, at least in part depending on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can alternatively allow for the existence of additional factors that are not necessarily explicitly described, again at least in part depending on the context.

[0032] Unless otherwise defined, the terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0033] To fully understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0034] Figure 1 is a schematic diagram of a semiconductor etching apparatus 100 shown according to an exemplary embodiment, Figure 2 is a schematic diagram of residues existing on the surface of a wafer shown according to an exemplary embodiment, Figure 3 is a schematic diagram of by-products formed on the surface of a wafer shown according to an exemplary embodiment. The following will be combined with Figures 1 to 3 to give an exemplary description of the semiconductor etching apparatus 100 and the wafer etching process.

[0035] Referring to Figure 1 As shown, the semiconductor etching apparatus 100 includes an etching chamber 101, a vacuum chamber (Vacuum Transport Module, VTM) 102, and a load lock chamber 103. The wafer is etched in the etching chamber 101. The vacuum chamber 102 provides a vacuum environment during the wafer etching process. The load lock chamber 103 loads the wafer to be etched into the vacuum chamber 102 or unloads the etched wafer from the vacuum chamber 102.

[0036] Still referring to Figure 1As shown, the semiconductor etching apparatus 100 further includes a work platform 104, a wafer alignment component (aligner) 105, a wafer transfer robot (Robot) 106, and a wafer cassette loading component (Load Port, LP) 107. The wafer cassette loading component 107 is used to load a wafer cassette, and the wafer cassette can carry multiple wafers to be etched, so as to process multiple wafers in batches. The work platform 104 controls the wafer transfer robot 106 to transport the wafer cassette to be etched to the valve of the load interlock chamber 103 or to carry the wafer cassette that has completed etching from the valve of the load interlock chamber 103. The wafer alignment component 105 can detect whether alignment is achieved during the process of the wafer transfer robot 106 picking up and placing the wafer cassette (or wafer). Of course, the semiconductor etching apparatus 100 may further include other components known in the art. For the sake of brevity, Figure 1 not shown in the figure.

[0037] If the Q-time for the wafer etching process to enter the next station is too long after the wafer etching process is completed, the residues (such as gases, free radicals, etc.) of the etching process will come into contact with air and react, and the reaction products will react with the film layer on the wafer surface, and the by-products generated will become difficult to remove at the next station (such as a wet station), thereby generating defects such as residues and condensates on the wafer surface. Therefore, it is necessary to strictly control the Q-time between some etching stations and the next station to reduce the contact time with air and reduce the generation of defects. Figure 2 It shows that there are residues such as fluoride ions, chloride ions, and water on the wafer surface after etching the titanium nitride film layer, Figure 3 It shows that by-products are formed after etching the titanium nitride film layer on the wafer surface.

[0038] In one example, the etched wafer cassette can be placed in nitrogen for storage to extend the Q-time. However, this requires taking out the etched wafer cassette from the load interlock chamber 103 in a vacuum environment, and the residues on the wafer surface may still come into contact with air and react after being taken out. It should be noted that the load interlock chamber 103 is also called a pre-pumping chamber, and the outside of the valve connecting the load interlock chamber 103 and the work platform 104 is in an atmospheric environment.

[0039] Based on one or more of the above technical problems, the embodiments of the present disclosure provide a semiconductor etching apparatus. Figure 4 is a schematic diagram of a semiconductor etching apparatus shown according to the embodiments of the present disclosure. The following will be combined with Figure 4 to give an exemplary description of the semiconductor etching apparatus provided by the embodiments of the present disclosure.

[0040] Refer to Figure 4As shown, the semiconductor etching apparatus 200 includes an etching chamber 201, a vacuum chamber 202, a load interlock chamber 203, and a purification chamber 208. The semiconductor etching apparatus 200 may include etching apparatuses such as an Ion Beam Etching (IBE) apparatus, a Reactive Ion Etching (RIE) apparatus, a Magnetron-Enhanced Reactive Ion Etching (MERIE) apparatus, an Electron Cyclotron Resonance (ECR) plasma etching apparatus, and an Inductively Coupled Plasma (ICP) etching apparatus.

[0041] The etching chamber 201 is used for etching wafers. The etching chamber 201 mainly includes: a pedestal, an upper electrode, a lower electrode, a radio frequency system, a temperature control system, a cooling system, etc. For the sake of brevity, Figure 4 the components inside the etching chamber 201 are not shown in the figure. The number of etching chambers 201 may be one or more. Exemplarily, as Figure 4 shown, four etching chambers 201 are arranged at intervals around the vacuum chamber 202.

[0042] The vacuum chamber 202 is connected to the etching chamber 201, and the vacuum chamber 202 is used to provide a vacuum environment for the wafers. Exemplarily, as Figure 4 shown, the vacuum chamber 202 is connected to all four etching chambers 201 and provides a vacuum environment for each etching chamber 201, thereby providing a vacuum environment for the wafers in each etching chamber 201. The perspective view of the vacuum chamber 202 is as shown by the arrow ① in Figure 4 the figure. Here, the wafers to be etched can be transferred from the vacuum chamber 202 to the etching chamber 201, and the wafers that have been etched can be transferred from the etching chamber 201 to the vacuum chamber 202.

[0043] The load interlock chamber 203 is connected to the vacuum chamber 202, and the load interlock chamber 203 is used to unload the wafers that have been etched from the vacuum chamber 202. The number of load interlock chambers 203 may be one or more.

[0044] In some embodiments, the semiconductor etching apparatus 200 includes multiple load interlock chambers 203, and all of the multiple load interlock chambers 203 can be used for loading and unloading wafers; or, a part of the multiple load interlock chambers 203 is used for loading wafers, and another part of the multiple load interlock chambers 203 is used for unloading wafers.

[0045] Exemplarily, as Figure 4As shown, the two loading interlock chambers 203 are both connected to the vacuum chamber 202. In one example, both of the two loading interlock chambers 203 can load the wafers to be etched into the vacuum chamber 202 and unload the etched wafers from the vacuum chamber 202. In another example, one loading interlock chamber 203 can load the wafers to be etched into the vacuum chamber 202, and the other loading interlock chamber 203 can unload the etched wafers from the vacuum chamber 202. Here, the wafers to be etched can be transferred from the loading interlock chamber 203 to the vacuum chamber 202, and the etched wafers can be transferred from the vacuum chamber 202 to the loading interlock chamber 203.

[0046] The cleaning chamber 208 is used to clean the etched wafers to remove the etching by-products remaining on the surface of the etched wafers. The position of the cleaning chamber 208 includes at least one of the connection between the vacuum chamber 202 and the etching chamber 201, inside the vacuum chamber 202, and the connection between the vacuum chamber 202 and the loading interlock chamber 203. It can be understood that the etched wafers enter the cleaning chamber 208 for cleaning treatment, which can reduce the etching reactants remaining on the wafer surface (for example, residual gas, free radicals, etc.), thereby reducing the possibility of defects generated by the air contact with the wafers that have been etched first, and extending the Q-time of the wafers to the next station.

[0047] In one example, the cleaning chamber 208 can be located at the connection between the vacuum chamber 202 and the etching chamber 201, and the cleaning chamber 208 can clean the etched wafers in the etching chamber 201.

[0048] In another example, the cleaning chamber 208 can be located inside the vacuum chamber 202, and the cleaning chamber 208 can clean the wafers transferred from the etching chamber 201 to the vacuum chamber 202.

[0049] In yet another example, the cleaning chamber 208 can be located at the connection between the vacuum chamber 202 and the loading interlock chamber 203, and the cleaning chamber 208 can clean the wafers unloaded into the loading interlock chamber 203. The three-dimensional view of the cleaning chamber 208 and the loading interlock chamber 203 is as shown by arrow ② in Figure 4 as follows.

[0050] The above three examples regarding the position of the purification chamber 208 are only illustrative and are used to convey the present disclosure to those skilled in the art. In other embodiments, the purification chamber 208 may be located at the connection between the vacuum chamber 202 and the etching chamber 201 and within the vacuum chamber 202, or at the connection between the vacuum chamber 202 and the etching chamber 201 and at the connection between the vacuum chamber 202 and the load interlock chamber 203, or within the vacuum chamber 202 and at the connection between the vacuum chamber 202 and the load interlock chamber 203, or at the connection between the vacuum chamber 202 and the etching chamber 201, within the vacuum chamber 202, and at the connection between the vacuum chamber 202 and the load interlock chamber 203. In practical applications, those skilled in the art can reasonably set the position of the purification chamber according to requirements, and the present disclosure has no special restrictions on this.

[0051] In an embodiment of the present disclosure, by disposing the purification chamber 208 at least at one of the connection between the vacuum chamber 202 and the etching chamber 201, within the vacuum chamber 202, and at the connection between the vacuum chamber 202 and the load interlock chamber 203, the purification chamber 208 can purify the wafer after etching in a vacuum environment, thereby removing the residual etching by-products on the surface of the etched wafer, avoiding the reaction of the etching by-products with air, and further extending the Q-time of the wafer to the next station and reducing the generation of wafer surface defects, which is beneficial to improving the product yield and performance.

[0052] In some embodiments, the semiconductor etching apparatus 200 includes a plurality of etching chambers 201; among them, a purification chamber 208 is disposed at the connection between at least one of the plurality of etching chambers 201 and the vacuum chamber 202. Exemplarily, as Figure 4 shown, the semiconductor etching apparatus 200 includes four etching chambers 201, and a purification chamber 208 can be disposed at the connection between at least one of the etching chambers 201 and the vacuum chamber 202, and the purification chamber 208 can purify the wafers that have been etched in the corresponding etching chambers 201. In a specific embodiment, a purification chamber 208 can be disposed at the connection between each etching chamber 201 and the vacuum chamber 202.

[0053] In some embodiments, the semiconductor etching apparatus 200 includes a plurality of load interlock chambers 203; among them, a purification chamber 208 is disposed at the connection between at least one of the plurality of load interlock chambers 203 and the vacuum chamber 202. Exemplarily, as Figure 4 shown, the semiconductor etching apparatus 200 includes two load interlock chambers 203, and a purification chamber 208 can be disposed at the connection between at least one of the load interlock chambers 203 and the vacuum chamber 202, and the purification chamber 208 can purify the wafers unloaded into the corresponding load interlock chambers 203. In a specific embodiment, a purification chamber 208 can be disposed at the connection between the vacuum chamber 202 and each load interlock chamber 203.

[0054] In some embodiments, the vacuum chamber 202 includes a receiving space with a preset height; wherein, the purification chamber 208 is located within the receiving space. Exemplarily, the height of the vacuum chamber 202 can be increased, and the increased space of the vacuum chamber 202 (i.e., the receiving space) is used to accommodate the purification chamber 208, and the purification chamber 208 can purify the wafers transferred from the etching chamber 201 to the vacuum chamber 202.

[0055] In some embodiments, the preset height is greater than the height of the purification chamber 208. Here, by setting the preset height to be greater than the height of the purification chamber 208, it can be ensured that the increased space of the vacuum chamber 202 is sufficient to accommodate the purification chamber 208.

[0056] In some embodiments, the semiconductor etching apparatus 200 further includes: a purification gas supply assembly (not shown in the figure), and the purification gas supply assembly is connected to the purification chamber 208; wherein, the purification gas supply assembly is used to supply purification gas to the purification chamber 208.

[0057] In the embodiments of the present disclosure, the purification gas supply assembly can be connected to the purification chamber 208 through an intake pipeline. When it is necessary to purify the wafers, the purification gas can be introduced into the purification chamber 208 through the intake pipeline. Here, the purification gas includes inert gases, for example, argon, etc. Since the inert gas does not react with the etching by-products remaining on the wafer surface, purging the wafers with the purification gas can carry away the etching by-products remaining on the wafer surface and avoid the reaction of the etching by-products with air.

[0058] In some embodiments, the semiconductor etching apparatus 200 further includes: an intake valve, and the intake valve is located on the intake pipeline. Here, by opening the intake valve, the purification gas can be introduced into the purification chamber 208; by closing the intake valve, the introduction of the purification gas into the purification chamber 208 can be stopped; by adjusting the intake valve, the gas flow rate of the purification gas introduced into the purification chamber 208 can be controlled. The intake valve includes a manual valve or an automatic valve.

[0059] In some embodiments, the semiconductor etching apparatus 200 further includes: a spraying assembly, and the spraying assembly is located within the purification chamber 208; wherein, the spraying assembly is used to spray the purification gas provided into the purification chamber 208 onto the surface of the etched wafers.

[0060] In the embodiments of the present disclosure, spraying the purification gas onto the surface of the etched wafers by using the spraying assembly can increase the uniformity of the distribution of the purification gas, thereby better removing the etching by-products remaining on the wafer surface.

[0061] In some embodiments, the semiconductor etching apparatus 200 further includes: an air extraction assembly connected to the purification chamber 208; wherein, the air extraction assembly is configured to extract the purification gas carrying etching by-products.

[0062] In the embodiments of the present disclosure, the air extraction assembly can be connected to the purification chamber 208 through an air outlet pipeline. During the purification process of the wafer, the air extraction assembly can timely extract the purification gas carrying etching by-products.

[0063] In some embodiments, the semiconductor etching apparatus 200 further includes: an air outlet valve located on the air outlet pipeline. Here, by opening the air outlet valve, the purification gas can be extracted; by closing the air outlet valve, the extraction of the purification gas can be stopped. The air outlet valve includes a manual valve or an automatic valve.

[0064] In some embodiments, the semiconductor etching apparatus 200 further includes: a wafer cassette loading assembly 207 connected to the loading interlock chamber 203; the wafer cassette loading assembly 207 is configured to load a wafer cassette; the wafer cassette is used to carry a plurality of wafers to be etched, so as to process a plurality of wafers in batches. Here, the loading interlock chamber 203 is configured to load the plurality of wafers carried by the wafer cassette into the vacuum chamber 202. The number of the wafer cassette loading assemblies 207 can be one or more. Exemplarily, as Figure 4 shown, three wafer cassette loading assemblies 207 are arranged on the same side of the work platform 204.

[0065] In a specific embodiment, the wafer cassette is a Front Opening Unified Pod (FOUP). Of course, the wafer cassette can also be other types known in the art, and the present disclosure has no special limitation thereon.

[0066] In some embodiments, the semiconductor etching apparatus 200 further includes: a work platform 204, a wafer alignment assembly 205, and a wafer transfer robot 206. The work platform 204 controls the wafer transfer robot 206 to transport the wafer cassette to be etched to the valve of the loading interlock chamber 203 or to carry the etched wafer cassette from the valve of the loading interlock chamber 203. The wafer alignment assembly 205 can detect whether alignment is achieved during the process of the wafer transfer robot 206 picking up and placing the wafer cassette (or wafer).

[0067] The features disclosed in the several apparatus embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new apparatus embodiments.

[0068] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0069] It should be noted that in this text, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0070] As described above, the above are only the implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor etching device, characterized in that: include: An etching chamber, wherein the etching chamber is used for etching a wafer; A vacuum chamber, the vacuum chamber being connected to the etching chamber; the vacuum chamber being used to provide a vacuum environment for the wafer; A load lock chamber, the load lock chamber being connected to the vacuum chamber; the load lock chamber being used to unload the etched wafer from the vacuum chamber; A purification chamber is used to purify the wafer after etching to remove etching byproducts remaining on the surface of the wafer after etching; wherein the location of the purification chamber includes at least one of the connection between the vacuum chamber and the etching chamber, inside the vacuum chamber, and the connection between the vacuum chamber and the loading interlock chamber.

2. The semiconductor etching device according to claim 1, characterized in that: The semiconductor etching device comprises a plurality of the load lock chambers; wherein the purification chamber is provided at the connection between at least one of the load lock chambers and the vacuum chamber.

3. The semiconductor etching device according to claim 1 or 2, characterized in that: The semiconductor etching device comprises a plurality of etching chambers; wherein the purification chamber is provided at the connection between at least one etching chamber and the vacuum chamber among the plurality of etching chambers.

4. The semiconductor etching device according to claim 1, characterized in that: The vacuum chamber comprises a containing space of a preset height; wherein the purification chamber is located in the containing space.

5. The semiconductor etching device according to claim 4, characterized in that: The preset height is greater than the height of the purification chamber.

6. The semiconductor etching device according to claim 1, characterized in that: The semiconductor etching device further comprises: A purification gas supply assembly is connected to the purification chamber; wherein the purification gas supply assembly is used to provide purification gas to the purification chamber.

7. The semiconductor etching device according to claim 6, characterized in that: The semiconductor etching device further comprises: The injection assembly is located in the purification chamber; wherein the injection assembly is used to spray the purification gas provided into the purification chamber onto the surface of the wafer after etching.

8. The semiconductor etching device according to claim 7, characterized in that: The semiconductor etching device further comprises: A gas extraction component is connected to the purification chamber; wherein the gas extraction component is used to extract the purification gas carrying the etching by-products.

9. The semiconductor etching device according to claim 6, characterized in that: The purge gas includes an inert gas.

10. The semiconductor etching device according to claim 1, characterized in that: The semiconductor etching device further comprises: A wafer box loading assembly, the wafer box loading assembly is connected to the load interlock chamber; the wafer box loading assembly is used to load a wafer box; the wafer box is used to carry a plurality of wafers to be etched; The load lock chamber is used to load the plurality of wafers to be etched carried by the wafer box into the vacuum chamber.

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