Testing device

Abstract

The utility model discloses a testing device, belongs to the technical field of testing, and is used for improving the testing efficiency. The device comprises a substrate, a network port, a network switching element, a universal asynchronous receiver / transmitter (UART) serial port, a micro control unit (MCU) and a plurality of objects to be tested, the network port, the network switching element, the UART serial port, the MCU and the plurality of objects to be tested are arranged on the substrate; the network port is connected with the first end of the network switching element; the second end of the network switching element is connected with the plurality of to-be-tested objects; the UART serial port is connected with the first end of the MCU; and the second end of the MCU is connected with the plurality of to-be-tested objects.

Description

Technical Field

[0001] This application belongs to the field of testing technology, and particularly relates to a testing device. Background Art

[0002] For the testing of Embedded Multi Media Card (EMMC), it mainly includes two parts: 1. Hardware tests: involving power-off tests, power supply tests, etc.; 2. Software tests: involving read and write tests (multi-data block, single-data block, queued data, etc.), protocol compatibility tests (V5.1 and downward compatibility, etc.). For these tests, currently, they are mainly controlled separately through the serial port commands of Universal Asynchronous Receiver / Transmitter (UART) or the network interface.

[0003] However, whether controlling the EMMC test through UART serial port commands or the network interface, the testing device only supports single EMMC testing. Thus, when there are a large number of EMMCs to be tested, all the EMMCs to be tested cannot be tested simultaneously, resulting in the problem of low testing efficiency for EMMC testing. Summary of the Utility Model

[0004] The purpose of the embodiments of this application is to provide a testing device that can solve the problem of low EMMC testing efficiency.

[0005] To solve the above technical problems, this application is implemented as follows:

[0006] The embodiments of this application provide a testing device, which includes: a substrate, a network interface, a network switching element, a Universal Asynchronous Receiver / Transmitter (UART) serial port, a Microcontroller Unit (MCU), and multiple objects to be tested; the network interface, the network switching element, the UART serial port, the MCU, and the multiple objects to be tested are arranged on the substrate; the network interface is connected to the first end of the network switching element; the second end of the network switching element is connected to multiple objects to be tested; the UART serial port is connected to the first end of the MCU; the second end of the MCU is connected to the multiple objects to be tested.

[0007] In an embodiment of the present application, the test device includes: a substrate, a network interface, a network switching element, a Universal Asynchronous Receiver-Transmitter (UART) serial port, a Microcontroller Unit (MCU), and multiple objects to be tested; the network interface, the network switching element, the UART serial port, the MCU, and the multiple objects to be tested are disposed on the substrate; the network interface is connected to a first end of the network switching element; a second end of the network switching element is connected to the multiple objects to be tested; the UART serial port is connected to a first end of the MCU; a second end of the MCU is connected to the multiple objects to be tested, and this test device can simultaneously test multiple objects to be tested, improving the test efficiency. Description of the Drawings

[0008] Figure 1 is a schematic structural diagram of a test device provided by an embodiment of the present application;

[0009] Figure 2 is a schematic structural diagram of another test device provided by an embodiment of the present application;

[0010] Figure 3 is a logic block diagram of the network interface connection provided by an embodiment of the present application;

[0011] Figure 4 is a schematic diagram of the hardware test logic provided by an embodiment of the present application;

[0012] Figure 5 is a schematic structural diagram of another test device provided by an embodiment of the present application;

[0013] Figure 6 is a schematic diagram of the structure of a socket provided by an embodiment of the present application;

[0014] Figure 7 is a schematic diagram of the socket holes provided by an embodiment of the present application.

[0015] Reference Numerals:

[0016] Substrate - 10, Network Interface - 20, Network Switching Element - 30, Universal Asynchronous Receiver-Transmitter (UART) Serial Port - 40, Microcontroller Unit (MCU) - 50, Object to be Tested - 60, Network Communication Element - 601, Processor CPU - 602, Base - 603, Power Control Component - 604, Embedded Multimedia Card (EMMC) - 605. Detailed Description of the Embodiment

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0018] The following will, with reference to the accompanying drawings, elaborate in detail on a test device provided by an embodiment of the present application through specific embodiments and their application scenarios.

[0019] Figure 1 The following is a schematic structural diagram of a test device provided by an embodiment of the present application. The test device includes: a substrate 10, a network interface 20, a network switching element 30, a universal asynchronous receiver / transmitter UART serial port 40, a microcontroller unit MCU 50, and multiple objects to be tested 60; the network interface 20, the network switching element 30, the UART serial port 40, the MCU 50, and the multiple objects to be tested 60 are arranged on the substrate 10; the network interface 20 is connected to the first end of the network switching element 30; the second end of the network switching element 30 is connected to the multiple objects to be tested 60; the UART serial port 40 is connected to the first end of the MCU 50; the second end of the MCU 50 is connected to the multiple objects to be tested 60.

[0020] Specifically, as Figure 1As shown in the figure, the test device of the embodiment of the present application includes a substrate 10 and multiple objects to be tested 60. The multiple objects to be tested 60 and the substrate 10 can be connected together in various ways. For example, the multiple objects to be tested 60 and the substrate 10 can be fixed together through a connector socket and screws, or the multiple objects to be tested 60 and the substrate 10 can be welded together by welding, or the multiple objects to be tested 60 and the substrate 10 can be connected together by means of cable connection. Here, the connection method between the multiple objects to be tested 60 and the substrate 10 is not specifically limited. An EMMC is provided in the multiple objects to be tested 60, and the test device of the embodiment of the present application is used to test the EMMC in the object to be tested 60. The number of the multiple objects to be tested 60 can be set according to actual needs, and the number of the objects to be tested 60 is not specifically limited here. The substrate 10 can be a PCBA board, that is, a semi-finished product produced by the entire process of SMT patching or DIP plug-in on a PCB board. The substrate 10 includes a power supply, and the power supply mainly supplies power to the external power supply of the entire test device (substrate 10 and object to be tested 60). As an example, according to the total power consumption evaluation, the selected power supply can be: industrial switching power supply, RSP-200-12, 12V / 16.7A, 200W, terminal block. The power supply interface on the substrate 10 PCBA is a terminal block adapted to the power supply: terminal block, socket, 6-bit, 5.08mm pitch, 08mm pitch, pluggable, green, 15A / 300V, right angle, plug-in.

[0021] As Figure 1 shown, a network interface 20 is provided on the substrate 10. The network interface 20 is connected to the first end of the network switching element 30, and the second end of the network switching element 30 is connected to multiple objects to be tested 60.

[0022] In one implementation, the second ends of the network switching element 30 are multiple, and each second end of the network switching element 30 is connected to the object to be tested 60 one by one.

[0023] Specifically, the network switching element 30 can be a network switching chip including multiple ports. In this way, the multiple second ends of the network switching element 30 can be connected to multiple objects to be tested 60, where each second end is connected to the object to be tested 60 one by one. As an example, for example Figure 2 shown, dual network interfaces 20 can be provided on the substrate 10. The network switching element 30 can be a multi-port gigabit network switching chip, such as an 8-port gigabit network switching chip. In this way, each network interface 20 passes through an 8-port gigabit network switching chip, and a total of 16 network interfaces can be expanded, which are respectively connected to 16 objects to be tested 60. Finally, 16 objects to be tested 60 can be accessed through the dual network interfaces 20. As an example, Figure 3 is the network interface connection logic block diagram provided by the embodiment of the present application. AsFigure 3 As shown, the network switching element 30 can be an 8-port gigabit Ethernet switching chip RTL8380M. The first end (MAC0) of the 8-port gigabit Ethernet switching chip is connected to a gigabit PHY chip RTL8211F for the external RJ45 network port 20. For the Physical layer of the port, an Ethernet PHY is a chip that can send and receive Ethernet data frames. The PHY chip needs to cooperate with the MAC chip or other high-level controller chips so that the computer and network devices can perform data exchange. Each object 60 to be tested is connected to a gigabit PHY chip RTL8211F to communicate with the processor (Central Processing Unit, CPU) 602 of the object 60 to be tested. The multiple second ends (MAC1-MAC8) of the 8-port gigabit Ethernet switching chip are respectively connected to the PHY chips of the objects 60 to be tested one by one. In this way, the test packet data for testing the object 60 to be tested can be received through the network port 20 of the substrate 10 and transmitted to the CPUs 602 of the multiple objects 60 to be tested, and then the EMMC in the multiple objects 60 to be tested can be software-tested. In the embodiment of the present application, if more network ports 20 need to be expanded to test more EMMCs, only the number of network ports 20 and network switching elements 30 needs to be increased.

[0024] The UART serial port 40 on the substrate 10 can be a four-pin socket. The Universal Asynchronous Receiver / Transmitter (UART) is a general-purpose serial bidirectional data bus that can achieve full-duplex transmission and reception. In embedded design, the UART is used to communicate with the host computer, including communicating with the monitoring debugger and other devices. The communication substrate 10 can be connected to the host computer through the four-pin serial cable of the UART serial port 40 to receive the control signaling sent by the host computer. Since the first end of the UART serial port 40 is connected to the MCU50, the control signaling can be transmitted into the MCU50 through the UART serial port 40 for processing, and the control signaling is converted into the corresponding power control signal through the MCU50. The second end of the MCU50 is connected to the multiple objects 60 to be tested, and the power control signal is transmitted to the multiple objects 60 to be tested through the MCU50 to control the power on the object 60 to be tested, and then the EMMC in the object 60 to be tested can be hardware-tested.

[0025] In one implementation, the second end of the MCU50 is multiple, and each second end of the MCU50 is connected to the object 60 to be tested one by one.

[0026] Specifically, the second end of the MCU50 can be multiple, so that each second end of the MCU50 can be connected to the object 60 to be tested one by one.

[0027] As an example, Figure 4 shows the schematic diagram of the hardware test logic provided by the embodiments of the present application. As Figure 4 shown, the control signaling sent by the host computer is received through the UART serial port 40 and sent to the MCU 50. The MCU 50 can be a low-cost eight-bit N79E814A machine with a TSSOP20 package. Since the number of ports of the MCU 50 is limited, the chip PCA9534 for expanding the I / O ports through I2C is selected to expand the ports of the MCU 50. In this way, the MCU 50 has multiple ports. The MCU 50 converts the control signaling into corresponding power control signals and outputs the power control signals to multiple objects to be tested 60 for power control, so as to realize the hardware test of the EMMC in the objects to be tested 60.

[0028] The test device provided by the embodiments of the present application includes: a substrate 10, a network interface 20, a network switching element 30, a universal asynchronous transceiver UART serial port 40, a micro control unit MCU 50, and multiple objects to be tested 60; the network interface 20, the network switching element 30, the UART serial port 40, the MCU 50, and the multiple objects to be tested 60 are arranged on the substrate 10; the network interface 20 is connected to the first end of the network switching element 30; the second end of the network switching element 30 is connected to multiple objects to be tested 60; the UART serial port 40 is connected to the first end of the MCU 50; the second end of the MCU 50 is connected to the multiple objects to be tested 60, which can select different test methods according to different test type characteristics and can simultaneously test multiple EMMCs, improving the EMMC test efficiency.

[0029] In one implementation, the object to be tested 60 includes: a network communication element 601, a processor 602, and a base 603; the first end of the network communication element 601 is connected to the second end of the network switching element 30; the second end of the network communication element 601 is connected to the first end of the processor 602; the second end of the processor 602 is connected to the base 603.

[0030] Specifically, Figure 5 shows the structural schematic diagram of another test device provided by the embodiments of the present application. Figure 5 Only the structural schematic diagram of one object to be tested 60 is shown, and the structural schematic diagrams of other objects to be tested 60 are similar and will not be elaborated here. As Figure 5As shown, the object 60 to be tested is connected to the substrate 10 through a connector socket. The object 60 to be tested includes: a network communication component 601, a processor 602, and a base 603. The first end of the network communication component 601 can be connected to the second end of the network switching component 30 through the connector socket. In this way, after the test packet data output from the network switching component 30 of the substrate 10 is transmitted to the object 60 to be tested through the connector socket, it first passes through the network communication component 601 and then is transmitted to the GMAC module port of the CPU 602 of the object 60 to be tested. In this way, each CPU 602 of the object 60 to be tested can be accessed through the network port 20, the network switching component 30, and the network communication component 601.

[0031] In the embodiment of the present application, the CPU 602 provided may be the main control platform Cambrian MLU220 that supports the EMMC5.1 protocol, supports 2-channel 16-bit wide LPDDR4, dual-gigabit GMAC network, and 3 UART ports. After obtaining the test packet data, the CPU 602 can perform software-related reading and writing tests on the EMMC in the base 603, and output the data during the EMMC test process in real time through network packets for R & D and test personnel to save and analyze.

[0032] In one implementation, the object 60 to be tested includes: a power control component 604 and a base 603; the first end of the power control component 604 is connected to the second end of the micro control unit; the second end of the power control component 604 is connected to the base 603.

[0033] Specifically, as Figure 5 shown, the object 60 to be tested may include a power control component 604 and a base 603. Among them, the first end of the power control component 604 is connected to the second end of the micro control unit; the second end of the power control component 604 is connected to the base 603. In this way, the power control component 604 can receive the power control signal sent by the MCU 50, and then control the power of the base 603 to implement the power hardware test on the EMMC in the base 603.

[0034] In one implementation, the object 60 to be tested further includes: an embedded multimedia card EMMC 605, and the EMMC 605 is located in the base 603.

[0035] Specifically, as Figure 5 shown, an EMMC 605 is further provided in the base 603 of the object 60 to be tested. The EMMC 605 is located in the base 603, and the EMMC 605 is tested for software and hardware through settings in the base 603.

[0036] In one implementation, the object 60 to be tested includes a plurality of spare holes, and the spare holes are used to place the base 603.

[0037] Specifically, for the convenience of testers to replace the EMMC605 at any time, the upper base 603 of the object 60 to be tested can be designed in the form of a test socket for assembling the EMMC. Figure 6 The structural schematic diagram of the base 603 is shown. The base 603 and the PCBA board of the object to be tested are fixed by screwing through four fixing holes around. There are material sockets from different manufacturers on the market currently. Regardless of the size and shape, the signal pins and power pins under the EMMC pads are encapsulated in the same way, but the positions of the screw holes for fixing the socket on the PCBA board are different. The current EMMC test devices on the market are all designed for a specific manufacturer's socket material and cannot be compatible with sockets of multiple models at the same time. Once the manufacturer is changed, the original PCBA board needs to be redesigned. Therefore, in the embodiment of the present application, Figure 7 The compatibility design shown in the figure is adopted. At the fixing hole positions of the base 603, multiple spare hole positions are provided to accommodate the fixing hole positions required by the mainstream sockets on the market, which can meet the test requirements of different types of bases 603. If more types of bases 603 need to be compatible in the future, more spare hole positions can be designed in this compatible form, and the fixing hole positions to be compatible can be arranged on the object 60 to be tested, improving the expandability of the base 603.

[0038] The embodiments of the present application have been described above with reference to the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. A testing device, characterized in that: include: Baseboard, network port, network switching element, universal asynchronous receiver / transmitter UART serial port, microcontroller unit MCU and multiple objects to be tested; The network port, the network switching element, the UART serial port, the MCU and the plurality of objects to be tested are arranged on the substrate; The network port is connected to the first end of the network switching element; The second end of the network switching element is connected to a plurality of the objects to be tested; The UART serial port is connected to a first end of the MCU; The second end of the MCU is connected to the multiple objects to be tested.

2. The device according to claim 1, characterized in that The object to be tested includes: a network communication element, a processor and a base; The first end of the network communication element is connected to the second end of the network switching element; The second end of the network communication element is connected to the first end of the processor; The second end of the processor is connected to the base.

3. The device according to claim 1, characterized in that The object to be tested includes: a power supply control unit and a base; The first end of the power control element is connected to the second end of the micro control unit; The second end of the power control component is connected to the base.

4. The device according to claim 2 or 3, characterized in that The object to be tested comprises a plurality of spare holes, and the spare holes are used to place the base.

5. The device according to claim 1, characterized in that The network switching element has a plurality of second ends, and each second end of the network switching element is connected to the object to be tested one by one.

6. The device according to claim 1, characterized in that The number of second terminals of the MCU is multiple, and each second terminal of the MCU is connected to the object to be tested one by one.

7. The device according to claim 2 or 3, characterized in that The object to be tested also includes: An embedded multimedia card EMMC is located in the base.

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