Array substrate and display panel

Abstract

The utility model provides an array substrate and a display panel. The array substrate comprises a substrate; the driving device layer is arranged on one surface of the substrate; the pixel driving layer is arranged on the face, away from the substrate, of the driving device layer, a first transparent electrode and a shading layer are arranged in the pixel driving layer, a first contact hole and a second contact hole are synchronously formed in the pixel driving layer, at least part of the first transparent electrode is exposed out of the first contact hole, and at least part of the second transparent electrode is exposed out of the second contact hole. At least part of the shading layer is exposed out of the second contact hole; the second transparent electrode is arranged on the face, away from the substrate, of the pixel driving layer, the second transparent electrode is connected with the first transparent electrode through the first contact hole, and the second transparent electrode is connected with the shading layer through the second contact hole. According to the invention, the first contact hole and the second contact hole are formed in the same etching process, so that the process of one-time etching and hole forming is reduced, the process is simplified, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] The array substrate with oxide semiconductor thin film transistors and low temperature polysilicon thin film transistors has higher performance, but the structure of such an array substrate needs to be etched multiple times to form multiple contact holes, and multiple contact holes are used to realize the switching of multiple lines. Forming multiple contact holes by etching multiple times is not conducive to simplifying the process and reducing costs. Utility Model Content

[0003] In view of this, the present application provides an array substrate and a display panel to improve the problem that the manufacturing process of the array substrate is relatively complicated.

[0004] The technical solution adopted by this application to solve the above technical problems is:

[0005] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A driving device layer, disposed on one side of the substrate;

[0008] A pixel driving layer is provided on a side of the driving device layer away from the substrate, wherein a first transparent electrode and a light shielding layer are provided in the pixel driving layer, and a first contact hole and a second contact hole are opened in the pixel driving layer, wherein the first contact hole exposes at least a portion of the first transparent electrode, and the second contact hole exposes at least a portion of the light shielding layer;

[0009] The second transparent electrode is arranged on a side of the pixel driving layer away from the substrate, the second transparent electrode is connected to the first transparent electrode through the first contact hole, and the second transparent electrode is connected to the light shielding layer through the second contact hole.

[0010] In some embodiments of the present application, an etching rate of the first transparent electrode is lower than an etching rate of the second passivation layer and the third passivation layer.

[0011] In some embodiments of the present application, the pixel driving layer includes:

[0012] A first passivation layer is provided on a side of the driving device layer away from the substrate, and the light shielding layer is provided on a side of the first passivation layer away from the substrate;

[0013] a second passivation layer, disposed on a side of the first passivation layer away from the substrate and covering the light shielding layer, and a first transparent electrode disposed on a side of the second passivation layer away from the substrate;

[0014] a third passivation layer, disposed on a side of the second passivation layer away from the substrate and covering the first transparent electrode;

[0015] a fourth passivation layer, disposed on a side of the third passivation layer facing away from the substrate;

[0016] The first contact hole sequentially penetrates the fourth passivation layer and the third passivation layer to expose the first transparent electrode, and the second contact hole sequentially penetrates the fourth passivation layer, the third passivation layer and the second passivation layer to expose the light-shielding layer, and the sum of the vertical distance between the light-shielding layer and the first transparent electrode and the thickness of the first transparent electrode is not greater than the thickness of the second passivation layer.

[0017] In some embodiments of the present application, the second transparent electrode is disposed on a side of the fourth passivation layer facing away from the substrate.

[0018] In some embodiments of the present application, the shading layer is a metal layer and includes a first metal part and a second metal part, the first transparent electrode includes a first electrode part and a second electrode part; the first metal part and the second transparent electrode are connected through the second contact hole, the first electrode part and the second transparent electrode are connected through the first contact hole, and the second metal part and the second electrode part are aligned to form a first capacitor.

[0019] In some embodiments of the present application, a third transparent electrode is disposed in the fourth passivation layer, and the third transparent electrode is at least partially aligned with the second transparent electrode to form a second capacitor.

[0020] In some embodiments of the present application, a first transistor is provided in the driving device layer, and a third contact hole is opened in the pixel driving layer, the third contact hole penetrates the pixel driving layer and extends into the driving device layer, the third contact hole is used to expose one of the first source and the first drain of the first transistor, and the second transparent electrode is connected to one of the first source and the first drain of the first transistor through the third contact hole.

[0021] In some embodiments of the present application, a second transistor is also provided in the driving device layer, the first transistor includes a first gate, the second transistor includes a second source, a second drain and a second gate, the first gate and the second gate are arranged on the same layer, and the first source or the first drain is arranged on the same layer as the second source and the second drain.

[0022] In some embodiments of the present application, the light-shielding layer includes a first light-shielding sub-layer, a second light-shielding sub-layer and an isolation layer, the first light-shielding sub-layer is arranged on the side of the first passivation layer facing away from the substrate, the isolation layer is arranged on the side of the first light-shielding sub-layer facing away from the substrate, the second light-shielding sub-layer is arranged on the side of the isolation layer facing away from the substrate, and the second contact hole penetrates the second light-shielding sub-layer and the isolation layer to expose at least a portion of the first light-shielding sub-layer.

[0023] In a second aspect, an embodiment of the present application provides a display panel, comprising the array substrate as described in the first aspect.

[0024] In summary, due to the adoption of the above technical solution, this application has at least the following beneficial effects:

[0025] The embodiments of the present application provide an array substrate and a display panel. By simultaneously opening a first contact hole and a second contact hole on a pixel driving layer, the first contact hole and the second contact hole can be formed in the same process, which is conducive to reducing the number of processes and the use of a mask and reducing costs. Also, by exposing the first transparent electrode in the first contact hole and exposing the light shielding layer in the second contact hole, the second transparent electrode can be deposited in the first contact hole and the second contact hole respectively in one process, and then the second transparent electrode is connected to the light shielding layer and the first transparent electrode respectively in the same process, further reducing the process and reducing costs. In addition, by forming a light shielding layer, light is transmitted only where it is needed, thereby improving the clarity and contrast of the image. By connecting the second transparent electrode with the first transparent electrode and the light shielding layer, a more stable and efficient electrical performance is achieved, and the overall functionality of the array substrate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of an array substrate provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a light shielding layer in an array substrate provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a display panel provided for a first comparative example;

[0029] Figure 4 A schematic diagram of a display panel provided for a second comparative example;

[0030] Figure 5 A preparation flow chart of an array substrate provided in an embodiment of the present application (Part 1);

[0031] Figure 6 A preparation flow chart of an array substrate provided in an embodiment of the present application (Part 2).

[0032] Description of reference numerals:

[0033] 100, array substrate; 110, substrate; 111, buffer layer; 120, driving device layer; 121, first transistor; 1211, first source; 1212, first drain; 1213, first active layer; 1214, first gate; 122, second transistor; 1221, second source; 1222, second drain; 1223, second gate; 1224, second active layer; 130, pixel driving layer; 131, first contact hole; 132, second contact hole; 133, first passivation layer; 134, second passivation layer; 135. A third passivation layer; 136. A fourth passivation layer; 137. A first planarization layer; 138. A second planarization layer; 139. A third planarization layer; 140. A first transparent electrode; 141. A first electrode portion; 142. A second electrode portion; 150. A light shielding layer; 151. A first light shielding sub-layer; 152. A second light shielding sub-layer; 153. An isolation layer; 154. A first metal portion; 155. A second metal portion; 160. A second transparent electrode; 170. A third transparent electrode; 180. A fourth transparent electrode; 190. A fifth transparent electrode. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0035] In the description of this application, it should be understood that the words "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0036] In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0037] See also Figure 1 , an embodiment of the present application provides an array substrate 100, comprising:

[0038] Substrate 110;

[0039] The driving device layer 120 is disposed on one side of the substrate 110;

[0040] The pixel driving layer 130 is disposed on the side of the driving device layer 120 facing away from the substrate 110. The pixel driving layer 130 is provided with a first transparent electrode 140 and a light shielding layer 150. The pixel driving layer 130 is simultaneously provided with a first contact hole 131 and a second contact hole 132. Synchronization here means that the first contact hole 131 and the second contact hole 132 are formed in the same etching process. The first contact hole 131 exposes at least a portion of the first transparent electrode 140, and the second contact hole 132 exposes at least a portion of the light shielding layer 150;

[0041] The second transparent electrode 160 is disposed on a side of the pixel driving layer 130 away from the substrate 110 . The second transparent electrode 160 is connected to the first transparent electrode 140 through the first contact hole 131 . The second transparent electrode 160 is connected to the light shielding layer 150 through the second contact hole 132 .

[0042] The technical solution provided by the present application is to simultaneously open the first contact hole 131 and the second contact hole 132 on the pixel driving layer 130, so that the first contact hole 131 and the second contact hole 132 can be formed in the same process, which is conducive to reducing the number of processes and the use of the mask and reducing costs. In addition, by making the first contact hole 131 expose the first transparent electrode 140 and the second contact hole 132 expose the light shielding layer 150, the second transparent electrode 160 can be deposited in the first contact hole 131 and the second contact hole 132 in one process, respectively, and then in the same process, the second transparent electrode 160 is connected to the light shielding layer 150 and the first transparent electrode 140 respectively, further reducing the process and reducing costs. In addition, by forming the light shielding layer 150, the light is transmitted only where it is needed, thereby improving the clarity and contrast of the image. Through the connection between the second transparent electrode 160 and the first transparent electrode 140 and the light shielding layer 150, a more stable and efficient electrical performance is achieved, and the overall functionality of the array substrate 100 is improved.

[0043] In some embodiments, the pixel driving layer 130 includes:

[0044] The first passivation layer 133 is disposed on the side of the driver device layer 120 facing away from the substrate 110, and is mainly used to protect the components in the driver device layer 120, such as transistors, and provide a flat surface for the deposition of subsequent layers. The light shielding layer 150 is disposed on the side of the first passivation layer 133 facing away from the substrate 110, and is used to prevent light from entering the driver device layer 120 and affecting the components in the pixel driving layer, such as transistors, thereby reducing light leakage and improving the display effect. The light shielding layer 150 is usually made of metal material to ensure its good light shielding performance.

[0045] The second passivation layer 134 is disposed on the side of the first passivation layer 133 away from the substrate 110 and covers the light shielding layer 150, and is mainly used to protect the light shielding layer 150 and provide insulation to ensure the stability of electrical performance. The first transparent electrode 140 is disposed on the side of the second passivation layer 134 away from the substrate 110. The first transparent electrode 140 is generally made of indium tin oxide or other transparent conductive materials, and is mainly used to drive pixels in the display panel.

[0046] The third passivation layer 135 is disposed on a side of the second passivation layer 134 facing away from the substrate 110 and covers the second transparent electrode 160 , and is mainly used to provide an additional protective layer to ensure the stability and durability of the first transparent electrode 140 .

[0047] The fourth passivation layer 136 is disposed on a side of the third passivation layer 135 facing away from the substrate 110 . Similarly, it is mainly used to provide additional protection to improve the overall performance and durability of the array substrate 100 .

[0048] Among them, the first contact hole 131 penetrates the fourth passivation layer 136 and extends to the third passivation layer 135 to expose the first transparent electrode 140, the second contact hole 132 penetrates the fourth passivation layer 136 and the third passivation layer 135, and extends to the second passivation layer 134 to expose the shading layer 150, and the sum of the vertical distance between the shading layer 150 and the first transparent electrode 140 and the thickness of the first transparent electrode 140 is not greater than the thickness of the second passivation layer 134.

[0049] By limiting the sum of the vertical distance between the light shielding layer 150 and the first transparent electrode 140 and the thickness of the first transparent electrode 140 to be no greater than the thickness of the second passivation layer 134, it is ensured that the distance between the first transparent electrode 140 and the light shielding layer 150 is not too large, so that the etching liquid can complete the etching of the second passivation layer 134 as soon as possible after etching the first transparent electrode 140, so as to expose the light shielding layer 150 as soon as possible, and avoid the first transparent electrode 140 being etched through and damaged due to the first contact hole 131 and the second contact hole 132 being formed in the same process by using a layer of photomask. By reducing the vertical distance between the first transparent electrode 140 and the light shielding layer 150, the etching time of the etching liquid on the first transparent electrode 140 can be effectively shortened, thereby effectively avoiding the first transparent electrode 140 from being damaged. At the same time, without damaging the first transparent electrode 140, only one photomask is needed and the first contact hole 131 and the second contact hole 132 are formed in the same process.

[0050] Furthermore, the etching rate of the first transparent electrode 140 is lower than the etching rate of the second passivation layer 134 and the third passivation layer 135. After the first transparent electrode 140 is deposited in the driving device layer 120, it will also be subjected to annealing treatment, which is mainly used to reduce defects and impurities in the first transparent electrode 140, improve its conductivity, and increase the grain size of the first transparent electrode 140, reduce light scattering, and improve transparency. It can also make the first transparent electrode 140 more uniform and dense, and improve its mechanical strength and stability. After the annealing treatment, the first transparent electrode 140 will also have an improved ability to resist etching, so that the etching rate of the first transparent electrode 140 is lower than the etching rate of the passivation layer, further extending the etching resistance time of the first transparent electrode 140, so that the second passivation layer 134 can be etched before the first transparent electrode 140 is damaged by etching, so as to expose the light shielding layer 150.

[0051] In some embodiments, the array substrate 100 further includes a second transparent electrode 160, which is disposed on a side of the fourth passivation layer 136 away from the substrate 110, and the second transparent electrode 160 is connected to the first transparent electrode 140 through the first contact hole 131, and the second transparent electrode 160 is connected to the light shielding layer 150 through the second contact hole 132. Through the connection between the second transparent electrode 160 and the first transparent electrode 140 and the light shielding layer 150, a more stable and efficient electrical performance is achieved, and the overall functionality of the array substrate 100 is improved. The contact holes formed in the same etching process simplify the manufacturing process, reduce the process complexity and production cost. Through the effective blocking of the light shielding layer 150, light leakage is reduced and the display effect is improved. The introduction of the second transparent electrode 160 and the diversity of connection methods make the array substrate 100 more flexible in design and application, and can adapt to different application requirements. The multi-layer passivation layer provides good protection to prevent the influence of the external environment on the electrodes and transistors, and improves the durability and reliability of the array substrate 100.

[0052] Furthermore, the shading layer 150 is a metal layer and includes a first metal portion 154 and a second metal portion 155, and the first transparent electrode 140 includes a first electrode portion 141 and a second electrode portion 142; the first metal portion 154 is connected to the second transparent electrode 160 through a second contact hole 132, the first electrode portion 141 is connected to the second transparent electrode 160 through the first contact hole 131, and the second metal portion 155 is aligned with the second electrode portion 142 to form a first capacitor.

[0053] The second transparent electrode 160 is connected to the first transparent electrode 140 and the light shielding layer 150 respectively to achieve multi-point connection, so that the current can flow through the electrode more stably, reduce resistance and improve conductivity. In addition, the metal material of the light shielding layer 150 has excellent conductivity, and is connected to the second transparent electrode 160 through the second contact hole 132, further improving the overall electrical performance. The light shielding layer 150 effectively blocks light from entering the transistor area and reduces light leakage. Light leakage will cause the image on the display to be blurred, affecting the display effect. By using the light shielding layer 150, it can be ensured that light is only transmitted where it is needed, thereby improving the clarity and contrast of the image. By aligning the second metal part 155 with the second electrode part 142 to form a capacitor, the array substrate 100 can store charge and enhance signal processing capabilities.

[0054] In some embodiments, a third transparent electrode 170 is provided in the fourth passivation layer 136, and the third transparent electrode 170 is at least partially aligned with the second transparent electrode to form a second capacitor. The specific capacitance of the second capacitor depends on the overlapping area between the electrodes, the dielectric constant of the dielectric material and the distance between the electrodes. The capacitance of the capacitor is proportional to the overlapping area between the electrodes. By partially aligning the second transparent electrode 160 and the third transparent electrode 170, the overlapping area between the electrodes is increased, thereby increasing the capacitance density. A higher capacitance density helps to improve the storage capacity and signal processing capabilities of the array substrate 100, especially in high-resolution displays, which can more effectively control the switching state of the pixels. The capacitor plays the role of filtering, energy storage and voltage stabilization in the circuit. By adding a second capacitor, power supply noise and voltage fluctuations can be effectively reduced, a more stable power supply can be provided, and transistors and electrodes can be ensured to work in a stable voltage environment, thereby improving the overall stability and reliability of the circuit. The presence of the capacitor can smooth voltage fluctuations and ensure stable driving of pixels. By arranging the third transparent electrode 170 in the fourth passivation layer 136, a transparent electrode deposition step can be added to the original passivation layer deposition process without adding additional complex process steps.

[0055] In some embodiments, a first transistor 121 is provided in the driver device layer 120, and a third contact hole is provided in the pixel driver layer 130, the third contact hole penetrates the pixel driver layer 130 and extends into the driver device layer 120, and the third contact hole is used to expose one of the first source 1211 and the first drain 1212 of the first transistor 121, and the second transparent electrode 160 is connected to one of the first source 1211 and the first drain 1212 of the first transistor 121 through the third contact hole. In the conventional process, the formation of each contact hole requires an independent etching step, but in the present embodiment, three contact holes can be formed through two etching processes, which significantly simplifies the manufacturing process. The third contact hole directly penetrates the pixel driver layer 130 and extends to the driver device layer 120, thereby realizing the electrical connection between the second transparent electrode 160 and the first transistor 121. This direct connection method reduces the resistance and capacitance in the electrical connection path, and improves the efficiency and stability of electrical signal transmission. By optimizing the design of contact holes and electrical connection paths, the loss and interference of electrical signals during transmission can be effectively reduced, ensuring that transistors and electrodes can operate in a stable voltage environment, thereby improving the response speed and image quality of the display.

[0056] In some embodiments, a second transistor 122 is further provided in the driver device layer 120, the first transistor 121 includes a first gate 1214, the second transistor 122 includes a second source 1221, a second drain 1222 and a second gate 1223, the first gate 1214 and the second gate 1223 are arranged in the same layer, and the first source 1211 or the first drain 1212 is arranged in the same layer as the second source 1221 and the second drain 1222. Arranging the first gate 1214 and the second gate 1223 in the same layer can save a patterning process of gate formation, simplify the procedure and reduce costs. Similarly, arranging the first source 1211 or the first drain 1212 in the same layer as the second source 1221 and the second drain 1222 can also save a patterning process of gate formation, simplify the procedure and reduce costs. In this embodiment, it is preferred that the first source 1211 is arranged in the same layer as the second source 1221 and the second drain 1222.

[0057] In some embodiments, the driver device layer 120 includes:

[0058] The buffer layer 111 is disposed on one side of the substrate 110. The buffer layer 111 may be formed by stacking multiple inorganic layers or a single inorganic layer. In this embodiment, the buffer layer 111 is formed by multiple inorganic layers, and the inorganic layer may be silicon dioxide or nitrogen oxide. The second active layer 1224 of the second transistor 122 is disposed on the side of the buffer layer 111 away from the substrate 110.

[0059] The first gate insulating layer is formed on the side of the buffer layer 111 facing away from the substrate 110 and covers the second active layer 1224. The first gate 1214 in the first transistor 121 and the second gate 1223 in the second transistor 122 are provided on the side of the first gate insulating layer facing away from the substrate 110.

[0060] The second gate insulating layer is formed on the side of the first gate insulating layer facing away from the substrate 110 and covers the first gate 1214 and the second gate 1223. The first active layer 1213 of the first transistor 121 is disposed on the side of the second gate insulating layer facing away from the substrate 110.

[0061] The third gate insulating layer is formed on the side of the second gate insulating layer facing away from the substrate 110 and covers the first active layer 1213 of the first transistor 121. A plurality of transfer holes are etched on the third gate insulating layer, and one of the first source 1211 and the first drain 1212 of the first transistor 121 is disposed on the side of the third gate insulating layer facing away from the substrate 110, and the second source 1221 and the second drain 1222 of the second transistor 122 are disposed, and the second source 1221 and the second drain 1222 are respectively connected to the second active layer 1224 through different transfer holes.

[0062] The first dielectric layer is formed on the side of the third gate insulating layer facing away from the substrate 110 and covers the first source 1211 or the first drain 1212 of the first transistor 121 and covers the second source 1221 and the second drain 1222 of the second transistor 122. A transfer hole is opened on the first dielectric layer, and the other of the first source 1211 and the first drain 1212 of the first transistor 121 is arranged on the side of the first dielectric layer facing away from the substrate 110, and is connected to the first active layer 1213 through the transfer hole.

[0063] The second dielectric layer is disposed on the side of the first dielectric layer facing away from the substrate 110 and covers the other of the first source 1211 and the first drain 1212 of the first transistor 121. The second dielectric layer is provided with a first blind hole, which penetrates the second dielectric layer and extends to the third gate insulating layer, so that a portion of the first active layer 1213 is exposed. A fourth transparent electrode 180 is disposed on the side of the second dielectric layer facing away from the substrate 110, and the fourth transparent electrode 180 extends along the inner wall of the first blind hole, so that the fourth transparent electrode 180 is connected to the exposed first active layer 1213.

[0064] The third dielectric layer is disposed on the side of the second dielectric layer facing away from the substrate 110 and covers the fourth transparent electrode 180. Correspondingly, due to the existence of the first blind hole, the third dielectric layer will also fill part of the first blind hole during the deposition process, resulting in a blind hole structure in the third dielectric layer.

[0065] In some embodiments, the specific structural relationship between the pixel driving layer 130 and the driving device layer 120 is as follows:

[0066] The pixel driving layer 130 includes a first planarization layer 137, which is disposed between the third dielectric layer and the first passivation layer 133. The first planarization layer 137 fills the blind hole on the third dielectric layer so that the subsequent stacking structure can be carried out on a flat surface. A second blind hole is opened from the third passivation layer 135, and the second blind hole sequentially penetrates the third passivation layer 135, the second passivation layer 134, the first passivation layer 133, the first planarization layer 137 and extends to the third dielectric layer to expose part of the fourth transparent electrode 180. A fifth transparent electrode 190 is disposed on the side of the third passivation layer 135 facing away from the substrate 110, and the fifth transparent electrode 190 extends along the inner wall of the second blind hole so that the fifth transparent electrode 190 is in contact with the fourth transparent electrode 180. Because the fifth transparent electrode 190 is arranged along the inner wall of the second blind hole, the fifth transparent electrode 190 defines a blind hole, and the second planarization layer 138 is arranged in the blind hole, thereby eliminating the blind hole formed by the fifth transparent electrode 190, and the side of the second planarization layer 138 facing away from the substrate 110 is flush with the side of the fifth transparent electrode 190 facing away from the substrate 110. The third planarization layer 139 and the third transparent electrode 170 are arranged on the surface flush with the fifth transparent electrode 190 and the second planarization layer 138, and the third transparent electrode 170 covers the third planarization layer 139, and the fourth passivation layer 136 covers the third transparent electrode 170, so as to isolate the second transparent electrode 160 from the third transparent electrode 170, and form a second capacitor.

[0067] In some embodiments, see Figure 1 and Figure 2 The light shielding layer 150 includes a first light shielding sublayer 151, a second light shielding sublayer 152 and an isolation layer 153. The first light shielding sublayer 151 is disposed on a side of the first passivation layer 133 facing away from the substrate 110, the isolation layer 153 is disposed on a side of the first light shielding sublayer 151 facing away from the substrate 110, the isolation layer 153 is disposed on a side of the first light shielding sublayer 151 facing away from the substrate 110, the second light shielding sublayer 152 is disposed on a side of the isolation layer 153 facing away from the substrate 110, and the second contact hole 132 penetrates the second light shielding sublayer 152 and the isolation layer 153 to expose at least a portion of the first light shielding sublayer 151.

[0068] The multi-layer structure of the light shielding layer 150 (the first light shielding sublayer 151, the isolation layer 153 and the second light shielding sublayer 152) provides multiple light shielding effects. The multi-layer light shielding structure can more effectively block the interference of external light and prevent light from penetrating, thereby improving the contrast and picture quality of the display panel. The isolation layer 153 is arranged between the first light shielding sublayer 151 and the second light shielding sublayer 152, effectively isolating the two layers of light shielding materials to avoid electrical interference. The presence of the isolation layer 153 ensures the electrical independence between different light shielding layers 150, reduces electromagnetic interference, and enhances the stability of electrical performance. The second contact hole 132 passes through the second light shielding sublayer 152 and the isolation layer 153, exposing the first light shielding sublayer 151. By optimizing the design of the contact hole, the electrical connection of the light shielding layer 150 can be achieved, while ensuring the independence of materials at different levels and avoiding mutual interference.

[0069] This example provides two comparative examples. Figure 3 and Figure 4 , Figure 3 A schematic diagram of a display panel provided for a first comparative example, Figure 4 A schematic diagram of a display panel provided for a second comparative example. Figure 3 In the embodiment, the display panel includes a substrate 110, a buffer layer 111, a driver layer 120 and a pixel driver layer 130 which are stacked in sequence. The pixel driver layer 130 further includes a first planarization layer 137, a first passivation layer 133, a second passivation layer 134 and a third passivation layer 135 which are stacked in sequence. A light shielding layer 150 is provided on the first passivation layer 133, the second passivation layer 134 covers the light shielding layer 150, and a second transparent electrode 160 is provided on the third passivation layer 135. The second transparent electrode 160 penetrates the passivation layer and overlaps with the light shielding layer 150 to form a second contact hole 132, and penetrates the entire pixel driver layer 130 and extends into the driver layer 120 to form a first contact hole 131, which overlaps with the metal layer in the driver layer 120. The depths of the first contact hole 131 and the second contact hole 132 are very different, and cannot be formed in the same process using the same mask, that is, in this comparative example, the two contact holes need to be formed by two processes. In this comparative example, a third transparent electrode 170 is disposed in the third passivation layer 135, and the third transparent electrode 170 is partially aligned with the second transparent electrode 160 to form a capacitor. It can be seen that the display panel in this comparative example only forms one capacitor.

[0070] exist Figure 4In the embodiment, the display panel includes a substrate 110, a buffer layer 111, a driving device layer 120 and a pixel driving layer 130 which are sequentially stacked. The pixel driving layer 130 further includes a first planarization layer 137, a first passivation layer 133, a second passivation layer 134, a third passivation layer 135, and a fourth passivation layer 136 which are stacked in sequence. A light shielding layer 150 is provided on the first passivation layer 133, and a first transparent electrode 140 is formed on the second passivation layer 134. The first transparent electrode 140 penetrates the second passivation layer 134 and overlaps with the light shielding layer 150. The first transparent electrode 140 also penetrates the second passivation layer 134, the first passivation layer 133, and the first planarization layer 137 in sequence and extends to the inside of the driving device layer 120, and overlaps with the metal layer inside the driving device layer 120. Although a capacitor can be formed between the first transparent electrode 140 and the light shielding layer 150, since the two metal layers overlapped by the first transparent electrode 140 are far apart, only two etching processes can be used to form two contact holes, so that the first transparent electrode 140 can overlap with the light shielding layer 150 and the metal layer in the driving device layer 120 respectively. A second transparent electrode 160 is disposed on the fourth passivation layer 136, and the second transparent electrode 160 is overlapped with the first transparent electrode 140 through a contact hole formed by an etching process, and a photomask is also required here, that is, the formation of three contact holes requires three etchings and three photomasks. Similar to the first comparative example, the second transparent electrode 160 and the third transparent electrode 170 can also form a capacitor.

[0071] In summary, the first comparative example requires two photomasks to form two contact holes, and a capacitor is formed by a transparent electrode. Single-layer capacitors are gradually unable to meet the current needs of small size and high resolution. The second comparative example is improved on the basis of the first comparative example, using three photomasks to form three contact holes, and forming a capacitor by the cooperation of transparent electrodes and transparent electrodes, and a capacitor is formed by the cooperation of transparent electrodes and light-shielding layers. A total of two capacitors can be formed, which can achieve the beneficial effects of higher resolution and smaller size compared to the first comparative example, but will increase the etching process and the number of times the mask is used, which is not conducive to cost reduction. It can be seen that both comparative examples have certain shortcomings, and the technical solution provided by the present application only requires two etching processes and two photomasks to realize double-layer capacitors, which can not only meet the requirements of small size and high resolution, but also reduce costs and save process time.

[0072] See also Figure 5 and Figure 6 , an embodiment of the present application provides a method for preparing a display panel, comprising:

[0073] A buffer layer 111 is formed on the substrate 110, a driving device layer 120 is formed on the buffer layer 111, and a pixel driving layer 130 is formed on the driving device layer 120. The preparation method of the pixel driving layer 130 further includes:

[0074] forming a first planarization layer 137 on the driving device layer 120;

[0075] forming a first passivation layer 133 on the first planarization layer 137;

[0076] A patterned light shielding layer 150 and a second passivation layer 134 are formed on the first passivation layer 133 , and the second passivation layer 134 covers the light shielding layer 150 ;

[0077] A patterned first transparent electrode 140 and a third passivation layer 135 are formed on the second passivation layer 134 , wherein the third passivation layer covers the first transparent electrode 140 ;

[0078] The third passivation layer 135 , the second passivation layer 134 , the first passivation layer 133 , the first planarization layer 137 and a portion of the driving device layer 120 are sequentially etched to form a via hole;

[0079] A fifth transparent electrode 190 is formed on the third passivation layer 135 , and a portion of the fifth transparent electrode 190 is deposited on the inner wall of the via hole;

[0080] Depositing a second planarization layer 138 in the via hole to cover the portion of the fifth transparent electrode 190 located in the via hole;

[0081] A third planarization layer 139 and a third transparent electrode 170 are formed on the fifth transparent electrode 190 , and the third transparent electrode 170 covers the third planarization layer 139 ;

[0082] forming a fourth passivation layer 136 on the third passivation layer 135 , wherein the fourth passivation layer 136 covers the third transparent electrode 170 and the fifth transparent electrode 190 ;

[0083] The fourth passivation layer 136, the third passivation layer 135, the second passivation layer 134, the first passivation layer 133, the first planarization layer 137 and a portion of the driving device layer 120 are sequentially etched to form a third contact hole, wherein the third contact hole exposes the metal layer;

[0084] The fourth passivation layer 136 , the third passivation layer 135 , and the second passivation layer 134 are sequentially etched to form a first contact hole 131 and a second contact hole 132 , wherein the first contact hole 131 exposes the first transparent electrode 140 , and the second contact hole 132 exposes the light shielding layer 150 ;

[0085] A second transparent electrode 160 is formed on the fourth passivation layer 136 , a portion of the second transparent electrode 160 is deposited into the third contact hole and overlaps with the metal layer, a portion of the second transparent electrode 160 is deposited into the second contact hole 132 and overlaps with the light shielding layer 150 , and a portion of the second transparent electrode 160 is deposited into the first contact hole 131 and overlaps with the second transparent electrode 160 .

[0086] It should be noted that, since the etching rate of the first transparent electrode 140 is lower than the etching rate of the second passivation layer 134 and the third passivation layer 135, when etching is performed to form the first contact hole 131 and the second contact hole 132, when the first contact hole 131 is completely etched to expose the second transparent electrode 160, the etching liquid will continue to etch the first transparent electrode 140, the second passivation layer 134, and the third passivation layer 135, and the first transparent electrode 140 can slow down the etching speed of the etching liquid, thereby ensuring that when the second contact hole 132 is formed to expose the light shielding layer 150, the first transparent electrode 140 will not be completely etched away by the etching liquid, so that two contact holes are formed in the same process and the first transparent electrode 140 can be retained.

[0087] An embodiment of the present application further provides a display panel, which includes the array substrate 100 described in any one of the above embodiments.

[0088] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0089] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of the present application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of the present application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

Claims

1. An array substrate, characterized in that: include: substrate; A driving device layer, disposed on one side of the substrate; A pixel driving layer is provided on a side of the driving device layer away from the substrate, wherein a first transparent electrode and a light shielding layer are provided in the pixel driving layer, and a first contact hole and a second contact hole are opened in the pixel driving layer, wherein the first contact hole exposes at least a portion of the first transparent electrode, and the second contact hole exposes at least a portion of the light shielding layer; The second transparent electrode is arranged on a side of the pixel driving layer away from the substrate, the second transparent electrode is connected to the first transparent electrode through the first contact hole, and the second transparent electrode is connected to the light shielding layer through the second contact hole.

2. The array substrate according to claim 1, characterized in that: The pixel driving layer comprises: A first passivation layer is provided on a side of the driving device layer away from the substrate, and the light shielding layer is provided on a side of the first passivation layer away from the substrate; a second passivation layer, disposed on a side of the first passivation layer away from the substrate and covering the light shielding layer, and a first transparent electrode disposed on a side of the second passivation layer away from the substrate; a third passivation layer, provided on a side of the second passivation layer away from the substrate and covering the first transparent electrode; a fourth passivation layer, disposed on a side of the third passivation layer facing away from the substrate; The first contact hole sequentially penetrates the fourth passivation layer and the third passivation layer to expose the first transparent electrode, and the second contact hole sequentially penetrates the fourth passivation layer, the third passivation layer and the second passivation layer to expose the light-shielding layer, and the sum of the vertical distance between the light-shielding layer and the first transparent electrode and the thickness of the first transparent electrode is not greater than the thickness of the second passivation layer.

3. The array substrate according to claim 2, characterized in that: An etching rate of the first transparent electrode is lower than an etching rate of the second passivation layer and the third passivation layer.

4. The array substrate according to claim 2, characterized in that: The second transparent electrode is arranged on a side of the fourth passivation layer facing away from the substrate.

5. The array substrate according to claim 4, characterized in that: The shading layer includes a first metal part and a second metal part, and the first transparent electrode includes a first electrode part and a second electrode part; the first metal part and the second transparent electrode are connected through the second contact hole, the first electrode part and the second transparent electrode are connected through the first contact hole, and the second metal part and the second electrode part are aligned to form a first capacitor.

6. The array substrate according to claim 2, characterized in that: A third transparent electrode is disposed in the fourth passivation layer, and the third transparent electrode is at least partially aligned with the second transparent electrode to form a second capacitor.

7. The array substrate according to claim 4, characterized in that: A first transistor is provided in the driving device layer, and a third contact hole is opened in the pixel driving layer. The third contact hole penetrates the pixel driving layer and extends into the driving device layer. The third contact hole is used to expose one of the first source and the first drain of the first transistor, and the second transparent electrode is connected to one of the first source and the first drain of the first transistor through the third contact hole.

8. The array substrate according to claim 7, characterized in that: A second transistor is also provided in the driving device layer, the first transistor includes a first gate, the second transistor includes a second source, a second drain and a second gate, the first gate and the second gate are arranged on the same layer, and the first source or the first drain is arranged on the same layer as the second source and the second drain.

9. The array substrate according to any one of claims 2 to 8, characterized in that: The light-shielding layer includes a first light-shielding sub-layer, a second light-shielding sub-layer and an isolation layer. The first light-shielding sub-layer is arranged on a side of the first passivation layer facing away from the substrate, the isolation layer is arranged on a side of the first light-shielding sub-layer facing away from the substrate, the second light-shielding sub-layer is arranged on a side of the isolation layer facing away from the substrate, and the second contact hole penetrates the second light-shielding sub-layer and the isolation layer to expose at least a portion of the first light-shielding sub-layer.

10. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 9.

Images