Optoelectronic device

Abstract

Some embodiments described herein provide an optoelectronic device including a multi-layer photodiode structure. The multi-layer photodiode structure includes a stacked configuration of a plurality of sensing structures. By using a stacked configuration of multiple sensing structures, the quantum effect length is increased relative to another photodiode comprising a single layer photodiode structure. In addition, a lower sensing structure of the multi-layer sensing structure shares a substrate with an integrated circuit of the optoelectronic device. The lower sensing structure is electrically isolated from the integrated circuit by a doped isolation region adjacent a sidewall of the lower sensing structure.

Description

Technical Field

[0001] The present disclosure relates to an optoelectronic device. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices use light-sensitive CMOS circuits to convert light energy into electrical energy. The light-sensitive CMOS circuits may include a photodiode structure formed in a silicon substrate. When the photodiode structure is exposed to light, an electric charge (called a photocurrent) is induced in the photodiode structure. The photodiode structure may be coupled to a switching transistor for extracting the charge from the photodiode structure. Color may be determined by placing a filter on the light-sensitive CMOS circuit. Utility Model Content

[0003] The present disclosure provides an optoelectronic device, including a substrate and a multilayer photodiode structure. The multilayer photodiode structure includes a first sensing structure, a second sensing structure, an oxide layer, and a dielectric layer. The first sensing structure extends into the substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate. The second sensing structure is located on the first sensing structure. The oxide layer is located under the second sensing structure and is located on the first sensing structure. The dielectric layer is located on the oxide layer and is located under the second sensing structure.

[0004] The present disclosure also provides an optoelectronic device, including a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip below the first semiconductor chip. The first semiconductor chip includes a first substrate and a pixel sensor. The pixel sensor includes a multilayer photodiode structure. The multilayer photodiode structure includes a first sensing structure and a second sensing structure. The first sensing structure extends into the first substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the first substrate. The second sensing structure is located on the first sensing structure. The second semiconductor chip includes a second substrate and a logic integrated circuit on or in the second substrate.

[0005] The present disclosure further provides an optoelectronic device. The optoelectronic device includes a substrate and a multilayer photodiode structure. The multilayer photodiode structure includes a vertically arranged electromagnetic wave transmission region and the electromagnetic wave transmission region includes a first sensing structure, a second sensing structure, an oxide layer and a dielectric layer. The electromagnetic wave transmission region has a width approximately the same as that of the first sensing structure, the first sensing structure extends into the substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate. The second sensing structure is located on the first sensing structure and is included outside the electromagnetic wave transmission region. The oxide layer is located under the second sensing structure and is located on the first sensing structure. The dielectric layer is located on the oxide layer and is located under the second sensing structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when reading the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an exemplary environment in which the systems and / or methods of the present disclosure may be implemented;

[0008] Figure 2 is a schematic diagram of an exemplary semiconductor structure of the present disclosure;

[0009] Figure 3 is a schematic diagram of an exemplary semiconductor chip package of the present disclosure;

[0010] FIG. 4A to FIG. 4C is a schematic diagram of an exemplary embodiment of a multilayer photodiode structure of the present disclosure;

[0011] FIG. 5A to FIG. 5M is a schematic diagram of an exemplary embodiment of the present disclosure;

[0012] Figure 6 This disclosure is Figure 1 A schematic diagram of exemplary elements of one or more devices;

[0013] Figure 7 is a flow chart of an exemplary process associated with forming a multilayer photodiode structure of the present disclosure.

[0014]

Explanation of symbols

[0015] 100: Environment

[0016] 102: Tools

[0017] 104: Tools

[0018] 106: Tools

[0019] 108: Tools

[0020] 110: Tools

[0021] 112: Tools

[0022] 114: Tools

[0023] 116: Tools

[0024] 118: Tools

[0025] 200: Pixel array

[0026] 202: Pixel sensor

[0027] 202a: Pixel sensor

[0028] 202b: Pixel sensor

[0029] 202c: Pixel sensor

[0030] 202d: Pixel sensor

[0031] 300: Photoelectric device

[0032] 302a: Semiconductor device

[0033] 302b: Semiconductor device

[0034] 304:Joint interface

[0035] 306a: Contact

[0036] 306b: Contact

[0037] 308a: Dielectric region

[0038] 308b: Dielectric region

[0039] 310a: Metallization layer

[0040] 310b: Metallization layer

[0041] 312a:Substrate

[0042] 312b:Substrate

[0043] 314:Multilayer photodiode structure

[0044] 314a: Multilayer photodiode structure

[0045] 314b: Multilayer photodiode structure

[0046] 314c: Multilayer Photodiode Structure

[0047] 316a: Sensing structure

[0048] 316b: Sensing structure

[0049] 318a: Electromagnetic waves

[0050] 318b: Electromagnetic waves

[0051] 320a: doped isolation region

[0052] 320b: doped isolation region

[0053] 320c: doped isolation region

[0054] 322a: p-type region

[0055] 322b: p-type region

[0056] 324a: n-type region

[0057] 324b: n-type region

[0058] 326: Reflow polysilicon oxide material layer

[0059] 328: Interconnection Structure

[0060] 330: Etching stop layer

[0061] 332: Metallization layer

[0062] 334: Bonding pad

[0063] 336: Dielectric layer

[0064] 338: Microlens layer

[0065] 340:Logic IC

[0066] 400: Implementation Method

[0067] 402: Electromagnetic wave transmission area

[0068] 404: Oxide layer

[0069] 406: Dielectric layer

[0070] 408: bottom raised part

[0071] 410: epitaxial layer

[0072] 500: Implementation method

[0073] 502: Cavity

[0074] 504: Cavity pattern

[0075] 506: Photoresist layer

[0076] 508: Cavity pattern

[0077] 510: Photoresist layer

[0078] 512: Cavity pattern

[0079] 514: Photoresist layer

[0080] 516: Depression area

[0081] 518: Boundary

[0082] 520: Cavity

[0083] 522: Cavity pattern

[0084] 524: Photoresist layer

[0085] 526: Cavity pattern

[0086] 528: Photoresist layer

[0087] 530: Cavity pattern

[0088] 532: Photoresist layer

[0089] 600: Device

[0090] 610: Bus

[0091] 620: Processor

[0092] 630: Memory

[0093] 640: Input element

[0094] 650: Output element

[0095] 660: Communication element

[0096] 700: Craftsmanship

[0097] 705: Block

[0098] 710: Block

[0099] 715: Block

[0100] 720: Block

[0101] 725: Block

[0102] 730: Block

[0103] 735: Block

[0104] 740: Block

[0105] 745: Cube

[0106] 750: Block

[0107] D1: Thickness

[0108] D2: Thickness

[0109] D3: Width

[0110] D4: Width

[0111] D5: Depth

[0112] D6: Thickness DETAILED DESCRIPTION

[0113] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and compositions are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the subsequent description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0114] Additionally, spatially relative terms, such as "below," "beneath," "lower," "upper," "above," etc., may be used herein to facilitate description to describe the relationship of one element or feature to another element or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0115] In some cases, a complementary metal oxide semiconductor image sensor (CIS) device (e.g., an optoelectronic device) includes a photodiode in a first layer of a first semiconductor material and an integrated circuit in a second layer of a second semiconductor material. During the manufacturing process, the formation of the first layer of the first semiconductor material (including the photodiode) and the formation of the second layer of the second semiconductor material (including the integrated circuit) may each independently consume a certain amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources). In addition, in the optoelectronic device, the photodiode may include a pn junction in a layer of a quantum material such as germanium. Photons from light that enter the layer of the quantum material can be absorbed to produce electron-hole pairs, which are separated by an electric field across the pn junction to produce a current (e.g., photocurrent) that can be detected by the integrated circuit.

[0116] The thickness or length of the layer of quantum material is sometimes referred to as the "quantum length" and can affect the performance of the photodiode. For example, if the quantum length of the layer of quantum material is too short (e.g., the layer of quantum material is too thin), photons from light that enter the layer of quantum material may pass through the layer of quantum material without being absorbed, thereby reducing the sensitivity and / or energy conversion efficiency of the photodiode.

[0117] Some embodiments described herein provide an optoelectronic device including a multilayer photodiode structure. The multilayer photodiode structure includes a stacked configuration of multiple sensing structures formed of a quantum effect material (e.g., a germanium material). By using a stacked configuration of multiple sensing structures, the quantum effect length is increased relative to another photodiode including a single-layer photodiode structure.

[0118] In addition, the lower sensing structure of the multi-layer sensing structure can share a substrate with the integrated circuit of the optoelectronic device. The lower sensing structure is electrically isolated from the integrated circuit by a plurality of doped isolation regions adjacent to a plurality of sidewalls of the lower sensing structure. The amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to manufacture the optoelectronic device is reduced relative to another optoelectronic device including the lower sensing structure and the integrated circuit on separate substrates.

[0119] By increasing the quantum length, an optoelectronic device including a photodiode has improved performance relative to another optoelectronic device including a photodiode having a single layer of quantum effect material. In this way, the performance of the optoelectronic device in the target application and / or environment, the quality of the optoelectronic device, and the reliability of the optoelectronic device can be improved, thereby improving manufacturing yield and reducing field failure rate. This improvement in manufacturing yield and reduction in field failure rate can be further extended by combining the lower sensing structure and the integrated circuit on the substrate to achieve resource conservation.

[0120] Figure 1 1 is a schematic diagram of an exemplary environment 100 in which the systems and / or methods of the present disclosure may be implemented. Figure 1 As shown, the environment 100 may include multiple semiconductor process tools 102 to 116 and a wafer / wafer transport tool 118. The multiple semiconductor process tools 102 to 116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, a bonding / debonding tool 116 and / or other types of semiconductor process tools. The tools included in the exemplary environment 100 may be included in examples such as a semiconductor clean room, a semiconductor foundry, a semiconductor process facility and / or a manufacturing facility.

[0121] The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool that can deposit a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other type of PVD tool. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102 .

[0122] The exposure tool 104 is a semiconductor process tool that can expose the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from the mask to the photoresist layer. The pattern may include a pattern of one or more semiconductor device layers for forming one or more semiconductor devices, may include a pattern of one or more structures for forming a semiconductor device, may include a pattern for etching various parts of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0123] The developing tool 106 is a semiconductor process tool capable of developing the photoresist layer exposed to the radiation source to form a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed or unexposed portion of the photoresist layer using a chemical developer.

[0124] The etching tool 108 is a semiconductor process tool that can etch various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, and may include using ionized gas to etch one or more portions isotropically or directionally.

[0125] The planarization tool 110 is a tool for semiconductor processes that can polish or planarize individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool to polish or planarize a layer or surface of a deposited or plated material. The planarization tool 110 can polish or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool 110 can use abrasive and corrosive chemical slurries in combination with a polishing pad and a retaining ring (e.g., typically larger in diameter than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and fixed in place by a retaining ring. The dynamic polishing head can rotate with different rotation axes to remove material and homogenize any irregular topography on the semiconductor device so that the semiconductor device is flat or level.

[0126] The electroplating tool 112 is a semiconductor processing tool that is capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0127] The ion implantation tool 114 is a semiconductor process tool that can implant ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided to the arc chamber, and an arc voltage is discharged between a cathode and an anode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed to the substrate so that the ions are implanted below the surface of the substrate.

[0128] The bonding / debonding tool 116 is a tool for a semiconductor process that is capable of bonding two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, the bonding / debonding tool 116 may include a eutectic bonding tool that is capable of forming a eutectic bond between two or more wafers. In these examples, the bonding / debonding tool 116 may heat two or more wafers to form a eutectic system between the materials of the two or more wafers. As another example, the bonding / debonding tool 116 may include a hybrid bonding tool, a direct bonding tool, and / or other types of bonding tools. In some embodiments, the bonding / debonding tool 116 may heat two or more wafers to separate the two or more wafers.

[0129] The wafer / wafer transport tool 118 may be included in an integrated tool or other type of tool including multiple process chambers, and may be configured to transport substrates and / or semiconductor devices between multiple process chambers, to transport substrates and / or semiconductor devices between process chambers and buffers; to transport substrates and / or semiconductor devices between process chambers and interface tools (such as equipment front end modules (EFEM)); and / or to transport substrates and / or semiconductor devices between process chambers and transport carriers (e.g., front opening unified pods (FOUPs)), etc. In some embodiments, the wafer / wafer transport tool 118 may be included in a multi-chamber (or integrated) deposition tool 102 to include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidations, and / or other types of contamination or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0130] One or more semiconductor process tools 102 to tools 116 and / or wafer / wafer transport tools 118 can perform a series of one or more semiconductor process operations described herein. In some embodiments, and by way of example, the series of one or more semiconductor process operations includes forming an oxide layer on a substrate. The series of one or more semiconductor process operations includes forming a first cavity through the oxide layer to enter the substrate. The series of one or more semiconductor process operations includes forming a first sensing structure in the first cavity. The series of one or more semiconductor process operations includes forming an isolation region adjacent to the sidewall of the first sensing structure. The series of one or more semiconductor process operations includes forming a p-type region in the first sensing structure. The series of one or more semiconductor process operations includes forming an n-type region in the first sensing structure. The series of one or more semiconductor process operations includes forming a dielectric layer on the first sensing structure. The series of one or more semiconductor process operations includes forming a recessed region within the dielectric layer. The series of one or more semiconductor process operations includes forming a second cavity through the dielectric layer within the recessed region and through the oxide layer. The sequence of one or more semiconductor process operations includes forming a second sensing structure located on the recessed area and including a bottom protrusion filling the second cavity to connect with the substrate, wherein forming the second sensing structure includes forming the second sensing structure above the first sensing structure. In some embodiments, among other examples, the one or more semiconductor process operations performed by the semiconductor process tool 102 to the tool 116 and / or the wafer / wafer transport tool 118 may correspond to FIG. 5A to FIG. 5M and one or more semiconductor process operations described elsewhere herein.

[0131] Figure 1 The number and configuration of devices shown are provided as one or more examples. In embodiments, there may be Figure 1 Other devices, fewer devices, different devices, or differently arranged devices than those shown. In addition, Figure 1 Two or more of the devices shown may be implemented in a single device, or Figure 1 The single device shown may be implemented as multiple separate devices. Additionally or alternatively, one or more devices in the exemplary environment 100 may perform one or more functions performed by another set of devices in the exemplary environment 100.

[0132] Figure 2 2 shows a top-down view of the pixel array 200. Figure 2 As shown, the pixel array 200 may include a plurality of pixel sensors 202. Figure 2 As further shown in FIG. 1 , the pixel sensors 202 can be arranged in a grid. In some embodiments, the pixel sensors 202 are square (e.g., Figure 2 In some embodiments, the pixel sensor 202 includes other shapes, such as a circle, an octagon, a diamond, and / or other shapes.

[0133] The pixel sensor 202 may be configured to sense and / or accumulate incident light (e.g., light directed toward the pixel array 200). For example, the pixel sensor 202 may absorb and accumulate photons of the incident light in a photodiode structure. The photons accumulated in the photodiode structure may generate a charge corresponding to the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a larger intensity or brightness, while a lower amount of charge may correspond to a lower intensity or brightness).

[0134] Pixel array 200 may be electrically connected to a back-end-of-line (BEOL) metal stack (not shown) of an image sensor. The BEOL metal stack may electrically connect pixel array 200 to a control circuit for measuring the accumulation of incident light in pixel sensor 202 and converting the measurement result into an electrical signal.

[0135] As combined Figures 3 to 7As described in more detail elsewhere herein, the pixel sensor 202 may include a combination of light wave filters (e.g., light wave filters for filtering light having a target wavelength). For example, when using light wave filters, the pixel sensor 202a may include a multilayer photodiode structure that senses red visible light (e.g., electromagnetic waves having wavelengths included in the range of about 620 nanometers to about 750 nanometers). Additionally, or alternatively, the pixel sensor 202b may include a multilayer photodiode structure that senses blue visible light (e.g., electromagnetic waves having wavelengths included in the range of about 450 nanometers to about 495 nanometers). Additionally, or alternatively, the pixel sensor 202c may include a multilayer photodiode structure that senses green visible light (e.g., electromagnetic waves having wavelengths included in the range of about 495 nanometers to about 570 nanometers). Additionally, or alternatively, the pixel sensor 202d may include a multilayer photodiode structure that senses near infrared (NIR) light (e.g., electromagnetic waves having wavelengths included in the range of about 750 nanometers to about 2500 nanometers).

[0136] As mentioned above, Figure 2 Provided as an example. Other examples may be Figure 2 Described differently.

[0137] Figure 3 is a schematic diagram of an exemplary optoelectronic device 300 described herein. In some embodiments, optoelectronic device 300 corresponds to a three-dimensional complementary metal oxide semiconductor image sensor (3DCIS) device, wherein semiconductor device 302a and semiconductor device 302b are stacked and / or vertically arranged. Figure 3 As shown, semiconductor device 302a (e.g., photonic semiconductor wafer) and semiconductor device 302b (e.g., complementary metal oxide semiconductor (CMOS) wafer) are connected via bonding interface 304. Bonding interface 304 may include contact 306a and contact 306b connected via eutectic bonding. Contact 306a and contact 306b may include an alloy having aluminum-copper (Al-Cu) alloy, aluminum-germanium (Al-Ge) alloy, or copper-tin (Cu-Sn) alloy material, etc.

[0138] like Figure 3 As further shown in FIG. 1 , the semiconductor device 302 a may include a dielectric region 308 a. The dielectric region 308 a (eg, an intermetallic dielectric region) may include one or more layers of dielectric material (eg, iron oxide (Fe x O y ) materials, zinc oxide (ZnO) materials, silicon oxide (SiO x) materials, silicon nitride (Si x N y ) material, silicon oxynitride (SiON) material, tetraethoxysilane oxide material, phosphosilicate glass (PSG) material, borophosphosilicate glass (BPSG) material, fluorinated silica glass (FSG) material, carbon-doped silicon oxide material or other dielectric material). One or more metallization layers 310a can be formed in the layers and / or between the layers of the dielectric region 308a. The metallization layer 310a may include bonding pads, wires and / or other types of conductive structures to electrically connect various regions of the semiconductor device 302a and / or to electrically connect various regions of the optoelectronic device 300 to one or more external devices and / or external packages. In some embodiments, the metallization layer 310a may be referred to as a metal stack of the BEOL and may include a conductive material such as gold, copper, silver, cobalt, tungsten, a metal alloy or a combination thereof.

[0139] The semiconductor device 302a may further include a substrate 312a. In some embodiments, the substrate 312a includes a semiconductor material, such as a silicon material (Si) or a gallium arsenide (GaAs) material. In some embodiments, the substrate 312a includes a dielectric material, such as an oxide material. Additionally or alternatively, in some embodiments, the substrate 312a corresponds to a silicon-on-insulator structure (e.g., an SOI structure).

[0140] like Figure 3 As shown in the detailed view of , semiconductor device 302a includes a multilayer photodiode structure 314. Multilayer photodiode structure 314 can be included as part of pixel sensor 202, and multilayer photodiode structure 314 includes a plurality of sensing structures, including sensing structure 316a (e.g., a lower sensing structure) and sensing structure 316b (e.g., a sensing structure on sensing structure 316a). Sensing structure 316a and sensing structure 316b can each be formed of a quantum effect material, such as a germanium (Ge) material, a silicon germanium (SiGe) material, a Group III material, a Group V material, or other suitable quantum effect material. In some embodiments, sensing structure 316a and sensing structure 316b include the same quantum effect material. In some embodiments, sensing structure 316a and sensing structure 316b each include different quantum effect materials.

[0141] As combined FIG. 5A to FIG. 5MAs described in more detail, the quantum effect material of the sensing structure 316a and / or the sensing structure 316b can be formed using a selective epitaxial growth process after forming cavities and / or recesses in the substrate 312a (and / or other layers of the multilayer photodiode structure 314) using lithography and etching processes. However, other formation techniques may be used (e.g., formed by a direct epitaxial growth process, formed after surface processing of the substrate 312a and / or other layers of the multilayer photodiode structure 314a).

[0142] like Figure 3 As shown in the detailed view of FIG. 3 , electromagnetic wave 318a and electromagnetic wave 318b (eg, light waves) are illustrated as passing through multilayer photodiode structure 314. Electromagnetic wave 318a passes through sensing structure 316a. Within multilayer photodiode structure 314, the quantum length of electromagnetic wave 318a corresponds to the thickness D1 of sensing structure 316a.

[0143] In addition, electromagnetic wave 318b passes through sensing structure 316b. In multilayer photodiode structure 314, the quantum length of electromagnetic wave 318b corresponds to thickness D2 of sensing structure 316b. Therefore, the effective quantum length of multilayer photodiode structure 314 for electromagnetic wave 318a and electromagnetic wave 318b (e.g., thickness D1+thickness D2) is increased relative to another photodiode structure including another sensing structure formed of a single layer of quantum material.

[0144] As such, the performance (e.g., sensitivity) of the optoelectronic device 300 including the multilayer photodiode structure 314 is improved compared to other optoelectronic devices including a photodiode structure formed of a single layer of quantum effect material. By improving the performance of the optoelectronic device 300, the quality and reliability of the optoelectronic device 300 in the target application and / or environment can be improved to improve manufacturing yield and reduce field failure rate. Improving manufacturing yield and reducing field failure rate can reduce the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor and / or computing resources) required to support the optoelectronic device 300 in the consumer market.

[0145] The thickness ranges of the sensing structures 316a and 316b can be similar. For example, in some embodiments, the thickness D1 and the thickness D2 are each included in the range of about 2 microns to about 10 microns.

[0146] In some embodiments, the thickness D2 is small relative to the thickness D1. Additionally or alternatively, the ratio of the thickness D2:thickness D1 may be included in the range of about 1:2 to about 1:1. If the ratio of the thickness D2:thickness D1 is included in the range of about 1:2 to about 1:1, the effective quantum length of the multilayer photodiode structure 314 may be sufficiently extended to meet a threshold of quantum effect performance (e.g., a threshold of sensitivity for the optoelectronic device 300). Additionally or alternatively, if the ratio of the thickness D2:thickness D1 is in the range of about 1:2 to about 1:1, the size of the multilayer photodiode structure 314 may be such that the multilayer photodiode structure 314 spatially matches other integrated circuits included in the optoelectronic device 300. Additionally or alternatively, if the ratio of the thickness D2:thickness D1 is in the range of about 1:2 to about 1:1, the cost of the optoelectronic device 300 may be feasible. If the ratio of the thickness D2:thickness D1 is less than about 1:2, the effective quantum length of the multilayer photodiode structure 314 may not be sufficiently extended to meet the threshold of quantum effect performance. If the ratio of thickness D2:thickness D1 is greater than about 1:1, the cost and / or efficiency of manufacturing optoelectronic device 300 may increase. Additionally, or alternatively, if the ratio of thickness D2:thickness D1 is greater than about 1:1, the size of multilayer photodiode structure 314 may be such that multilayer photodiode structure 314 does not spatially match other integrated circuits included in optoelectronic device 300. However, other values ​​and ranges of thickness D1, thickness D2, and the ratio of thickness D2:thickness D1 are also within the scope of the present disclosure.

[0147] The semiconductor device 302a may include additional features, such as a fixed lens or an adjustable lens, to focus and / or diverge electromagnetic waves (e.g., electromagnetic waves 318a, electromagnetic waves 318b, and / or other similar electromagnetic waves) between sensing structures (e.g., sensing structure 316a, sensing structure 316b, and / or other similar sensing structures) to adjust or enhance the performance of the multilayer photodiode structure 314. Focusing and / or diverging the electromagnetic waves may include focusing and / or diverging the electromagnetic waves to pass through the center of the sensing structure or the edge of the sensing structure, etc.

[0148] exist Figure 3 Detailed view, and as combined Figure 5E and Figure 5J As described in more detail, dopants can be implanted into the multilayer photodiode structure 314 to form one or more doped isolation regions 320a. As shown, the doped isolation regions 320a are adjacent to the sidewalls of the sensing structure 316a and extend into the substrate 312a to a depth that is greater than the thickness D1 of the sensing structure 316a. In some embodiments, the doped isolation regions 320a can merge with the sidewalls of the sensing structure 316a.

[0149] In addition, if Figure 3 As shown in the detailed view of FIG. 3 , the sensing structure 316 a includes a region that forms a pn junction or a pin junction (e.g., a junction between a p-type region 322 a, an intrinsic (or undoped) region, and an n-type region 324 a). Fig. 5F and Figure 5G As described in more detail, the sensing structure 316a can be doped with a p-type dopant to form a p-type region 322a and doped with an n-type dopant to form an n-type region 324a. Additionally, or alternatively, and as in combination with Figure 5K and Figure 5L As described in greater detail, the sensing structure 316 b may be doped with a p-type dopant to form a p-type region 322 b and with an n-type dopant to form an n-type region 324 b .

[0150] Doped isolation region 320a can reduce the potential for current leakage between integrated circuits that may be included in semiconductor device 302a and sensing structure 316a (e.g., a pn junction or a pin junction of sensing structure 316a). As such, the performance of sensing structure 316a (and multi-layer photodiode structure 314) can be improved relative to another semiconductor device including a similar sensor structure without electrical isolation.

[0151] In addition, electrically isolating the sensing structure 316a enables the sensing structure 316a and the additional integrated circuit to be formed using a common substrate (e.g., substrate 312a). In this way, the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to manufacture the optoelectronic device 300 can be reduced relative to using separate substrates for the sensing structure 316a and the additional integrated circuit.

[0152] like Figure 3 As shown in the detailed view of , the multilayer photodiode structure 314 may include additional structures and / or layers. For example, the multilayer photodiode structure 314 may include a layer 326 of reflowed poly-silicon oxide (RPO) material for insulation purposes. Additionally or alternatively, the multilayer photodiode structure 314 may include one or more interconnect structures 328, such as one or more vertical interconnects formed of a conductive material such as cobalt (Co). Additionally or alternatively, the multilayer photodiode structure 314 may include an etch stop layer 330 including a silicon nitride (SiN) material or the like.

[0153] In some embodiments, the multi-layer photodiode structure 314 can be connected to one or more metallization layers 332 located above the multi-layer photodiode structure 314. The metallization layer 332 can include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof.

[0154] like Figure 3 As shown, semiconductor device 302a includes bonding pad 334. Bonding pad 334 can contact one or more metallization layers 310a in dielectric region 308a. Bonding pad 334 can include conductive material, such as gold, silver, aluminum, copper, aluminum copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, metal alloy, other metal or combination thereof. Bonding pad 334 can provide electrical connection between metallization layer 310a of optoelectronic device 300 and external device and / or external package.

[0155] In some embodiments, Figure 3 As shown, semiconductor device 302a includes a dielectric layer 336 above multi-layer photodiode structure 314. In some embodiments, dielectric layer 336 includes a material such as titanium nitride (TiN) or an oxide such as silicon dioxide (SiO 2 ) material. In some embodiments, a portion of the dielectric layer 336 is included as part of a color filter array (CFA) structure. Additionally or alternatively, in some embodiments, a portion of the dielectric layer 336 is included as part of a hard mask (HM) structure.

[0156] like Figure 3 As further shown in FIG. 3 , microlens layer 338 is included above and / or on dielectric layer 336. Microlens layer 338 may include a plurality of microlenses. In particular, microlens layer 338 may include microlenses that each correspond to a pixel sensor in the pixel sensor array (e.g., each pixel sensor 202 included in pixel array 200).

[0157] like Figure 3 As further shown in FIG. 1 , the semiconductor device 302 b may include a dielectric region 308 b. The dielectric region 308 b (eg, an intermetallic dielectric region) may include one or more layers of dielectric material (eg, silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), tetraethoxysilane oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide or other dielectric materials). One or more metallization layers 310b can be formed in the dielectric region 308b and / or between its layers. The metallization layer 310b may include bonding pads, wires and / or other types of conductive structures to electrically connect various regions of the semiconductor device 302b and / or to electrically connect various regions of the optoelectronic device 300 to one or more external devices and / or external packages. In some embodiments, the metallization layer 310b may be referred to as a metal stack of the BEOL and may include a conductive material such as gold, copper, silver, cobalt, tungsten, a metal alloy or a combination thereof.

[0158] The semiconductor device 302b may further include a substrate 312b. In some embodiments, the substrate 312b includes a semiconductor material such as a silicon (Si) material or a gallium arsenide (GaAs) material. Figure 3 As further shown in FIG. 3 , semiconductor device 302b includes logic integrated circuit 340 within or on substrate 312b. In some embodiments, logic integrated circuit 340 is electrically connected to multilayer photodiode structure 314 via bonding interface 304 (eg, via contacts 306a and 306b).

[0159] like Figure 3 As shown, a device (e.g., optoelectronic device 300) includes a first semiconductor wafer (e.g., semiconductor device 302a), the first semiconductor wafer includes a first substrate (e.g., substrate 312a) and a pixel sensor (e.g., pixel sensor 202), wherein the pixel sensor includes a multilayer photodiode structure (e.g., multilayer photodiode structure 314). The multilayer photodiode structure includes a first sensing structure (e.g., sensing structure 316a) extending to the first substrate, the first sensing structure includes a first quantum effect material and has a sidewall adjacent to a doped isolation region (e.g., doped isolation region 320a) in the first substrate. The multilayer photodiode structure includes a second sensing structure (e.g., sensing structure 316b) located above the first sensing structure, and the second sensing structure includes a second quantum effect material. The device includes a second semiconductor wafer (e.g., semiconductor device 302b) located below the first semiconductor wafer and connected to the first semiconductor wafer. The second semiconductor wafer includes a second substrate (e.g., substrate 312b) and a logic integrated circuit (e.g., logic integrated circuit 340) on or within the second substrate.

[0160] although Figure 3 The optoelectronic device 300 corresponds to a stacked device (eg, semiconductor device 302a is stacked on semiconductor device 302b), but is different from Figure 3The described related structures and / or features may be included in other types of optoelectronic devices (frontside illumination sensor (FSI) devices or backside illumination sensor (BSI) devices, etc.).

[0161] As mentioned above, Figure 3 Provided as an example. Other examples may be related to Figure 3 Described differently.

[0162] FIG. 4A to FIG. 4C is a schematic diagram of an exemplary embodiment 400 of a multilayer photodiode structure described herein. The multilayer photodiode structure may correspond to Figure 3 and the multilayer photodiode structure 314 described elsewhere herein. FIG. 4A to FIG. 4C Different configurations of the multilayer photodiode structure 314 are shown relative to an EM wave transmissive region 402 (eg, EM wave transmissive regions of EM wave 318a and EM wave 318b) that includes the sensing structure 316a and has approximately the same width as the sensing structure 316a.

[0163] exist Figure 4A In the multi-layer photodiode structure 314a, the electromagnetic wave transmission region 402 includes a sensing structure 316a (eg, a first sensing structure). Figure 4A As shown, the sensing structure 316 b (eg, the second sensing structure) located above the sensing structure 316 a is included outside the electromagnetic wave transmitting region 402 .

[0164] like Figure 4AAs further shown in FIG. 4 , the electromagnetic wave transmission region 402 and the sensing structure 316a have approximately the same width D3. As an example, the width D3 may be included in the range of about 1 micron to about 10 microns. If the width D3 is in the range of about 1 micron to about 10 microns, the electromagnetic wave transmission region 402 may provide a sufficient width to detect electromagnetic waves (e.g., electromagnetic waves 318a and electromagnetic waves 318b) to improve the performance of the multilayer photodiode structure 314a. In addition, or alternatively, if the width D3 is in the range of about 1 micron to about 10 microns, the size of the multilayer photodiode structure 314 may keep the size (and cost) of the optoelectronic device (e.g., optoelectronic device 300) including the multilayer photodiode structure 314 within a feasible range. If the width D3 is less than about 1 micron, the sensing structure 316a and / or the electromagnetic wave transmission region 402 may have an area that is insufficient to detect electromagnetic waves (e.g., electromagnetic waves 318a and electromagnetic waves 318b), and thus reduce the performance of the multilayer photodiode structure 314a. If width D3 is greater than about 10 microns, the size (and cost) of an optoelectronic device (eg, optoelectronic device 300) including multilayer photodiode structure 314a may increase. However, other values ​​and ranges of width D3 are also within the scope of the present disclosure.

[0165] like Figure 4A As shown, the sensing structure 316a extends into the substrate 312a, and the doped isolation region 320a (e.g., the first doped isolation region) is adjacent to the sidewalls of the sensing structure 316a. In some embodiments, the doped isolation region 320a can merge with and / or contact the sidewalls of the sensing structure 316a. The p-type region 322a (e.g., the first p-type region) and the n-type region 324a (e.g., the first n-type region) can form a junction (e.g., a pn or pin junction) within the sensing structure 316a.

[0166] The multilayer photodiode structure 314a includes an oxide layer 404 located below the sensing structure 316b and above the sensing structure 316a. The oxide layer 404 may include silicon dioxide (SiO 2 ) materials, etc.

[0167] In addition, the multi-layer photodiode structure 314a includes a dielectric layer 406 (eg, a first dielectric layer) on the oxide layer 404. The dielectric layer 406 may include a silicon nitride (SiN) material or the like.

[0168] like Figure 4A As further shown in FIG. 4 , sensing structure 316 b includes a bottom protrusion 408 extending downward through dielectric layer 406 , through oxide layer 404 and extending to substrate 312 a . Fig.5I and Figure 5JAs described in more detail, bottom protrusion 408 may be formed during an epitaxial growth operation that forms sensing structure 316b within a cavity through dielectric layer 406 and through oxide layer 404. P-type region 322b (second p-type region) and n-type region 324b (e.g., second n-type region) may form a junction (e.g., a pn or pin junction) within sensing structure 316b.

[0169] like Figure 4B The multilayer photodiode structure 314b (the second exemplary embodiment) is shown in FIG. Figure 4A In contrast to the multilayer photodiode structure 314a, the sensing structure 316b extends laterally to the electromagnetic wave transmission region 402 and includes a doped isolation region 320b (eg, a second doped isolation region). Figure 4B As shown, the doped isolation region 320 b is located within the electromagnetic wave transmission region 402 .

[0170] Multilayer photodiode structure 314b may meet another different performance range (e.g., a range defined by a lower sensitivity limit and an upper sensitivity limit) than the performance range associated with multilayer photodiode structure 314a. Additionally or alternatively, the effective quantum length of multilayer photodiode structure 314b may be different from the effective quantum length associated with multilayer photodiode structure 314a. Additionally or alternatively, the electrical isolation characteristics (e.g., leakage characteristics) of multilayer photodiode structure 314b may be different from the electrical isolation characteristics of multilayer photodiode structure 314a.

[0171] like Figure 4C The multilayer photodiode structure 314c (the third exemplary embodiment) is shown in FIG. Figure 4A The multilayer photodiode structure 314a and Figure 4B Compared to the multilayer photodiode structure 314b, the epitaxial layer 410 is included as part of the multilayer photodiode structure 314c. The epitaxial layer 410 (e.g., a layer of silicon (Si) material, etc.) may include additional integrated circuits. In some embodiments, the epitaxial layer 410 includes a doped isolation region 320c (e.g., a third isolation region).

[0172] In addition, if Figure 4C As shown, the doped isolation regions 320c can be dispersed between one or more sensing structures 316b at intervals. The electrical isolation characteristics of the multilayer photodiode structure 314c can be different from the isolation characteristics of the multilayer photodiode structure 314a and / or the multilayer photodiode structure 314b. In addition, the isolation characteristics of the multilayer photodiode structure 314c can be adjusted based on the arrangement or position of the doped isolation regions 320a, the doped isolation regions 320b, and / or the doped isolation regions 320c.

[0173] In some embodiments, the concentration of dopants in doped isolation region 320a, doped isolation region 320b, and / or doped isolation region 320c can vary vertically. Additionally or alternatively, the concentration of dopants in doped isolation region 320a, doped isolation region 320b, and / or doped isolation region 320c can vary within a device (e.g., optoelectronic device 300) based on the design of a pixel sensor associated with multilayer photodiode structure 314 (e.g., pixel sensor 202a, pixel sensor 202b, pixel sensor 202c, or pixel sensor 202d associated with multilayer photodiode structure 314).

[0174] As combined Figure 3 and FIG. 4A to FIG. 4C As described, in some embodiments, an optoelectronic device (e.g., optoelectronic device 300) includes a substrate (e.g., substrate 312a). The optoelectronic device includes a multilayer photodiode structure (e.g., multilayer photodiode structure 314), and the multilayer photodiode structure includes a first sensing structure (e.g., sensing structure 316a). The first sensing structure extends into the substrate, includes a first quantum effect material, and has a sidewall adjacent to a doped isolation region (e.g., doped isolation region 320a) in the substrate. The multilayer photodiode structure includes a second sensing structure (e.g., sensing structure 316b) located above the first sensing structure, and the second sensing structure includes a second quantum effect material. The multilayer photodiode structure includes an oxide layer (e.g., oxide layer 404) located below the second sensing structure and above the first sensing structure. The multilayer photodiode structure includes a dielectric layer (e.g., dielectric layer 406) located above the oxide layer and below the second sensing structure.

[0175] As mentioned above, FIG. 4A to FIG. 4C Provided as an example. Other examples may be FIG. 4A to FIG. 4C The description is different.

[0176] FIG. 5A to FIG. 5M is a schematic diagram of an example implementation 500 described herein. The implementation 500 may include Figure 1 A series of one or more semiconductor process operations performed by one or more semiconductor process tools 102 to tools 116 and / or wafer / wafer transport tools 118.

[0177] like Figure 5A As shown, oxide layer 404 is formed on and / or over substrate 312a. Deposition tool 102 may be used in PVD operations, ALD operations, CVD operations, epitaxy operations, oxidation operations, and Figure 1The oxide layer 404 (or another suitable dielectric material) may be deposited in other types of deposition operations and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the oxide layer 404 after the oxide layer is deposited.

[0178] As an example, in some embodiments, oxide layer 404 has a thickness of up to about 1 micron. However, other values ​​and ranges of thickness are also within the scope of the present disclosure.

[0179] like Figure 5B As shown, the cavity 502 is formed through the oxide layer 404 and into the substrate 312a. In some embodiments, the pattern of the photoresist layer is used to etch the oxide layer 404 and the substrate 312a to form the cavity 502. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the oxide layer 404. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove a portion of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the oxide layer 404 and the substrate 312a based on the pattern to form the cavity 502. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique when etching the oxide layer 404 and the substrate 312a based on the pattern.

[0180] As an example, in some embodiments, cavity 502 has a width of up to about 10 microns and a depth of up to about 10 microns. However, other values ​​and ranges of width and depth are also within the scope of the present disclosure.

[0181] like Figure 5C As shown, sensing structure 316a is formed above and / or on substrate 312a (eg, within cavity 502). Deposition tool 102 may be used in epitaxial operations, with Figure 1 The quantum effect material is deposited in another type of deposition operation and / or another suitable deposition operation to form the sensing structure 316a.

[0182] like Figure 5D As shown, the sensing structure 316a is planarized. The planarization tool 110 can be used to planarize the sensing structure 316a using a CMP operation. Figure 1 Another type of planarization operation and / or another planarization operation is related to planarizing the sensing structure 316a. In some embodiments, planarizing the sensing structure 316a includes removing a portion of the oxide layer 404.

[0183] like Figure 5E As shown, the doped isolation region 320a is formed in the substrate 312a. In some embodiments, the cavity pattern 504 of the photoresist layer 506 is used to define the doped isolation region 320a. In these embodiments, the deposition tool 102 can be used to form the photoresist layer 506 on the oxide layer 404. The exposure tool 104 can be used to expose the photoresist layer 506 to a radiation source to pattern the photoresist layer 506. The development tool 106 can be used to develop and remove a portion of the photoresist layer 506 to form the cavity pattern 504. After the cavity pattern 504 is formed, the ion implantation tool 114 can be used to implant ions (boron (B) ions, etc.) into the substrate 312a to dope the substrate 312a and form the doped isolation region 320a. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer 506 (for example, using a chemical stripper, plasma ashing and / or another technique).

[0184] like Fig. 5F As shown, a p-type region 322a is formed in the sensing structure 316a. In some embodiments, a cavity pattern 508 of the photoresist layer 510 is used to define the p-type region 322a. In these embodiments, a deposition tool 102 may be used to form the photoresist layer 510 on the oxide layer 404 and the sensing structure 316a. An exposure tool 104 may be used to expose the photoresist layer 510 to a radiation source to pattern the photoresist layer 510. A development tool 106 may be used to develop and remove a portion of the photoresist layer 510 to form a cavity pattern 508. After forming the cavity pattern 508, an ion implantation tool 114 may be used to implant ions (gallium (Ga), aluminum (Al) or indium (In) ions, etc.) into the sensing structure 316a to dope the sensing structure 316a and form the p-type region 322a. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer 510 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0185] like Figure 5GAs shown, n-type region 324a is formed in sensing structure 316a. In some embodiments, cavity pattern 512 of photoresist layer 514 is used to define n-type region 324a. In these embodiments, deposition tool 102 can be used to form photoresist layer 514 on oxide layer 404 and sensing structure 316a. Exposure tool 104 can be used to expose photoresist layer 514 to a radiation source to pattern photoresist layer 514. Development tool 106 can be used to develop and remove a portion of photoresist layer 514 to form cavity pattern 512. After forming cavity pattern 512, ion implantation tool 114 can be used to implant ions (phosphorus (P), arsenic (As) or antimony (Sb) ions, etc.) into sensing structure 316a to dope sensing structure 316a and form n-type region 324a. In some embodiments, photoresist removal tool can be used to remove the remaining portion of photoresist layer 514 (e.g., using chemical stripper, plasma ashing and / or another technique).

[0186] like Figure 5H As shown, dielectric layer 406 is formed on and / or over oxide layer 404. Deposition tool 102 may be used in PVD operations, ALD operations, CVD operations, epitaxy operations, oxidation operations, and Figure 1 The dielectric layer 406 may be deposited in another type of deposition operation and / or another suitable deposition operation. In some embodiments, the planarization tool 110 may be used to planarize the dielectric layer 406 after the dielectric layer 406 is deposited.

[0187] By way of example, in some embodiments, dielectric layer 406 has a thickness of up to about 2 microns. However, other values ​​and ranges of thickness are also within the scope of the present disclosure.

[0188] like Fig.5I As shown, a recessed region 516 is formed in the dielectric layer 406. In some embodiments, the pattern of the photoresist layer is used to etch the dielectric layer 406 to form the recessed region 516. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the dielectric layer 406. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove a portion of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric layer 406 based on the pattern to form a groove in the dielectric layer 406. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a tool for photoresist removal can be used to remove the remaining portion of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etching the dielectric layer 406 based on the pattern.

[0189] In some embodiments ( Figure 4B In the multilayer photodiode structure 314b, etc., as Fig.5I As shown, the recessed region 516 extends through a boundary 518 corresponding to the outer edge of the sensing structure 316a, so that the recessed region 516 overlaps the sensing structure 316a. Figure 4A The recessed region 516 is near the boundary 518 such that no portion of the recessed region 516 overlaps with the sensing structure 316a.

[0190] like Fig.5I , a cavity 520 is formed in the recessed area 516 through the dielectric layer 406 and through the oxide layer 404 to the substrate 312a. In some embodiments, the pattern of the photoresist layer is used to etch the dielectric layer 406 and the oxide layer 404 to form the cavity 520. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the dielectric layer 406. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove a portion of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric layer 406 and the oxide layer 404 based on the pattern to form the cavity 520. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of dielectric layer 406 and oxide layer 404 .

[0191] In some implementations, the cavity 520 can be formed to have a width D4 included in the range of about 0.1 microns to about 1.0 microns. Additionally, or alternatively, the cavity 520 can be formed to have a depth D5 included in the range of about 0.1 microns to about 1.0 microns. If the width D4 and / or the depth D5 are in the range of about 0.1 microns to about 1.0 microns, the volume of the cavity 520 may be sufficient to cause epitaxial growth of a quantum effect material for another sensing structure (e.g., sensing structure 316b). Additionally, or alternatively, the aspect ratio of the cavity 520 can reduce defects (e.g., peeling, voids) within the quantum effect material. If the cavity 520 has a width D4 and / or a depth D5 less than about 0.1 microns, the volume of the cavity 520 may be insufficient to cause epitaxial growth of a quantum effect material for other sensing structures. If cavity 520 has a width D4 and / or depth D5 greater than about 1.0 micrometer, the aspect ratio of cavity 520 may cause defects (e.g., delamination, voids) within the quantum effect material. However, other values ​​and ranges of width D4 and depth D5 are also within the scope of the present disclosure.

[0192] like Figure 5J As shown, sensing structure 316b is formed above and / or on dielectric layer 406 (eg, within recessed region 516). Deposition tool 102 may be used in epitaxial operations, with Figure 1 The quantum effect material is deposited in another type of deposition operation and / or another suitable deposition operation to form the sensing structure 316b. Figure 5J As shown, forming the sensing structure 316b includes forming the bottom raised portion 408 (eg, within the cavity 520). The bottom raised portion 408 may have similar dimensions to the cavity 520 (eg, width D4 and depth D5).

[0193] exist Figure 5J In the embodiment of the present invention, the sensing structure 316b can be flat. The planarization tool 110 can be used to perform a CMP operation, Figure 1 Another type of planarization operation and / or another planarization operation is related to planarizing the sensing structure 316 b .

[0194] In addition, if Figure 5J As shown, a doped isolation region 320b is formed in the sensing structure 316b. In some embodiments, a cavity pattern 522 of a photoresist layer 524 is used to define the doped isolation region 320b. In these embodiments, a deposition tool 102 may be used to form a photoresist layer 524 on the sensing structure 316b and / or the dielectric layer 406. An exposure tool 104 may be used to expose the photoresist layer 524 to a radiation source to pattern the photoresist layer 524. A development tool 106 may be used to develop and remove a portion of the photoresist layer 524 to form a cavity pattern 522. After forming the cavity pattern 522, an ion implantation tool 114 may be used to implant ions (boron (B) ions, etc.) into the sensing structure 316b to dope the sensing structure 316b and form the doped isolation region 320b. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer 524 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0195] like Figure 5KAs shown, a p-type region 322b is formed in the sensing structure 316b. In some embodiments, a cavity pattern 526 of a photoresist layer 528 is used to define the p-type region 322b. In these embodiments, a deposition tool 102 may be used to form a photoresist layer 528 on the oxide layer 404 and the sensing structure 316a. An exposure tool 104 may be used to expose the photoresist layer 528 to a radiation source to pattern the photoresist layer 528. A development tool 106 may be used to develop and remove a portion of the photoresist layer 528 to form a cavity pattern 526. After forming the cavity pattern 526, an ion implantation tool 114 may be used to implant ions (gallium (Ga), aluminum (Al) or indium (In) ions, etc.) into the sensing structure 316b to dope the sensing structure 316b and form a p-type region 322b. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer 528 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0196] like Figure 5L As shown, n-type region 324b is formed in sensing structure 316b. In some embodiments, cavity pattern 530 of photoresist layer 532 is used to define n-type region 324b. In these embodiments, deposition tool 102 can be used to form photoresist layer 532 on sensing structure 316b and / or dielectric layer 406. Exposure tool 104 can be used to expose photoresist layer 532 to a radiation source to pattern photoresist layer 532. Development tool 106 can be used to develop and remove a portion of photoresist layer 532 to form cavity pattern 530. After forming cavity pattern 530, ion implantation tool 114 can be used to implant ions (phosphorus (P), arsenic (As) or antimony (Sb) ions, etc.) into sensing structure 316b to dope sensing structure 316b and form n-type region 324b. In some embodiments, photoresist removal tool can be used to remove the remaining portion of photoresist layer 532 (e.g., using chemical stripper, plasma ashing and / or another technique).

[0197] like Figure 5M As shown, epitaxial layer 410 is formed on and / or over sensing structure 316b. Deposition tool 102 may be used in epitaxial operations, Figure 1 The epitaxial layer 410 is deposited in another type of deposition operation and / or another suitable deposition operation. In some embodiments, the planarization tool 110 can be used to planarize the epitaxial layer 410 after the epitaxial layer 410 is deposited.

[0198] As an example, in some embodiments, the epitaxial layer 410 has a thickness D6 included in the range of about 4 microns to about 6 microns. If the thickness D6 is included in the range of about 4 microns to about 6 microns, the risk of leakage in a semiconductor device (e.g., semiconductor device 302a) including the epitaxial layer 410 can be reduced. In addition, or alternatively, if the thickness D6 is included in the range of about 4 microns to about 6 microns, the cost of manufacturing the semiconductor device may be feasible. If the thickness D6 is less than about 4 microns, the risk of leakage in the semiconductor device including the epitaxial layer 410 may increase. If the thickness D6 is greater than about 6 microns, the cost of manufacturing the semiconductor device may increase and is not feasible. However, other values ​​and ranges of thickness D6 are also within the scope of the present disclosure.

[0199] FIG. 5A to FIG. 5M Embodiment 500 is provided as an example. Embodiment 500 may include additional semiconductor process operations, fewer semiconductor process operations, different semiconductor process operations, or more semiconductor process operations. FIG. 5A to FIG. 5M In addition, or alternatively, a semiconductor process operation different from that shown in FIG. Figure 1 Related technologies and / or technologies other than semiconductor process tools to perform one or more semiconductor process operations.

[0200] Figure 6 This article describes Figure 1 In some embodiments, semiconductor processing tool 102 to tool 116 and / or wafer / wafer transport tool 118 may include one or more apparatuses 600 and / or one or more elements of apparatus 600. Figure 6 As shown, the device 600 may include a bus 610 , a processor 620 , a memory 630 , an input element 640 , an output element 650 , and / or a communication element 660 .

[0201] The bus 610 may include one or more components to enable wired and / or wireless communication between components of the device 600. The bus 610 may include one or more components to enable wired and / or wireless communication between components of the device 600. Figure 6Two or more elements of a processor 620 are coupled together, for example, by operational coupling, communication coupling, electronic coupling and / or electrical coupling. For example, bus 610 may include electrical connections (e.g., wires, routing and / or leads) and / or wireless buses. Processor 620 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, a special application integrated circuit and / or other types of processing elements. Processor 620 may be implemented in hardware, software or a combination of hardware and software. In some embodiments, processor 620 may include one or more processors that can be programmed to perform one or more operations or processes described herein.

[0202] The memory 630 may include volatile and / or non-volatile memory. For example, the memory 630 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 630 may include internal memory (e.g., RAM, ROM, or hard drive) and / or removable memory (e.g., moved via a universal serial bus connection). The memory 630 may be a non-transitory computer-readable medium. The memory 630 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 600. In some embodiments, the memory 630 may include one or more memories, for example, coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620) via a bus 610. The communicatively coupled between the processor 620 and the memory 630 may enable the processor 620 to read and / or process information in the memory 630 and / or store information in the memory 630.

[0203] Input element 640 can make device 600 receive input, such as user input and / or sensor input.For example, input element 640 can include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope and / or actuator.Output element 650 can make device 600 provide output, such as via display, loudspeaker and / or light emitting diode.Communication element 660 can make device 600 communicate with other devices by wired connection and / or wireless connection.For example, communication element 660 can include receiver, transmitter, transceiver, modem, network interface card and / or antenna.

[0204] The device 600 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 630) can store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 620. The processor 620 can execute the instruction set to perform one or more operations or processes described herein. In some embodiments, the instruction set is executed by one or more processors 620 so that one or more processors 620 and / or the device 600 perform one or more operations or processes described herein. In some embodiments, hardware circuits can be used instead of or in combination with instructions to perform one or more operations or processes described herein. In addition, or alternatively, the processor 620 can be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0205] Figure 6 The number and arrangement of elements shown are provided as examples. Apparatus 600 may include additional elements, fewer elements, different elements, or different Figure 6 Additionally or alternatively, one set of elements (eg, one or more elements) of the apparatus 600 may perform one or more functions performed by another set of elements of the apparatus 600.

[0206] Figure 7 is a flow chart of an exemplary process 700 associated with forming a multilayer photodiode structure described herein. In some embodiments, Figure 7 One or more process blocks of the method are performed using one or more semiconductor process tools (e.g., one or more semiconductor process tools 102 to 116). Additionally or alternatively, Figure 7 One or more process blocks may be performed using one or more components of the apparatus 600 , such as the processor 620 , the memory 630 , the input component 640 , the output component 650 , and / or the communication component 660 .

[0207] like Figure 7 As shown, process 700 may include forming an oxide layer on a substrate (block 705). For example, one or more semiconductor process tools 102-116 may be used to form an oxide layer (eg, oxide layer 404) on a substrate (eg, substrate 312a), as described herein.

[0208] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a first cavity through the oxide layer into the substrate (block 710). For example, one or more semiconductor process tools 102 to 116 may be used to form the first cavity (e.g., cavity 502) through the oxide layer into the substrate, as described herein.

[0209] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a first sensing structure in the first cavity (block 715 ). For example, one or more semiconductor process tools 102 to 116 may be used to form the first sensing structure (eg, sensing structure 316 a ) in the first cavity, as described herein.

[0210] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a doped isolation region adjacent to a sidewall of the first sensing structure (block 720). For example, one or more semiconductor process tools 102 to 116 may be used to form a doped isolation region adjacent to a sidewall of the first sensing structure (e.g., doped isolation region 320a), as described herein.

[0211] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a p-type region in the first sensing structure (block 725 ). For example, one or more semiconductor process tools 102 to 116 may be used to form a p-type region (eg, p-type region 322 a ) in the first sensing structure, as described herein.

[0212] like Figure 7 As further shown in FIG. 7 , process 700 may include forming an n-type region in the first sensing structure (block 730 ). For example, one or more semiconductor process tools 102 - 116 may be used to form an n-type region (eg, n-type region 324 a ) in the first sensing structure, as described herein.

[0213] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a dielectric layer on the first sensing structure (block 735 ). For example, one or more semiconductor process tools 102 - 116 may be used to form a dielectric layer (eg, dielectric layer 406 ) on the first sensing structure, as described herein.

[0214] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a recessed region in the dielectric layer (block 740 ). For example, one or more semiconductor process tools 102 - 116 may be used to form a recessed region (eg, recessed region 516 ) in the dielectric layer, as described herein.

[0215] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a second cavity through the dielectric layer in the recessed region and through the oxide layer (block 745). For example, one or more semiconductor process tools 102 to 116 may be used to form the second cavity (e.g., cavity 520) through the dielectric layer in the recessed region and through the oxide layer, as described herein.

[0216] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a second sensing structure located above the recessed region, and the second sensing structure includes a bottom protrusion filling the second cavity to connect to the substrate (block 750). For example, one or more semiconductor process tools 102 to 116 may be used to form a second sensing structure (e.g., sensing structure 316b) located above the recessed region and including a bottom protrusion filling the second cavity to connect to the substrate, as described herein. In some embodiments, forming the second sensing structure includes forming the second sensing structure above the first sensing structure.

[0217] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or be associated with one or more other processes described elsewhere herein.

[0218] In a first embodiment, forming the doped isolation region includes performing an implantation operation to dope a region of the substrate adjacent to a sidewall of the first sensing structure.

[0219] In a second embodiment, either alone or in combination with the first embodiment, performing an implantation operation includes implanting a boron dopant.

[0220] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the doped isolation region includes forming the doped isolation region to a greater depth relative to the cavity depth.

[0221] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the doped isolation region is a first isolation region, and further includes forming at least one second isolation region (eg, doped isolation region 320 b ) in the second sensing structure.

[0222] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the p-type region is a first p-type region, the n-type region is a first n-type region, and further includes forming a second p-type region (e.g., p-type region 322b) or a second n-type region (e.g., n-type region 324b) in the second sensing structure.

[0223] although Figure 7 illustrative blocks of process 700 are shown, but in some embodiments, process 700 includes Figure 7 Additional blocks, fewer blocks, different blocks, or blocks arranged differently may be used. Additionally or alternatively, two or more blocks of process 700 may be performed in parallel.

[0224] Some embodiments described herein provide an optoelectronic device including a multilayer photodiode structure. The multilayer photodiode structure includes a stacked configuration of multiple sensing structures formed of a quantum effect material (e.g., a germanium material). By using a stacked configuration of multiple sensing structures, the quantum effect length is increased relative to another photodiode including a single-layer photodiode structure.

[0225] In addition, the lower sensing structure of the multi-layer sensing structure can share a substrate with the integrated circuit of the optoelectronic device. The lower sensing structure is electrically isolated from the integrated circuit by a doped isolation region adjacent to the sidewall of the lower sensing structure. The amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to manufacture the optoelectronic device is reduced relative to another optoelectronic device including the lower sensing structure and the integrated circuit on separate substrates.

[0226] By increasing the quantum length, an optoelectronic device including a photodiode has improved performance relative to another optoelectronic device including a photodiode having a single layer of quantum effect material. By improving the performance of the optoelectronic device, the quality and reliability of the optoelectronic device in the target application and / or environment can be improved, thereby improving manufacturing yield and reducing field failure rate. This improvement in manufacturing yield and reduction in field failure rate can be further combined with the lower sensing structure on the substrate and the integrated circuit to expand the realization of resource conservation.

[0227] Thus, the performance of an optoelectronic device including a multilayer photodiode structure is improved relative to another optoelectronic device including a photodiode structure of a single planar sensing structure. By improving the performance of the optoelectronic device, the quality and reliability of the optoelectronic device in a target application and / or environment can be improved, thereby improving manufacturing yield and reducing field failure rates. Improving manufacturing yield and reducing field failure rates can reduce the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to maintain market consumption of the optoelectronic device.

[0228] As described herein, an optoelectronic device includes a multilayer photodiode structure. The multilayer photodiode structure includes a stacked configuration of multiple sensing structures formed of a quantum effect material (e.g., a germanium material). By using a stacked configuration of multiple sensing structures, the quantum effect length is increased relative to another photodiode including a single-layer photodiode structure. In addition, a lower sensing structure of the multilayer sensing structure can share a substrate with an integrated circuit of the optoelectronic device. The lower sensing structure is electrically isolated from the integrated circuit by a doped isolation region adjacent to a sidewall of the lower sensing structure. Relative to another optoelectronic device including a lower sensing structure and an integrated circuit on a separate substrate, the amount of resources required to manufacture the optoelectronic device (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) is reduced.

[0229] By increasing the quantum length, the performance of an optoelectronic device including a photodiode is improved relative to another optoelectronic device including a photodiode having a single layer of quantum effect material. In this way, the performance of the optoelectronic device, the quality of the optoelectronic device, and the reliability of the optoelectronic device in the target application and / or environment can be improved, thereby improving manufacturing yield and reducing field failure rate. This improvement in manufacturing yield and reduction in field failure rate can be achieved by further combining the lower sensing structure and the integrated circuit on the substrate to expand the resource saving.

[0230] As described in detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes a substrate and a multilayer photodiode structure. The multilayer photodiode structure includes a first sensing structure, a second sensing structure, an oxide layer, and a dielectric layer. The first sensing structure extends into the substrate, includes a first quantum effect material, and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate. The second sensing structure is located on the first sensing structure and includes a second quantum effect material. The oxide layer is located below the second sensing structure and is located on the first sensing structure. The dielectric layer is located on the oxide layer and is located below the second sensing structure. In some embodiments, the second sensing structure includes a bottom protrusion that passes downward through the dielectric layer, through the oxide layer, and reaches the substrate. In some embodiments, the substrate includes a silicon-on-insulator structure. In some embodiments, the dielectric layer includes an iron oxide material or a zinc oxide material. In some embodiments, the thickness of the second sensing structure is smaller than the thickness of the first sensing structure. In some embodiments, the optoelectronic device also includes a vertically arranged electromagnetic wave transmission region, the electromagnetic wave transmission region includes the first sensing structure and has a width approximately the same as the first sensing structure. In some embodiments, the second sensing structure is included outside the electromagnetic wave transmission region. In some embodiments, the second sensing structure extends laterally into the electromagnetic wave transmissive region.

[0231] As described in detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes a first semiconductor wafer and a second semiconductor wafer bonded to the first semiconductor wafer below the first semiconductor wafer. The first semiconductor wafer includes a first substrate and a pixel sensor. The pixel sensor includes a multilayer photodiode structure. The multilayer photodiode structure includes a first sensing structure and a second sensing structure. The first sensing structure extends into the first substrate, includes a first quantum effect material, and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the first substrate. The second sensing structure is located on the first sensing structure and includes a second quantum effect material. The second semiconductor wafer includes a second substrate and a logic integrated circuit on or within the second substrate. In some embodiments, the first sensing structure includes a p-type region and an n-type region. In some embodiments, the second sensing structure includes a p-type region and an n-type region. In some embodiments, the first quantum effect material and the second quantum effect material each include a Group III material or a Group V material. In some embodiments, the doped isolation regions are a plurality of first doped isolation regions and the second sensing structure includes a plurality of second doped isolation regions. In some embodiments, the optoelectronic device further includes an epitaxial layer on the second sensing structure and a plurality of third doped isolation regions, wherein the third doped isolation regions are located in the epitaxial layer.

[0232] As described in detail above, some embodiments described herein provide a method for manufacturing an optoelectronic device. The method includes the following operations. An oxide layer is formed on a substrate. A first cavity is formed through the oxide layer to enter the substrate. A first sensing structure is formed in the first cavity. A plurality of doped isolation regions are formed adjacent to a plurality of sidewalls of the first sensing structure. A p-type region is formed in the first sensing structure. An n-type region is formed in the first sensing structure. A dielectric layer is formed on the first sensing structure. A recessed region is formed in the dielectric layer. A second cavity is formed through the dielectric layer in the recessed region and through the oxide layer. A second sensing structure is formed on the recessed region, and the second sensing structure includes a bottom protrusion filling the second cavity to connect with the substrate, wherein forming the second sensing structure includes forming the second sensing structure on the first sensing structure. In some embodiments, forming the doped isolation regions includes performing an implantation operation on a plurality of doped regions of the substrate adjacent to the sidewalls of the first sensing structure. In some embodiments, performing the implantation operation includes implanting a boron dopant. In some embodiments, forming the doped isolation regions includes forming the depth of the doped isolation regions to be greater than the depth of the first cavity. In some embodiments, the doped isolation regions are a plurality of first isolation regions, and the method further comprises forming at least one second isolation region in the second sensing structure. In some embodiments, the p-type region is a first p-type region, the n-type region is a first n-type region, and the method further comprises forming a second p-type region or a second n-type region in the second sensing structure.

[0233] The present disclosure provides an optoelectronic device, including a substrate and a multilayer photodiode structure. The multilayer photodiode structure includes a first sensing structure, a second sensing structure, an oxide layer, and a dielectric layer. The first sensing structure extends into the substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate. The second sensing structure is located on the first sensing structure. The oxide layer is located under the second sensing structure and is located on the first sensing structure. The dielectric layer is located on the oxide layer and is located under the second sensing structure. In some embodiments, the second sensing structure includes: a bottom protrusion that passes downward through the dielectric layer, through the oxide layer, and reaches the substrate. In some embodiments, the thickness of the second sensing structure is smaller than the thickness of the first sensing structure. In some embodiments, the optoelectronic device also includes: a vertically arranged electromagnetic wave transmission region, the electromagnetic wave transmission region includes the first sensing structure and has approximately the same width as the first sensing structure. In some embodiments, the second sensing structure extends laterally into the electromagnetic wave transmission region.

[0234] The present disclosure also provides an optoelectronic device, including a first semiconductor wafer and a second semiconductor wafer bonded to the first semiconductor wafer below the first semiconductor wafer. The first semiconductor wafer includes a first substrate and a pixel sensor. The pixel sensor includes a multilayer photodiode structure. The multilayer photodiode structure includes a first sensing structure and a second sensing structure. The first sensing structure extends into the first substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the first substrate. The second sensing structure is located on the first sensing structure. The second semiconductor wafer includes a second substrate and a logic integrated circuit on or in the second substrate. In some embodiments, the first sensing structure includes: a p-type region; and an n-type region. In some embodiments, the doped isolation region is a plurality of first doped isolation regions and wherein the second sensing structure includes: a plurality of second doped isolation regions. In some embodiments, the optoelectronic device further includes: an epitaxial layer on the second sensing structure; and a plurality of third doped isolation regions, wherein the third doped isolation regions are located in the epitaxial layer.

[0235] The present disclosure further provides an optoelectronic device. The optoelectronic device includes a substrate and a multilayer photodiode structure. The multilayer photodiode structure includes a vertically arranged electromagnetic wave transmission region and the electromagnetic wave transmission region includes a first sensing structure, a second sensing structure, an oxide layer and a dielectric layer. The electromagnetic wave transmission region has a width approximately the same as that of the first sensing structure, the first sensing structure extends into the substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate. The second sensing structure is located on the first sensing structure and is included outside the electromagnetic wave transmission region. The oxide layer is located under the second sensing structure and is located on the first sensing structure. The dielectric layer is located on the oxide layer and is located under the second sensing structure.

[0236] As used herein, the term "and / or", when used in conjunction with multiple items, is meant to cover each of the multiple items individually as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A but not B", and "B but not A".

[0237] As used herein, "satisfies a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, or not equal to a threshold, etc., depending on the context.

[0238] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A photoelectric device, characterized in that: include: a substrate; as well as A multi-layer photodiode structure comprising: a first sensing structure extending into the substrate, the first sensing structure having a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate; A second sensing structure is located on the first sensing structure; An oxide layer is located under the second sensing structure and on the first sensing structure; and A dielectric layer is located on the oxide layer and below the second sensing structure.

2. The photovoltaic device according to claim 1, wherein: The second sensing structure includes: A bottom protrusion extends downward through the dielectric layer, through the oxide layer and to the substrate.

3. The photovoltaic device according to claim 1, wherein: A thickness of the second sensing structure is smaller than a thickness of the first sensing structure.

4. The photovoltaic device according to any one of claims 1 to 3, characterized in that Also includes: An electromagnetic wave transmission area is arranged vertically, wherein the electromagnetic wave transmission area includes the first sensing structure and has a width substantially the same as that of the first sensing structure.

5. The photovoltaic device according to claim 4, characterized in that The second sensing structure extends laterally into the electromagnetic wave transmission area.

6. A photoelectric device, characterized in that: include: A first semiconductor wafer comprising: a first substrate; and A pixel sensor comprising: A multi-layer photodiode structure comprising: a first sensing structure extending into the first substrate, the first sensing structure having a plurality of sidewalls adjacent to a plurality of doped isolation regions in the first substrate; and a second sensing structure located on the first sensing structure; and A second semiconductor wafer bonded to the first semiconductor wafer below the first semiconductor wafer, the second semiconductor wafer comprising: a second substrate; and A logic integrated circuit is on or in the second substrate.

7. The photovoltaic device according to claim 6, wherein: The first sensing structure includes: a p-type region; and An n-type region.

8. The photovoltaic device according to any one of claims 6 to 7, characterized in that: The plurality of doped isolation regions are a plurality of first doped isolation regions and the second sensing structure comprises: A plurality of second doped isolation regions.

9. The photovoltaic device according to claim 8, wherein: Also includes: An epitaxial layer is on the second sensing structure; as well as A plurality of third doped isolation regions are provided, wherein the plurality of third doped isolation regions are located in the epitaxial layer.

10. A photoelectric device, characterized in that: include: a substrate; A multi-layer photodiode structure comprising: An electromagnetic wave transmission region arranged vertically, the electromagnetic wave transmission region includes a first sensing structure and has a width approximately the same as the first sensing structure, the first sensing structure extends into the substrate and has a plurality of sidewalls adjacent to a plurality of doped isolation regions in the substrate; A second sensing structure is located on the first sensing structure and is included outside the electromagnetic wave transmission area; An oxide layer is located under the second sensing structure and on the first sensing structure; and A dielectric layer is located on the oxide layer and below the second sensing structure.

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