Short-circuit fault latch protection and self-recovery circuit

Abstract

The utility model belongs to the technical field of electronics, and discloses a short-circuit fault latch protection and self-recovery circuit, which comprises a short-circuit protection control circuit and a short-circuit protection output circuit, the short-circuit protection control circuit is connected with the short-circuit protection output circuit, the short-circuit protection control circuit comprises a first triode circuit, a second triode circuit, an RC charging and discharging circuit, a NAND gate circuit and a third triode circuit, and the first triode circuit and the RC charging and discharging circuit are connected in parallel and then connected with the second triode circuit. The first triode circuit, the second triode circuit and the RC charging and discharging circuit are connected with the input end of the NAND gate circuit, the output end of the NAND gate circuit is connected with the third triode circuit, and the third triode circuit is connected with the short-circuit protection output circuit. According to the utility model, the problem that output cannot be automatically recovered after output short-circuit protection in the prior art can be solved.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, and particularly relates to a short - circuit fault latching protection and self - recovery circuit. Background Art

[0002] During the use of a DC power supply, it is inevitable that an output short - circuit occurs. After the power supply output is short - circuited, its output current increases abnormally, which will cause the abnormal operation of the power supply unit circuit and damage the power supply itself. Existing DC power supplies generally have a short - circuit protection function. When an output short - circuit is detected, the output power supply and the load connection are immediately disconnected to protect the power supply from being damaged. However, for some power supplies, after the output short - circuit protection, the power supply output is disconnected. Even if the output short - circuit state is removed, the power supply cannot automatically resume output and needs to be powered on again to work properly. Content of the Utility Model

[0003] The utility model provides a short - circuit fault latching protection and self - recovery circuit to solve the problem that the existing technology cannot automatically resume output after output short - circuit protection.

[0004] To achieve the above object, the utility model adopts the following technical solutions:

[0005] A short - circuit fault latching protection and self - recovery circuit includes a short - circuit protection control circuit and a short - circuit protection output circuit;

[0006] The short - circuit protection control circuit includes a first triode circuit, a second triode circuit, an RC charge - discharge circuit, a NAND gate circuit, and a third triode circuit. The first triode circuit and the RC charge - discharge circuit are connected in parallel and then connected to the second triode circuit. The first triode circuit, the second triode circuit, and the RC charge - discharge circuit are connected to the input end of the NAND gate circuit. The output end of the NAND gate circuit is connected to the third triode circuit, and the third triode circuit is connected to the short - circuit protection output circuit; the short - circuit protection control circuit is connected to the short - circuit protection output circuit. When receiving a high - level short - circuit fault signal ERR, it outputs a low - level LOCK signal to the short - circuit protection output circuit, then cuts off the connection between the front - stage and the rear - stage of the short - circuit protection output circuit, and at the same time, the capacitor in the short - circuit protection control circuit starts to discharge until it is completely discharged; when receiving a low - level short - circuit fault signal ERR, it outputs a high - level LOCK signal to the short - circuit protection output circuit, and at the same time, the capacitor in the short - circuit protection control circuit starts to charge until the charging voltage reaches the threshold of the NAND gate circuit and then restores the connection between the front - stage and the rear - stage of the short - circuit protection output circuit.

[0007] In some embodiments, the first triode circuit includes: resistor R1, resistor R2, and triode Q1;

[0008] The resistor R1 is connected to the base of the triode Q1. A resistor R2 is provided between the base and the emitter of the triode Q1. The emitter of the triode Q1 is grounded, and the collector of the triode Q1 is connected to the NAND gate circuit.

[0009] In some embodiments, after the base of the triode Q1 is connected to the resistor R1, it is connected to the high-level short-circuit fault signal ERR or the low-level short-circuit fault signal ERR.

[0010] In some embodiments, the second triode circuit includes: a triode Q2 and a resistor R5; the emitter of the triode Q2 is grounded, the base of the triode Q2 is connected to the resistor R5 and then connected to the NAND gate circuit, and the collector of the triode Q2 is connected to the collector of the triode Q1.

[0011] In some embodiments, the RC charge and discharge circuit includes: a diode D1, a resistor R3, a diode D2, a resistor R4, a capacitor C1, and a power supply VCC;

[0012] The anode of the diode D1 is connected to the power supply VCC, the cathode of the diode D1 is connected to the resistor R3, the resistor R3 is connected to the collector of the triode Q1, the anode of the diode D2, and the collector of the triode Q2. The cathode of the diode D2 is connected to the upper end of the parallel connection of the resistor R4 and the capacitor C1, and is also connected to the NAND gate circuit. The lower end of the parallel connection of the resistor R4 and the capacitor C1 is grounded.

[0013] In some embodiments, the NAND gate circuit includes a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate. The input terminals 1A and 1B of the first NAND gate are connected to the input terminals 3A of the third NAND gate and the collector of the triode Q1. The output terminal 1Y of the first NAND gate is connected to the input terminal 2A of the second NAND gate. The input terminal 2B of the second NAND gate is connected to the input terminal 3B of the third NAND gate, the resistor R4, and the capacitor C1. The output terminal 2Y of the second NAND gate is connected to the input terminals 4A and 4B of the fourth NAND gate. The output terminal of the fourth NAND gate is connected to the resistor R5. The output terminal 3Y of the third NAND gate is connected to the third triode circuit.

[0014] In some embodiments, the third triode circuit includes: a resistor R6, a resistor R7, a triode Q3, and a resistor R8. The base of the triode Q3 is connected to the resistor R6, the resistor R6 is connected to the output terminal 3Y of the third NAND gate. A resistor R7 is provided between the emitter and the base of the triode Q3. The emitter of the triode Q3 is grounded, and the collector of the triode Q3 is connected to the power supply VCC in series with the resistor R8.

[0015] In some embodiments, the collector of the triode Q3 outputs the low-level LOCK signal or the high-level LOCK signal to the short-circuit protection output circuit.

[0016] In some embodiments, the short-circuit protection output circuit includes: resistor R11, resistor R12, resistor R13, resistor R14, capacitor C11, capacitor C12, diode D11, PMOS transistor Q5, and NMOS transistor Q4;

[0017] The source of PMOS transistor Q5 is connected to resistor R11 and then connected to the front stage of the short-circuit protection output circuit. A resistor R12 is provided between the gate and the source of PMOS transistor Q5. The drain of PMOS transistor Q5 is connected in parallel with diode D11 and capacitor C12 and then connected to the rear stage of the short-circuit protection output circuit. The cathode of diode D11 is connected to the drain of PMOS transistor Q5, and the anode of diode D11 is grounded. One end of resistor R13 is connected to the gate of PMOS transistor Q5, and the other end is connected to the drain of NMOS transistor Q4. Resistor R14 and capacitor C11 are connected in parallel and then connected to the gate of NMOS transistor Q4. The source of NMOS transistor Q4, capacitor C11, resistor R14, and capacitor C12 are all grounded.

[0018] In some embodiments, the high-level LOCK signal or the low-level LOCK signal is input to the gate of NMOS transistor Q4.

[0019] Compared with the prior art, the present utility model has the following beneficial effects:

[0020] The utility model provides a short - circuit fault latching protection and self - recovery circuit, which includes a short - circuit protection control circuit and a short - circuit protection output circuit. The short - circuit protection control circuit includes a first triode circuit, a second triode circuit, an RC charge - discharge circuit, a NAND gate circuit and a third triode circuit. The first triode circuit and the RC charge - discharge circuit are connected in parallel and then connected to the second triode circuit. The first triode circuit, the second triode circuit and the RC charge - discharge circuit are connected to the input end of the NAND gate circuit. The output end of the NAND gate circuit is connected to the third triode circuit, and the third triode circuit is connected to the short - circuit protection output circuit. When the short - circuit protection control circuit receives a high - level short - circuit fault signal, it outputs a low level to the short - circuit protection output circuit, then cuts off the connection between the front - stage and the rear - stage of the short - circuit protection output circuit. At the same time, the capacitor in the short - circuit protection control circuit starts to discharge until it is completely discharged. After receiving a low - level short - circuit fault signal, it outputs a high level to the short - circuit protection output circuit. At the same time, the capacitor in the short - circuit protection control circuit starts to charge until the charging voltage reaches the threshold value of the NAND gate circuit, and then restores the connection between the front - stage and the rear - stage of the short - circuit protection output circuit. It can maintain the normal output of the front - stage of the short - circuit protection output circuit inside the power supply after the power supply output is short - circuit protected, and disconnect the connection between the rear - stage of the power supply circuit protection output circuit and the load. At the same time, when the output short - circuit phenomenon disappears, the power supply can self - recover the connection with the load and output the normal voltage, solving the problem that the prior art cannot automatically recover the output after the output is short - circuit protected. At the same time, the utility model performs self - recovery through charge - discharge, has a fault latching function, and has higher reliability and faster short - circuit protection response in practical applications. Description of the Drawings

[0021] Figure 1 It is the structural diagram of the short - circuit protection control circuit provided in Embodiment 1;

[0022] Figure 2 It is the structural diagram of the short - circuit protection output circuit provided in Embodiment 1. Detailed Embodiments

[0023] This part will describe the specific embodiments of the utility model in detail. The preferred embodiments of the utility model are shown in the drawings. The role of the drawings is to supplement the description of the text part of the specification, enabling people to intuitively and vividly understand each technical feature and the overall technical solution of the utility model. However, it cannot be understood as a limitation on the protection scope of the utility model.

[0024] In the description of the utility model, the meaning of "a plurality" is more than two. Understandings such as "greater than", "less than", "exceeding", etc. do not include the present number, and understandings such as "above", "below", "within", etc. include the present number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0025] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0026] Embodiment 1

[0027] The utility model provides a short circuit fault latch protection and self-recovery circuit, such as Figure 1 and Figure 2 As shown, the circuit is composed of a short-circuit protection control circuit and a short-circuit protection output circuit. The short-circuit protection output circuit includes: resistor R11, resistor R12, resistor R13, resistor R14, capacitor C11, capacitor C12, diode D11, PMOS tube Q5 and NMOS tube Q4. The short-circuit protection control circuit is connected to the short-circuit protection output circuit. The short-circuit protection output circuit is located in the front stage of the power output VOUT as a part of the power supply circuit, between the output VOUT and the load. When the output short circuit occurs at the power output, the connection between the front stage VOUT1 and the output VOUT can be immediately cut off to keep the power supply VOUT1 stable. Even if the fault disappears, the short-circuit fault signal is still latched, and VOUT1 and VOUT are kept disconnected. Then, the internal RC discharge circuit is started. After the time reaches the preset time, it is determined whether the short-circuit fault state is maintained. If it is maintained, the short-circuit fault signal is kept unchanged, and the disconnection state of VOUT1 and VOUT is maintained. If the short-circuit fault state has disappeared at this time, the fault signal is cleared, and the RC charge and discharge circuit starts to reset, and VOUT1 and VOUT are restored to conduction. The short-circuit fault latching and self-recovery circuit provided in this embodiment is a pure analog circuit, and has fast short-circuit protection response, low cost, simple design and high reliability.

[0028] 1. Short circuit protection control circuit

[0029] like Figure 1 As shown, the short-circuit protection control circuit is composed of resistor R1, resistor R2, transistor Q1, resistor R5, transistor Q2, diode D1, resistor R3, diode D2, capacitor C1, resistor R4, NAND gate logic chip U1 (NAND gate circuit), resistor R6, resistor R7, resistor R8 and transistor Q3. Among them, ERR is the short-circuit fault signal, LOCK is the fault protection signal, and is connected to the NMOS tube Q4 of the short-circuit protection output circuit. The power supply VCC and GND are the positive and negative poles of the control circuit power supply.

[0030] The resistor R1 is connected to the base of the triode Q1. A resistor R2 is provided between the base and the emitter of the triode Q1. The emitter of the triode Q1 is grounded. The collector of the triode Q1 is connected to the NAND gate circuit. The emitter of the triode Q2 is grounded. The base of the triode Q2 is connected to the resistor R5 and then connected to the NAND gate circuit. The collector of the triode Q2 is connected to the collector of the triode Q1. The anode of the diode D1 is connected to the power supply VCC, and the cathode of the diode D1 is connected to the resistor R3. The resistor R3 is connected to the collector of the triode Q1, the anode of the diode D2, and the collector of the triode Q2. The cathode of the diode D2 is connected to the upper end of the parallel connection of the resistor R4 and the capacitor C1 and is also connected to the NAND gate circuit. The lower end of the parallel connection of the resistor R4 and the capacitor C1 is grounded. The base of the triode Q3 is connected to the resistor R6, and the resistor R6 is connected to the output terminal 3Y of the third NAND gate. A resistor R7 is provided between the emitter and the base of the triode Q3. The emitter of the triode Q3 is grounded. The collector of the triode Q3 is connected to the power supply VCC in series with the resistor R8.

[0031] The NAND gate logic chip U1 includes a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate. The input terminals 1A and 1B of the first NAND gate are connected to the input terminal 3A of the third NAND gate and the collector of the triode Q1. The output terminal 1Y of the first NAND gate is connected to the input terminal 2A of the second NAND gate. The input terminal 2B of the second NAND gate is connected to the input terminal 3B of the third NAND gate, the resistor R4, and the capacitor C1. The output terminal 2Y of the second NAND gate is connected to the input terminals 4A and 4B of the fourth NAND gate. The output terminal of the fourth NAND gate is connected to the resistor R5. The output terminal 3Y of the third NAND gate is connected to the third triode circuit.

[0032] 2. Short-circuit protection output circuit

[0033] As Figure 2 shown, the short-circuit protection output circuit is composed of a capacitor C11, a resistor R14, an NMOS transistor Q4, a resistor R11, a resistor R12, a resistor R13, a PMOS transistor Q5, a diode D11, and a capacitor C12 connected. VOUT1 is the input, and VOUT is the output. VOUT1 is connected in series with the resistor R11 and the PMOS transistor Q5. VOUT is connected to the load.

[0034] The source of PMOS transistor Q5 is connected to resistor R11 and then connected to the front stage of the short-circuit protection output circuit. A resistor R12 is provided between the gate and source of PMOS transistor Q5. The drain of PMOS transistor Q5 is connected in parallel with diode D11 and capacitor C12 and connected to the rear stage of the short-circuit protection output circuit. The cathode of diode D11 is connected to the drain of PMOS transistor Q5, and the anode of diode D11 is grounded. One end of resistor R13 is connected to the gate of PMOS transistor Q5, and the other end is connected to the drain of NMOS transistor Q4. Resistor R14 and capacitor C11 are connected in parallel and then connected to the gate of NMOS transistor Q4. The source of NMOS transistor Q4, capacitor C11, resistor R14, and capacitor C12 are all grounded.

[0035] The working principles of the above short-circuit protection control circuit and short-circuit protection output circuit are as follows:

[0036] (1) Under normal operating conditions: The short-circuit fault signal ERR is at a low level, transistor Q1 is turned off, capacitor C1 is charged to a high level, inputs 1A, 1B, and 2B are high, output 1Y and input 2A are low, output 4Y is at a low level, transistor Q2 is turned off, inputs 3A and 3B are high, output 3Y is at a low level, transistor Q3 is turned off, the LOCK signal is at a high level, NMOS transistor Q4 is turned on, PMOS transistor Q5 is turned on, and VOUT is normally output;

[0037] (2) Under short - circuit condition: When an output short - circuit occurs, the short - circuit fault signal ERR is at high level, the triode Q1 conducts, the input terminals 1A, 1B, 3A, and 3B are at low level, the output terminal 1Y and the input terminal 2A are at high level, the output terminal 3Y is at high level, the triode Q3 conducts, the LOCK signal is at low level, the NMOS transistor Q4 is turned off, and the PMOS transistor Q5 is turned off, disconnecting the connection between VOUT1 and VOUT. Since the triode Q1 conducts, due to the reverse cut - off of the diode D2, the capacitor C1 discharges through the resistor R4. The resistance value of the resistor R4 is set very large, and it cannot discharge to low level in a short time. Therefore, the input terminal 2B is at high level, the output terminal 4Y is at high level, and the triode Q2 conducts. In fact, the triode Q2 conducts almost synchronously with the triode Q1. At this time, even if the fault signal disappears, that is, the triode Q1 is turned off, because the triode Q2 remains conducting, the triode Q3 still remains conducting, the LOCK signal is at low level, and the short - circuit fault signal is latched until the capacitor C1 is completely discharged, the input terminal 2B is at low level, the output terminal 4Y is at low level, and the triode Q2 is turned off. At this time, the circuit detects the state of the short - circuit fault signal ERR. If the short - circuit fault signal ERR is at high level, it indicates that the short - circuit fault state still exists, and the disconnection state between VOUT1 and VOUT is maintained. If the short - circuit fault signal ERR is at low level, it indicates that the short - circuit fault state has disappeared, then the fault signal is cleared, and VCC charges the capacitor C1 through the diode D1, resistor R3, diode D2, and GND. When the charging voltage of the capacitor C1 reaches the threshold voltage of the NAND - gate logic chip U1, the input terminal 2B is at high level, the output terminal 4Y is high, the triode Q2 is turned off, the triode Q3 is turned off, the LOCK signal is at high level, the NMOS transistor Q4 conducts, the PMOS transistor Q5 conducts, the connection between VOUT1 and VOUT is restored, and VOUT outputs normally. Here, the resistance values and capacitance values of the resistor R4, capacitor C1, and resistor R3 can be set to adjust the length of the fault - latching time and the self - recovery time.

[0038] Compared with other short - circuit protection and self - recovery circuits, the circuit provided in this embodiment has the advantages that it is a pure analog circuit, with fast short - circuit protection response, low cost, simple design, has a fault - latching function, and is more reliable in practical applications.

[0039] Embodiment Two

[0040] This embodiment provides a short - circuit fault latching protection and self - recovery circuit, including a short - circuit protection control circuit and a short - circuit protection output circuit;

[0041] The short - circuit protection control circuit is connected to the short - circuit protection output circuit. When receiving a high - level short - circuit fault signal ERR, it outputs a low - level LOCK signal to the short - circuit protection output circuit, then cuts off the connection between the front - stage and the rear - stage of the short - circuit protection output circuit. At the same time, the capacitor in the short - circuit protection control circuit starts to discharge until it is completely discharged; when receiving a low - level short - circuit fault signal ERR, it outputs a high - level LOCK signal to the short - circuit protection output circuit. At the same time, the capacitor in the short - circuit protection control circuit starts to charge until the charging voltage reaches the threshold of the NAND gate circuit and then restores the connection between the front - stage and the rear - stage of the short - circuit protection output circuit;

[0042] The short - circuit protection control circuit includes a first triode circuit, a second triode circuit, an RC charge - discharge circuit, a NAND gate circuit, and a third triode circuit. The first triode circuit and the RC charge - discharge circuit are connected in parallel and then connected to the second triode circuit. The first triode circuit, the second triode circuit, and the RC charge - discharge circuit are connected to the input terminal of the NAND gate circuit. The output terminal of the NAND gate circuit is connected to the third triode circuit, and the third triode circuit is connected to the short - circuit protection output circuit;

[0043] The first triode circuit includes: resistor R1, resistor R2, and triode Q1. Resistor R1 is connected to the base of triode Q1. A resistor R2 is provided between the base and the emitter of triode Q1. The emitter of triode Q1 is grounded, and the collector of triode Q1 is connected to the NAND gate circuit.

[0044] The second triode circuit includes: triode Q2 and resistor R5. The emitter of triode Q2 is grounded. The base of triode Q2 is connected to resistor R5 and then connected to the NAND gate circuit. The collector of triode Q2 is connected to the collector of triode Q1;

[0045] The RC charge - discharge circuit includes: diode D1, resistor R3, diode D2, resistor R4, capacitor C1, and power supply VCC. The anode of diode D1 is connected to the power supply VCC. The cathode of diode D1 is connected to resistor R3. Resistor R3 is connected to the collector of triode Q1, the anode of diode D2, and the collector of triode Q2. The cathode of diode D2 is connected to the upper end of the parallel connection of resistor R4 and capacitor C1 and is also connected to the NAND gate circuit. The lower end of the parallel connection of resistor R4 and capacitor C1 is grounded;

[0046] The third triode circuit includes: resistor R6, resistor R7, triode Q3, and resistor R8. The base of triode Q3 is connected to resistor R6. Resistor R6 is connected to the output terminal 3Y of the third NAND gate. A resistor R7 is provided between the emitter and the base of triode Q3. The emitter of triode Q3 is grounded. The collector of triode Q3 is connected to the power supply VCC in series with resistor R8.

[0047] The NAND gate circuit is the same as the NAND gate logic chip U1 described in the first embodiment, and the short-circuit protection output circuit is the same as that in the first embodiment.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the specific implementation manners of the present invention can still be modified or equivalently replaced, and any modification or equivalent replacement without departing from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A short circuit fault latch protection and self-recovery circuit, characterized in that: It includes a short-circuit protection control circuit and a short-circuit protection output circuit; The short-circuit protection control circuit comprises a first triode circuit, a second triode circuit, an RC charge-discharge circuit, a NAND gate circuit and a third triode circuit, the first triode circuit and the RC charge-discharge circuit are connected in parallel and then connected to the second triode circuit, the first triode circuit, the second triode circuit and the RC charge-discharge circuit are connected to the input end of the NAND gate circuit, the output end of the NAND gate circuit is connected to the third triode circuit, and the third triode circuit is connected to the short-circuit protection output circuit; The short-circuit protection control circuit is connected to the short-circuit protection output circuit, and is used for outputting a low-level LOCK signal to the short-circuit protection output circuit when receiving a high-level short-circuit fault signal ERR, thereby cutting off the connection between the front stage and the rear stage of the short-circuit protection output circuit, and at the same time, the capacitor in the short-circuit protection control circuit starts to discharge until it is completely discharged; after receiving the low-level short-circuit fault signal ERR, the high-level LOCK signal is output to the short-circuit protection output circuit, and at the same time, the capacitor in the short-circuit protection control circuit starts to charge until the charged voltage reaches the threshold of the NAND gate circuit, and then the connection between the front stage and the rear stage of the short-circuit protection output circuit is restored.

2. A short circuit fault latch protection and self-recovery circuit according to claim 1, characterized in that: The first transistor circuit includes: a resistor R1, a resistor R2, and a transistor Q1; The resistor R1 is connected to the base of the transistor Q1 , a resistor R2 is arranged between the base and the emitter of the transistor Q1 , the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the NAND gate circuit.

3. A short circuit fault latch protection and self-recovery circuit according to claim 2, characterized in that: The base of the transistor Q1 is connected to the resistor R1 and then connected to the high level short circuit fault signal ERR or the low level short circuit fault signal ERR.

4. A short circuit fault latch protection and self-recovery circuit according to claim 2, characterized in that: The second transistor circuit includes: a transistor Q2 and a resistor R5; the emitter of the transistor Q2 is grounded, the base of the transistor Q2 is connected to the resistor R5 and then connected to the NAND gate circuit, and the collector of the transistor Q2 is connected to the collector of the transistor Q1.

5. A short circuit fault latch protection and self-recovery circuit according to claim 4, characterized in that: The RC charging and discharging circuit includes: a diode D1, a resistor R3, a diode D2, a resistor R4, a capacitor C1, and a power supply VCC; The anode of the diode D1 is connected to the power supply VCC, the cathode of the diode D1 is connected to the resistor R3, the resistor R3 is connected to the collector of the transistor Q1, the anode of the diode D2 and the collector of the transistor Q2, the cathode of the diode D2 is connected to the parallel upper end of the resistor R4 and the capacitor C1, and is connected to the NAND gate circuit, and the parallel lower end of the resistor R4 and the capacitor C1 is grounded.

6. A short-circuit fault latch protection and self-recovery circuit according to claim 5, characterized in that: The NAND gate circuit includes a first NAND gate, a second NAND gate, a third NAND gate and a fourth NAND gate, the input end 1A and the input end 1B of the first NAND gate are connected to the input end 3A of the third NAND gate and the collector of the transistor Q1, the output end 1Y of the first NAND gate is connected to the input end 2A of the second NAND gate, the input end 2B of the second NAND gate is connected to the input end 3B of the third NAND gate, the resistor R4 and the capacitor C1, the output end 2Y of the second NAND gate is connected to the input end 4A and the input end 4B of the fourth NAND gate, the output end of the fourth NAND gate is connected to the resistor R5, and the output end 3Y of the third NAND gate is connected to the third transistor circuit.

7. A short-circuit fault latch protection and self-recovery circuit according to claim 6, characterized in that: The third transistor circuit includes: resistor R6, resistor R7, transistor Q3 and resistor R8, the base of the transistor Q3 is connected to resistor R6, the resistor R6 is connected to the output end 3Y of the third NAND gate, the resistor R7 is arranged between the emitter and the base of the transistor Q3, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is connected in series with the resistor R8 and then connected to the power supply VCC.

8. A short circuit fault latch protection and self-recovery circuit according to claim 7, characterized in that: The collector of the transistor Q3 outputs the low-level LOCK signal or the high-level LOCK signal to the short-circuit protection output circuit.

9. A short-circuit fault latch protection and self-recovery circuit according to claim 1, characterized in that: The short circuit protection output circuit includes: a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C11, a capacitor C12, a diode D11, a PMOS tube Q5 and an NMOS tube Q4; The source of the PMOS tube Q5 is connected to the resistor R11 and then connected to the front stage of the short-circuit protection output circuit. A resistor R12 is arranged between the gate and the source of the PMOS tube Q5. The drain of the PMOS tube Q5 is connected in parallel with a diode D11 and a capacitor C12 and connected to the rear stage of the short-circuit protection output circuit. The cathode of the diode D11 is connected to the drain of the PMOS tube Q5, and the anode of the diode D11 is grounded. One end of the resistor R13 is connected to the gate of the PMOS tube Q5, and the other end is connected to the drain of the NMOS tube Q4. The resistor R14 and the capacitor C11 are connected in parallel and then connected to the gate of the NMOS tube Q4. The source of the NMOS tube Q4, the capacitor C11, the resistor R14 and the capacitor C12 are all grounded.

10. A short circuit fault latch protection and self-recovery circuit according to claim 9, characterized in that: The gate of the NMOS tube Q4 is connected to the high level LOCK signal or the low level LOCK signal.

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