Image sensor and electronic device

Abstract

The utility model provides an image sensor and an electronic device, the image sensor comprises pixel blocks, at least a second type of pixel blocks are defined, and a first type of pixel blocks and / or a third type of pixel blocks are also defined; a first type gain unit, a shared gain unit and a second type gain unit are correspondingly arranged; the image sensor includes a first gain compensation pixel block having a first gain compensation unit to correspond to a shared gain unit; and / or a second gain compensation pixel block with a second gain compensation unit is included, so as to correspond to the shared gain unit. By improving the structure of the image sensor and designing a gain compensation circuit, each pixel block in a pixel array can have an equivalent gain control effect, so that the pixel utilization rate can be improved, and the area waste can be reduced; improvement can be carried out based on an existing virtual region, the area utilization rate is further improved, and the design of a combined circuit with a voltage clamping circuit can be carried out at the same time.

Description

Technical Field

[0001] This new type belongs to the technical field of image acquisition, and particularly relates to an image sensor and an electronic device. Background Art

[0002] An image sensor is an important component of a digital camera. According to different components, it can be divided into two categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor). With the continuous development of CMOS integrated circuit manufacturing technology, especially the design and manufacturing technology of CMOS image sensors, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application values in fields such as machine vision, consumer electronics, high-definition monitoring, and medical imaging.

[0003] Currently, with the development of CMOS image sensor technology, the continuous increase in the number of pixels and the continuous miniaturization of pixel sizes, in the prior art, in order to improve the dynamic range, various schemes for adding different gain functions are often designed in the pixel array. In addition, in the face of various application environments of existing image sensors, the corresponding pixel array will also be designed complexly. As a result, there are often different types of pixel units in the pixel array of CMOS image sensors, resulting in incomplete consistency in the operations that each pixel unit can achieve, which has an adverse impact on the operation control and manufacturing cost of the image sensor and is not conducive to effectively exerting the function of the image sensor.

[0004] Therefore, it is necessary to provide an image sensor and an electronic device to solve the problem of pixel unit consistency in the above-mentioned pixel array in the prior art. Summary of the Utility Model

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide an image sensor and an electronic device for solving the problem of pixel unit consistency in the existing pixel array.

[0006] To achieve the above purpose and other related purposes, the present utility model provides an image sensor, including:

[0007] A plurality of pixel blocks arranged in an array, and each of the pixel blocks is correspondingly configured with a photosensitive unit, a reset unit, a gain unit, an output unit, and a selection unit;

[0008] Wherein, at least a second type of pixel block is defined among the plurality of pixel blocks, and a first type of pixel block and / or a third type of pixel block are also defined among the plurality of pixel blocks;

[0009] The first type of pixel block has a first type of gain unit, the second type of pixel block has a shared gain unit, and the third type of pixel block has a second type of gain unit;

[0010] Wherein, the image sensor includes a first gain compensation pixel block having a first gain compensation unit, and the first gain compensation unit is coupled to the first type of gain unit to correspond to the shared gain unit; and / or, the image sensor includes a second gain compensation pixel block having a second gain compensation unit, and the second gain compensation unit is coupled to the second type of gain unit to correspond to the shared gain unit.

[0011] The present application further provides a control method for an image sensor as described in any one of the above solutions, and the control method includes the following steps:

[0012] Control the opening and / or closing of the gain unit in the pixel block having an equivalent shared gain unit to control the size of the floating diffusion node capacitance accessing the pixel unit, so that the image sensor enters different gain modes, wherein the first type of pixel block realizes the corresponding gain mode based on the first gain compensation pixel block, and the third type of pixel block realizes the corresponding gain mode based on the second gain compensation pixel block.

[0013] The present application further provides an electronic device, including the image sensor as described in any one of the above solutions.

[0014] As described above, the image sensor and the electronic device of the present utility model can, through improving the structure of the image sensor and designing the gain compensation circuit, enable each pixel block in the pixel array to have an equivalent gain control effect, thereby being beneficial to improving pixel utilization rate and reducing area waste; in addition, it can be improved based on the existing virtual area to further improve the area utilization rate. Moreover, the present application can also simultaneously perform the combined circuit design of the voltage clamping circuit to improve the overall performance of the device. Description of the Drawings

[0015] Figure 1 Shown as a basic structural block diagram of an image sensor system.

[0016] Figure 2 Shown as a schematic diagram of a pixel circuit of an image sensor.

[0017] Figure 3 Shown as a schematic diagram of the first gain compensation pixel block provided by an embodiment of the present application.

[0018] Figure 4 Shown as an arrangement schematic diagram of the first clamping circuit provided by an embodiment of the present application.

[0019] Figure 5Shown is a schematic diagram of a voltage clamping circuit provided by an embodiment of the present application.

[0020] Figure 6 Shown is a schematic diagram of a circuit of a first clamping compensation mode provided by an embodiment of the present application.

[0021] Figure 7 Shown is a schematic diagram of a second gain compensation pixel block provided by an embodiment of the present application.

[0022] Figure 8 Shown is a schematic layout of a second clamping circuit provided by an embodiment of the present application.

[0023] Figure 9 Shown is a schematic diagram of a circuit of a second clamping compensation mode provided by an embodiment of the present application.

[0024] Figure 10 Shown is a schematic layout of an image sensor array provided by an embodiment of the present application.

[0025] Figure 11 Shown is a schematic layout of a control circuit provided by an embodiment of the present application.

[0026] Figure 12 Shown is a schematic diagram of a group of focus pixel blocks provided by an embodiment of the present application.

[0027] Description of Component Labels

[0028] 100 - First type pixel block; 101 - First type gain unit; 200 - Second type pixel block; 201 - Shared gain unit; 300 - Third type pixel block; 301 - First type gain compensation unit; 400 - First clamping circuit; 410 - Start control module; 411 - Shared connection structure; 420 - Voltage transfer module; 430 - Output module; 440 - Virtual photosensitive module; 500 - First clamping compensation module; 501 - First clamping module; 502 - First gain matching module; 600 - Third type pixel block; 601 - Third type gain unit; 700 - Second gain compensation module; 701 - Second gain compensation unit; 800 - Second clamping circuit; 900 - First clamping compensation module; 901 - First clamping module; 902 - First gain matching module. Detailed Embodiments

[0029] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] It should be emphasized that the term "comprising / including", as used herein, refers to the presence of features, whole pieces, steps or components, but does not exclude the presence or addition of one or more other features, whole pieces, steps or components.

[0031] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments. When detailing the embodiments of the present novelty, for ease of illustration, the cross-sectional views showing the device structure may be enlarged locally in a non-general proportion. The schematic diagrams are only examples and should not limit the scope of protection of the present utility model herein. In actual production, the three-dimensional spatial dimensions of length, width and depth should be included.

[0032] For convenience of description, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers. The structure in which the described first feature is "above" the second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, "coupled" means that it can be connected directly or indirectly.

[0033] The illustrations provided in this embodiment only schematically illustrate the basic concept of the present novelty. Therefore, only the components related to the present novelty are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, quantities and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. The following will detail the content proposed by the present novelty in conjunction with the accompanying drawings.

[0034] Figure 1 Shown is a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. Additionally, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to implement the control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3... Ry) and columns (C1, C2, C3... Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In some applications, the image sensor acquires and reads image data in a mode specified by the status register and then transmits it to the functional logic unit. In a specific implementation, the readout circuit may include an analog-to-digital conversion (ADC) circuit and other circuits.

[0035] In some applications, the status register may include a programmed selection system for determining whether the readout system exposes and reads out through a rolling shutter mode or a global shutter mode. The functional logic unit may store the original image data or the image data after image processing. In some implementations, the readout circuit may read out one row of image data along the readout column lines at a time. Of course, other ways may also be used to read out the image data. The operation of the control circuit may be determined by the current settings of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some applications, this shutter signal may be a global exposure signal, enabling all pixels of the pixel array to simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal may also be a rolling exposure signal, enabling the pixels of each pixel row of the pixel array to continuously perform exposure and readout operations through the acquisition window.

[0036] Figure 2 Shown is a schematic diagram of a pixel unit in an image sensor. As Figure 2 shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode PD) and a pixel circuit (shown as transistors within the dashed box in the figure). The photodiode may be a buried photodiode (PPD) used in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), connected to the transfer transistor (TX) and the photodiode as Figure 2 shown. In an application example of a stacked structure, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel selection transistor placed on a first circuit chip, and also includes a transfer transistor placed on a second circuit chip. The photodiode in the second circuit chip is connected to the other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between the floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photo charges in response to incident light during the exposure process. The transfer transistor connects to a transfer signal, which controls the transfer transistor to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and responds to the reset signal to reset the sensor pixel circuit. The floating diffusion region is connected to the gate of the source follower transistor. The source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it. The pixel selection transistor is connected between the source follower transistor and the bit line, and realizes pixel selection and readout in response to the pixel selection control signal.

[0037] However, with the development of CMOS image sensor technology, the continuous increase in the number of pixels and the continuous miniaturization of pixel sizes, in the prior art, in order to improve the dynamic range, various schemes with different gain functions are often designed in the pixel array. In addition, in the face of various application environments of existing image sensors, the corresponding pixel array will also be designed complexly. As a result, there are often different types of pixel units in the pixel array of the CMOS image sensor, resulting in incomplete consistency in the operations that each pixel unit can achieve, which has an adverse impact on the operation control and manufacturing cost of the image sensor and is not conducive to effectively exerting the function of the image sensor. This novel type can effectively improve the above problems through the design of the overall structure and operation of the image sensor.

[0038] Embodiment 1:

[0039] Please refer to Figure 3 As shown, this embodiment provides an image sensor. In this embodiment, the image sensor includes a plurality of pixel blocks arranged in an array. Each pixel block is correspondingly configured with a photosensitive unit, a reset unit, a gain unit, an output unit, and a selection unit. Among them, at least a second type of pixel block 200 is defined among the plurality of pixel blocks, and a first type of pixel block 100 is also defined among the plurality of pixel blocks. It should be noted that the above-mentioned various units configured for each pixel block to implement the corresponding functions of the image sensor can be configured according to the existing method, and the traditional functions of each unit can be achieved according to the operation of the existing CMOS image sensor.

[0040] Specifically, the first type of pixel block 100 has a first type of gain unit 101; the second type of pixel block 200 has a shared gain unit 201; in addition, the image sensor further includes a first gain compensation pixel block 300 having a first gain compensation unit 301, wherein the first gain compensation unit 301 is coupled to the first type of gain unit 101 to correspond to the shared gain unit 201; that is, the structure formed by the first gain compensation unit 301 and the first type of gain unit 101 after being coupled has the same gain configuration as the shared gain unit 201, and the gain adjustment that the two can achieve is the same, and corresponding identical gain magnitudes can be formed based on the corresponding control.

[0041] As an example, the first type of pixel block 100 has a first type of reset unit, and the first type of reset unit and the gain unit of the first type of pixel block 100 constitute the first type of gain unit 101.

[0042] Specifically, the first type of reset unit corresponds to the first type of pixel block 100 and can reset the first type of pixel block 100. The gain unit of the first type of pixel block 100 may include a gain control transistor, and the gain of the first type of pixel block 100 is controlled based on the capacitance value. Among them, the first type of reset unit may be a reset transistor connected to the gain control transistor of the first type of pixel block 100, and the reset transistor and the gain control transistor constitute the first type of gain unit 101.

[0043] In a specific example, the first type of reset unit of the first type of pixel block 100 includes a first reset transistor RST1, the gain unit of the first type of pixel block 100 includes a first gain control transistor DCG1, and the first reset transistor RST1 and the first gain control transistor DCG1 form the first type of gain unit 101. The first gain compensation unit 301 of the first gain compensation pixel block 300 includes a second gain control transistor DCG2. The first gain control transistor DCG1 and the second gain control transistor DCG2 are connected in series, and the series node therebetween is coupled to the first reset transistor RST1. Among them, the first gain control transistor DCG1, the second gain control transistor DCG2, and the first reset transistor RST1 share the gain unit 201 correspondingly.

[0044] As an example, the second type of pixel block 200 has a second type of reset unit, and the second type of reset unit and the gain unit of the corresponding second type of pixel block 200 constitute the shared gain unit 201.

[0045] Specifically, the second type of reset unit corresponds to at least two second type of pixel blocks 200 sharing gain, and is used to reset the at least two second type of pixel blocks 200 sharing gain. For example, the second type of reset unit may include a reset transistor connected to the shared node of the interconnected gain units of the second type of pixel blocks 200 sharing gain. The respective gain control transistors of the at least two second type of pixel blocks 200 sharing gain and their shared reset transistor constitute the shared gain unit 201.

[0046] In a specific example, the second type of reset unit of the second type of pixel block 200 includes a reset transistor RST. The gain units of the two second type of pixel blocks 200 sharing gain each include a gain control transistor DCG, and the three form the shared gain unit 201. Further, the two second type of pixel blocks 200 may be pixel blocks located in adjacent rows and in the same column. Of course, the sharing method and quantity are set according to actual situations.

[0047] As an example, both the first type of pixel block 100 and the second type of pixel block 200 further include a photosensitive transmission unit and a readout unit. Among them, the photosensitive transmission unit at least includes a photosensitive element and further includes a transmission element, and the readout unit includes an output element and further includes a selection element. In one example, the photosensitive transmission units of the first type of pixel block 100 and the second type of pixel block 200 both include a photoelectric conversion element (such as a photodiode PD) and a corresponding transmission transistor TX, and the readout units both include a source follower transistor SF. Further, each pixel block is configured with a selection transistor RS. As Figure 3 shown, in this example, the selection transistor RS adopts a shared design method, that is, different pixel blocks share a selection transistor RS. For example, adjacent two rows share a selection transistor RS to enable each pixel block to output. Further, it can be that two adjacent pixel blocks that do not share a reset transistor RST share the selection transistor RS, that is, the reset transistor RST and the selection transistor RS are cross-shared to form a pixel column. In addition, the figure shows four photodiodes PD1 to PD4 and four transmission transistors TX1 to TX4.

[0048] As an example, the first gain compensation pixel block 300 further includes a first compensation readout unit. The first compensation readout unit includes a source follower transistor SF, and the control terminal of the source follower transistor SF is coupled to the first gain compensation unit 301 (such as the second gain control transistor DCG2) and adopts a source-drain common connection method.

[0049] Specifically, the control terminal of the second gain control transistor DCG2 can receive a gain control signal dcg, and the other two ends are respectively connected to one end of the first gain control transistor DCG1 of the first type of pixel block 100 and the gate of the source follower transistor SF of the first compensation readout unit. The source and drain of the source follower transistor SF are commonly connected. For example, the common connection terminal can provide a power supply voltage PIXVDD, thereby facilitating the realization of the gain compensation function.

[0050] As an example, the first gain compensation pixel block 300 further includes a virtual photosensitive transmission unit. The output terminal of the virtual photosensitive transmission unit is coupled to one end of the first gain compensation unit 301 and the control terminal of the first compensation readout unit. For example, they are both coupled to one end of the second gain control transistor DCG2 and the control terminal of the source follower transistor SF to form the first gain compensation pixel block 300 corresponding to the first type of pixel block 100.

[0051] In one example, the virtual photosensitive transmission unit can include a virtual photosensitive element, a corresponding transmission transistor, and a floating diffusion node, where the floating diffusion node serves as the output terminal of the virtual photosensitive transmission unit; the number of virtual photosensitive elements and corresponding transmission transistors can be one or more, designed according to actual needs.

[0052] Furthermore, the virtual photosensitive element, transfer transistor, and floating diffusion node of the virtual photosensitive transfer unit can correspond one-to-one with the photosensitive element, transfer transistor, and floating diffusion node of the first type of pixel block. The number and structure of both are the same, and they are fabricated based on the same process. For example, both are of a 2×2 sharing structure. Further, a 2×4 pixel block combination can be formed based on the connection method of shared gain for operation.

[0053] Please refer to Figure 7 As shown, this embodiment provides another image sensor. In this example, the image sensor includes a plurality of pixel blocks arranged in an array, and each pixel block is correspondingly configured with a photosensitive unit, a reset unit, a gain unit, an output unit, and a selection unit. Among them, at least a second type of pixel block 200 is defined in the plurality of pixel blocks, and a third type of pixel block 600 is also defined in the plurality of pixel blocks. It should be noted that Figure 7 the image sensor of the example shown is similar to Figure 3 the image sensor of the example shown. Similar structures can be referred to the above description and will not be elaborated here. The main differences between the two examples are described below.

[0054] Specifically, the second type of pixel block 200 has a shared gain unit 201; the third type of pixel block 600 has a second type of gain unit 601; in addition, the image sensor further includes a second gain compensation pixel block 700 having a second gain compensation unit 701, where the second gain compensation unit 701 is coupled to the second type of gain unit 601 to correspond to the shared gain unit 201; that is, the structure formed by the coupling of the second gain compensation unit 701 and the second type of gain unit 601 has the same gain configuration as the shared gain unit 200, and the same gain adjustment can be achieved by both, and the same gain magnitude can be formed based on the corresponding control.

[0055] It should be noted that when the image sensor has the second type of pixel block 200, it can also have the first type of pixel block 100 and the third type of pixel block 600 at the same time. Correspondingly, it has the first gain compensation pixel block 300 and the second gain compensation pixel block 700 at the same time to respectively perform gain compensation on the two types of pixel blocks with incomplete gain, so that each pixel block in the pixel array can have an equivalent shared gain unit.

[0056] Specifically, it can be combined with Figure 3 and Figure 7As shown, taking a pixel array composed of eight rows of pixel blocks as an example, the 0th row is a first-type pixel block 100, the 7th row is a third-type pixel block 600, and the remaining 1st to 6th rows are second-type pixel blocks. Further, a corresponding row of first gain compensation pixel blocks 300 is arranged above the 0th row of the pixel array, such as the -1st row. Correspondingly, a corresponding row of second gain compensation pixel blocks 700 is arranged below the 7th row of the pixel array, such as the 8th row, to achieve consistent gain for each pixel block. That is to say, one end of the pixel array has a row of first-type pixel blocks, and the other end has a row of third-type pixel blocks. The gains of these two types of pixel blocks are incomplete compared with other pixel blocks, and the gain of the entire pixel array can be made complete based on the first gain compensation pixel blocks and the second gain compensation pixel blocks.

[0057] As an example, for the pixel array of an image sensor, a group composed of two of the three pixel blocks shares the same reset transistor, and another group composed of one pixel block in this group and the remaining one pixel block shares the same selection transistor; in a further example, two groups composed of adjacent pixel blocks among three adjacent pixel blocks in the same column share the same selection transistor and the same reset transistor respectively.

[0058] As an example, the gain units of the third-type pixel block 600 form second-type gain units 601, and the gain units include gain control transistors, and the gain control transistors form second-type gain units 601.

[0059] Specifically, the second gain compensation pixel block 700 further has a third-type reset unit, corresponding to the third-type pixel block 600, which can reset the third-type pixel block 600, that is, the third-type pixel block is reset based on the compensation pixel block; in addition, the gain units of the third-type pixel block 600 may include gain control transistors to control the gain magnitude of the third-type pixel block 600. Among them, the third-type reset unit may be a reset transistor connected to the gain control transistor of the second gain compensation pixel block 700.

[0060] In a specific example, the third-type reset unit of the second gain compensation pixel block 700 includes a second reset transistor RST2, and the second gain compensation pixel block includes a fourth gain control transistor DCG4, and the two form a second-type gain unit; the gain units of the third-type pixel block 600 include a third gain control transistor DCG3; the third gain control transistor DCG3 and the fourth gain control transistor DCG4 are connected in series, and the series node between the two is coupled to the second reset transistor RST2. Among them, the third gain control transistor DCG3, the fourth gain control transistor DCG4, and the second reset transistor RST2 share the gain unit 201 correspondingly.

[0061] As an example, the second gain compensation pixel block 700 further includes a second compensation readout unit. The second compensation readout unit includes a source follower transistor SF. The control terminal of the source follower transistor SF is coupled to the second gain compensation unit 701 (such as the fourth gain control transistor DCG4) and is connected in a source-drain common connection manner.

[0062] Specifically, the control terminal of the fourth gain control transistor DCG4 can receive a gain control signal dcg. The other two ends are respectively connected to one end of the third gain control transistor DCG3 of the third type pixel block 600 and the gate of the source follower transistor SF of the second compensation readout unit. The source and drain of the source follower transistor SF are connected in common. For example, the common connection terminal can provide a power supply voltage PIXVDD, thereby facilitating the realization of the gain compensation function.

[0063] In addition, the second gain compensation pixel block 700 further includes a virtual photosensitive transfer unit, whose structure is the same as that of the first gain compensation pixel block 300 and will not be described in detail here. That is, in the entire pixel array, the structures and numbers of the photosensitive elements and transfer elements of the first to third type pixel blocks and the first and second gain compensation pixel blocks can be designed to be the same. Further, the number and structural layout of the gain control transistors of the gain units of the three type pixel blocks and the gain compensation pixel blocks and the source follower transistors in the readout units in the substrate can also be designed to be the same. Further, the same structure can also be fabricated through the same mask.

[0064] Please refer to Figure 4 and Figure 5 As shown, as an example, the image sensor further includes a first clamping circuit 400 for voltage control of the selected output bit line pix. In this example, the first clamping circuit 400 corresponds to the first type pixel block 100 one by one, so as to facilitate the design of the entire image sensor array structure.

[0065] As an example, as Figure 5 shown, a design of a voltage clamping circuit is provided. The voltage clamping circuit includes: a start control module 410, a voltage transfer module 420, and an output module 430, where:

[0066] The startup control module 410 is used to provide a startup voltage; the control terminal of the voltage transfer module 420 receives the transfer voltage Vclamp, and is used to receive the startup voltage and generate a clamped voltage under the control of the transfer voltage Vclamp. In this example, the voltage PIXVDD at the receiving terminal of the startup control module 410 is defined as the startup voltage, and this voltage is provided to the voltage transfer module 420 through the startup control module 410 to start the voltage transfer module 420. Based on the transfer voltage control, the voltage formed at the output terminal of the voltage transfer module 420 is the clamped voltage. Among them, the first terminal of the voltage transfer module 420 is coupled to the startup control module 410 to receive the corresponding startup voltage, and the second terminal is used to output the clamped voltage; the control terminal of the output module 430 receives the output control signal Vc, the first terminal is coupled to the second terminal of the voltage transfer module 420, and the second terminal is coupled to the output bit line Pix, and is used to output the clamped voltage to the output bit line Pix, so as to control the output bit line voltage based on the magnitude of the transfer voltage Vclamp.

[0067] As an example, the voltage transfer module 420 includes at least one voltage transfer transistor, Figure 4 which is shown as two voltage transfer transistors M4 and M5 in the figure. Among them, when there are multiple voltage transfer transistors, the voltage transfer transistors are arranged in parallel to respectively receive the startup voltage provided by the startup control module 110. Among them, the control terminal of each voltage transfer transistor receives the transfer voltage Vclamp, the first terminal is coupled to the startup control module 410, and the second terminal is coupled to the first terminal of the output module 430. For example, the voltage transfer transistor can be a source follower transistor SF, and in a specific implementation, it is an NMOS transistor.

[0068] As an example, the output module 430 includes a selection output transistor M6. The control terminal of the selection output transistor receives the output control signal Vc, the first terminal is coupled to the second terminal of the voltage transfer module 420, such as the first terminal is coupled to the second terminal of the voltage transfer transistor, and the second terminal is coupled to the output bit line Pix. For example, the selection output transistor can be a pixel selection transistor RS, and in a specific implementation, it is an NMOS transistor.

[0069] As an example, the voltage clamping circuit further includes a virtual photosensitive module 440. The virtual photosensitive module 440 includes a photoelectric conversion unit PD, a transmission unit TX, and a floating diffusion unit that are sequentially coupled. Among them, the floating diffusion unit is coupled to the startup voltage providing node of the startup control module 410 and the startup voltage receiving node of the voltage transfer module 420. Among them, the number of the photoelectric conversion unit PD and the transmission unit TX can be set according to the actual situation; further, the virtual photosensitive module included in the voltage clamping circuit has the same structural design as the virtual photosensitive transmission unit of the gain compensation pixel block, so as to be implemented based on the same and have the same layout.

[0070] In one example, the virtual photosensitive module may further include a plurality of virtual photosensitive sub-modules. Figure 4 Two virtual photosensitive sub-modules 440_1 and 440_2 are shown in Figure 4 , corresponding to sub-floating diffusion nodes respectively. Among them, the number of photoelectric conversion units PD and transmission units TX in each sub-module can be set according to the actual situation. The above arrangement is conducive to realizing the correspondence between the virtual photosensitive module and the pixel unit photosensitive module, so that the virtual photosensitive module and the pixel unit photosensitive module of the voltage clamping circuit can be fabricated simultaneously. Further, each transistor and node in the voltage clamping circuit can correspond one-to-one and be the same as each transistor and node in the pixel circuit of the pixel unit, and its own function can be realized through different electrical connections when controlling signals.

[0071] Continue to refer to Figure 5 As shown, as an example, the start control module 410 includes:

[0072] The first start voltage providing node FD1 is coupled to the first end of the voltage transfer module 420. For example, the first start voltage providing node FD1 is coupled to the first end of the voltage transfer transistor M4.

[0073] The first voltage providing module includes a first transistor M1. The first transistor M1 is coupled between the first voltage source and the first start voltage providing node FD1. Among them, the first transistor M1 can be a conversion gain control transistor. In a specific implementation, it is an NMOS transistor.

[0074] The second start voltage providing node FD2 is coupled to the first end of the voltage transfer module 420. For example, the second start voltage providing node FD2 is coupled to the first end of the voltage transfer transistor M5.

[0075] The second voltage providing module includes a second transistor M2 and a third transistor M3 connected in series, and is coupled between the second voltage source and the second start voltage providing node FD2. The second transistor M2 and the third transistor M3 can be a conversion gain control transistor and a reset transistor respectively. In a specific implementation, both of them are NMOS transistors. In addition, the second voltage source and the first voltage source can be the same voltage source, both being PIXVDD.

[0076] Among them, the control end of the first transistor M1 is coupled to the first voltage source PIXVDD, the first end is coupled to the first start voltage providing node FD1, and the second end of the first transistor M1 is coupled to the shared node between the second end of the second transistor M2 and the first end of the third transistor M1. The control ends of the second transistor M2 and the third transistor M3 are both coupled to the second voltage source PIXVDD. The first end of the second transistor M2 is further coupled to the second start voltage providing node FD2, and the second end of the third transistor M3 is further coupled to the second voltage source PIXVDD.

[0077] In one example, a shared connection structure 411 is further provided between a first start voltage supply node FD1 and a second start voltage supply node FD2. For example, the shared connection structure 411 can be a metal interconnect line. In other examples, the shared connection structure 411 can further include multiple metal interconnect lines and switches connected in series between the interconnect lines to control whether electrical connection is made between the two through the switches.

[0078] Please refer to Figure 6 As shown, in one implementation, the first clamping circuit 400 corresponds to the first type of pixel block 100 one by one, and the two together form a first clamping compensation circuit 500. The first clamping compensation circuit 500 includes a first clamping module 501 and a first gain compensation module 502, and the first clamping module 501 and the first gain compensation module 502 share an output bit line. Here, sharing can be considered as corresponding together; where:

[0079] The first clamping module 501 includes a first start control module, a first voltage transfer module, and a first output module. The first output module is electrically connected to the output bit line pix0. The first gain compensation module 502 includes a first gain matching module and a first source follower module. The control end of the first source follower module is coupled to the first gain matching module, the first end is coupled to the first voltage source, and the second end is electrically disconnected from the corresponding output bit line pix0.

[0080] In a specific example, the first start control module includes a second transistor M2 and a third transistor M3 connected in series, coupled between the start voltage PIXVDD and the floating diffusion node. Further, the control ends of the second transistor M2 and the third transistor M3 and the first end of the series structure receive the start voltage PIXVDD, and the second end of the series structure is coupled to the first voltage transfer module; the second transistor M2 and the third transistor M3 can be a conversion gain control transistor and a reset transistor respectively. For example, both of them are NMOS transistors.

[0081] The first voltage transfer module includes a fifth transistor M5, which can be a source follower transistor, with the gate connected to the transfer control voltage Vclamp, the first end coupled to the floating diffusion node corresponding to the first start control module, that is, the first end of the second transistor M2, and the second end of the fifth transistor M5 is coupled to the first output module; the first output module includes a sixth transistor M6, which can be a selection transistor, with the control end coupled to the selection control signal Vc, the first end coupled to the first voltage transfer module, and the second end connected to the output bit line Pix. The first gain compensation module 502 includes a first gain matching module and a first source follower module. The control end of the first source follower module is coupled to the first gain matching module, the first end is coupled to the first voltage source, and the second end is electrically disconnected from the output bit line.

[0082] In a specific example, the first gain matching module of the first gain compensation module 502 includes a first transistor M1. The first transistor M1 is coupled between the first type pixel block 100 and the floating diffusion node corresponding to the first gain matching module. The control terminal of the first transistor M1 receives a gain control signal dcg. Among them, the first transistor M1 can be a conversion gain control transistor. For example, it is an NMOS transistor.

[0083] The first source follower module of the first gain compensation module 502 includes a fourth transistor M4. The control terminal is coupled to the floating diffusion node corresponding to the first gain matching module and the first gain matching module. The first terminal is coupled to the first power supply voltage, and the second terminal is floating. For example, the fourth transistor M4 includes a source follower transistor. The gate is connected to the floating diffusion node corresponding to the first gain matching module and the first terminal of the first transistor M1. The first terminal is coupled to the first power supply voltage, and the second terminal is floating to perform gain compensation under the control of the gain control signal.

[0084] In this example, the first clamping compensation circuit 500 further includes a first virtual photosensitive unit and a second virtual photosensitive unit to form a first floating diffusion node and a second floating diffusion node, which are respectively connected to the first clamping module 501 and the first gain compensation module 502. Further, the first virtual photosensitive unit and the second virtual photosensitive unit are consistent with the structural layout and the number of transistors of the photosensitive transmission units of the first type pixel block, the second type pixel block, and the third type pixel block, facilitating preparation based on the same process.

[0085] As an example, as Figure 8 shown, the image sensor further includes a second clamping circuit 800 for voltage control of the selected output bit line pix. In this example, the second clamping circuit 800 corresponds to the third type pixel block 100 one by one to facilitate the design of the entire image sensor array structure. It should be noted that the second clamping circuit 800 can adopt the same structure as the first clamping circuit 400 as Figure 5 shown.

[0086] In an example, the second clamping circuit 800 corresponds to the third type pixel block 600 one by one to form a second clamping compensation circuit. The second clamping compensation circuit 900 includes a second clamping module 902 and a second gain compensation module 901, and the second clamping module and the second gain compensation pixel block share the output bit line. Among them:

[0087] The second gain compensation module 901 includes a second gain matching module and a second source follower module. The second gain matching module is coupled to the floating diffusion node. For example, the second gain matching module includes an eighth transistor M8 and a ninth transistor M9 connected in series. The control terminal of the eighth transistor M8 receives the gain control signal dcg, the control terminal of the ninth transistor M9 receives the reset signal rst, and the second terminal of the ninth transistor M9 receives the reset drain control signal rstd. The connection node between the eighth transistor M8 and the ninth transistor M9 is connected to the gain unit of the third type pixel block for gain compensation. Among them, the eighth transistor M8 and the ninth transistor M9 can be a conversion gain control transistor and a reset transistor respectively. For example, both of them are NMOS transistors. The second source follower module includes an eleventh transistor M11, which can be a source follower transistor. The control terminal is connected to the corresponding floating diffusion node of the second gain matching module, the first terminal is coupled to the second power supply voltage, and the second terminal is floatingly arranged to perform gain compensation under the control of the gain control signal. The second clamping module includes a second start control module, a second voltage transfer module and a second output module. The second output module is electrically connected to the output bit line pix0.

[0088] In a specific example, the second start control module includes a seventh transistor M7, the control terminal and the first terminal receive the start voltage PIXVDD. The second voltage transfer module includes a tenth transistor M10, which can be a source follower transistor. The gate is connected to the transfer control voltage Vclamp. The first terminal is coupled to the corresponding floating diffusion node of the second gain matching module and the first terminal of the seventh transistor M7, and the second terminal is coupled to the first output module. The second output module includes a twelfth transistor M12, which can be a selection transistor. The control terminal is connected to the coupled selection control signal Vc, the first terminal is coupled to the first voltage transfer module, and the second terminal is connected to the output bit line. It should be noted that based on the above design method of the clamping compensation circuit, the voltage clamping function and the gain compensation function can be realized based on the pixel structure configuration corresponding to the pixel block combination that shares the gain in the pixel unit array.

[0089] Please refer to Figure 10 As shown, as an example, the image sensor 000 includes a pixel area 10 and a first virtual area 30_1 located outside the pixel area 10 and / or a second virtual area 30_2 located outside the pixel area 10. In one example, when both exist, they are located on opposite sides of the pixel area 10. It should be noted that the periphery here can be a whole circle area around the pixel area or a part of the area around it.

[0090] There is a first boundary between the pixel area 10 and the first virtual area 30_1. The first boundary includes a first type pixel block 100 in the pixel area 10 and a first gain compensation pixel block 300 in the first virtual area 30_1. See Figure 3As shown, it can be considered that the top of the pixel region 10 has a first type of pixel block 100, as shown in the 0th row corresponding to Figure 3 In the figure, correspondingly, the first virtual region 30_1 has a first gain compensation pixel block 300, as shown in the -1th row corresponding to Figure 3 In the figure. Thus, the incomplete first type of pixel block 100 in the pixel region 10 can be compensated by the first gain compensation pixel block 300 located in the first virtual region 30_1, so that the entire pixel region 10 has the same gain effect as the second type of pixel block 200.

[0091] There is a second boundary between the pixel region 10 and the second virtual region 30_2, and this second boundary includes a third type of pixel block 600 located in the pixel region 10 and a second gain compensation pixel block 700 located in the second virtual region 30_2. Refer to Figure 7 As shown, it can be considered that the bottom end of the pixel region 10 has a third type of pixel block 600, as shown in the 7th row corresponding to Figure 7 In the figure, correspondingly, the second virtual region 30_2 has a second gain compensation pixel block 700, as shown in the 8th row corresponding to Figure 7 In the figure. Thus, the incomplete third type of pixel block 600 in the pixel region 10 can be compensated by the second gain compensation pixel block 700 located in the second virtual region 30_2, so that the entire pixel region 10 has the same gain effect as the second type of pixel block 200.

[0092] Continuing to refer to Figure 10 As shown, the image sensor 000 further includes a black pixel region 20, and the black pixel region 20 is arranged at intervals with the pixel region 10. Among them, the black pixel region 20 can adopt the design of the existing black pixel region BLC and complete the corresponding dark current correction function. The pixel structure of the black pixel region 20 in the semiconductor substrate is the same as the pixel structure of the pixel units in the pixel region 10. A light-shielding material layer can be configured on one side of the black pixel region 20 facing the incident light direction to realize its own function.

[0093] In an example, when there is a first virtual region 30_1, the black pixel region 20 is located on the side of the first virtual region 30_1 away from the pixel region 10, and there is a third boundary between the black pixel region 20 and the first virtual region 30_1. This third boundary includes a third type of pixel block 600 located in the black pixel region 20 and a second gain compensation pixel block 700 located in the first virtual region 30_1; among them, refer to Figure 7 As shown, it can be considered that the bottom end of the black pixel region 20 has a third type of pixel block 600, as shown in the 7th row corresponding to Figure 7 In the figure, correspondingly, the first virtual region 30_1 has a second gain compensation pixel block 700, as shown in the Figure 7As shown in the 8th row of , the incomplete third-type pixel block 600 in the black pixel region 20 can be compensated by the second gain compensation pixel block 700 located in the first virtual region 30_1, so that the entire black pixel region 20 has the same gain effect as the second-type pixel block 200.

[0094] In one example, the image sensor 000 includes a third virtual region 30_3 on the side of the black pixel region 20 away from the pixel region 10. There is a fourth boundary between the black pixel region 20 and the third virtual region 30_3. The fourth boundary includes the first-type pixel block 100 in the black pixel region 20 and the first gain compensation pixel block 300 in the third virtual region 30_1.

[0095] Specifically, it can be considered that the top of the black pixel region 20 has the first-type pixel block 100, as shown in the 0th row of . Correspondingly, the third virtual region 30_3 has the first gain compensation pixel block 300, as shown in the -1th row of . Figure 3 Thus, the incomplete first-type pixel block 100 in the black pixel region 20 can be compensated by the first gain compensation pixel block 300 in the third virtual region 30_3, so that the entire black pixel region 20 has the same gain effect as the second-type pixel block 200. Figure 3 As an example, the first virtual region 30_1 further includes a first clamping circuit arrangement region.

[0096] Specifically, the pixel region 10 has the first-type pixel block 100, the first virtual region 30_1 has the first gain compensation pixel block 300, and the first virtual region 30_1 further has the first clamping circuit 400. In a further example, the first clamping circuit 400 correspondingly forms the first clamping compensation circuit 500. That is, the first virtual region 30_1 includes the first clamping module 501 and the first gain compensation module 502. In this example, the first gain compensation module 502 functions as the first gain compensation pixel block 300 in the first virtual region 30_1 to achieve the gain compensation function.

[0097] In a further example, the first virtual region 30_1 includes a first sub-region and a second sub-region. The first gain compensation module 502 is located in the first sub-region, and the first clamping circuit arrangement region is located in the second sub-region and extends to the first sub-region. Among them, the first clamping module 501 is located in the first sub-region. That is, the first clamping circuit arrangement region includes the first clamping module 501 as a form of the clamping circuit, and may also include other forms of clamping circuits, such as the clamping circuit shown in .

[0098] In a further example, the first virtual region 30_1 includes a first sub-region and a second sub-region. The first gain compensation module 502 is located in the first sub-region, and the first clamping circuit arrangement region is located in the second sub-region and extends to the first sub-region. Among them, the first clamping module 501 is located in the first sub-region. That is, the first clamping circuit arrangement region includes the first clamping module 501 as a form of the clamping circuit, and may also include other forms of clamping circuits, such as the clamping circuit shown in , which is equivalent to Figure 6 the clamping circuit shown, which is equivalent to Figure 6A part of the clamping circuit shown is used as a clamp (the first clamping module 501), and another part is used for gain compensation (the first gain compensation module 502). Thus, in the case of having a clamping circuit, gain compensation can be performed without wasting chip area.

[0099] Based on the above design, in the first virtual area 30_1, virtual pixels for gain compensation of the pixel area 10 (the first gain compensation module 502) are arranged, and a clamping circuit for controlling the column line voltage (the first clamping module 501) is also arranged. Further, the virtual pixels for pixel compensation and the virtual pixels for voltage clamping together form a pixel block structure corresponding to the pixel unit (the first clamping compensation circuit 500).

[0100] In this example, Dum rows (virtual pixels, the first virtual area 30_1) that originally exist in the overall pixel array are designed as special TOP dummy border pixels and BTM dummy border pixels at the boundary. In the modified border pixels, half are used for gain compensation to make the low gain of the pixels in the pixel area at the boundary normal, and the other half retains the clamping structure without affecting the clamping function. Without additional layout area (especially for mobile phone products that are very sensitive to cost), the problem that the low gain of the border pixels in the pixel area of the pixel array is different from that of the normal pixels and cannot be used can be solved.

[0101] As an example, the second virtual area 30_2 further includes a second clamping circuit arrangement area.

[0102] Specifically, the pixel area 10 has the first type of pixel block 100, the second virtual area 30_2 has the second gain compensation pixel block 700, and the second virtual area 30_2 also has the second clamping circuit 800. In a further example, the second clamping circuit 800 correspondingly forms the second clamping compensation circuit 900, that is, the second virtual area 30_2 includes the second clamping module 902 and the second gain compensation module 901. Among them, in this example, the second gain compensation module 901 serves as the second gain compensation pixel block 700 of the first virtual area 30_1.

[0103] In a further example, the second virtual area 30_2 includes a fourth sub-region and a fifth sub-region. The second gain compensation module 901 is located in the fourth sub-region, and the second clamping circuit arrangement area is located in the fifth sub-region and extends to the fourth sub-region. Among them, the second clamping module 902 is located in the fourth sub-region. The description of the specific design is similar to the arrangement of the first clamping circuit, which can be referred to the above description and will not be elaborated here.

[0104] As an example, the third virtual area 30_3 further includes a third clamping circuit arrangement area.

[0105] Specifically, when the image sensor further has a black pixel region 20, the black pixel region 20 has a first type of pixel block 100, the third virtual region 30_3 has a first gain compensation pixel block 300, and the third virtual region 30_3 further has a first clamping circuit 400. In a further example, the first clamping circuit 400 correspondingly forms a first clamping compensation circuit 500, that is, the third virtual region 30_3 includes a first clamping module 501 and a first gain compensation module 502. Among them, in this example, the first gain compensation module 502 serves as the first gain compensation pixel block 300 of the first virtual region 30_1.

[0106] In a further example, the third virtual region 30_3 includes a sixth sub-region and a seventh sub-region. The first gain compensation module 501 is located in the sixth sub-region, and the third clamping circuit arrangement region is located in the seventh sub-region and extends to the sixth sub-region. Among them, the first clamping module 502 is located in the sixth sub-region. The description of the specific design is similar to the arrangement of the first clamping circuit, which can be referred to the above description and will not be elaborated here.

[0107] In an example, when the image sensor further has a black pixel region 20, the first virtual region 30_1 further has a second clamping circuit 800. In a further example, the second clamping circuit 800 correspondingly forms a second clamping compensation circuit 900, that is, the first virtual region 30_1 includes a second clamping module 902 and a second gain compensation module 901. Among them, in this example, the second gain compensation module 901 serves as the second gain compensation pixel block 700 of the first virtual region 30_1. In a further example, the first virtual region 30_1 further includes a third sub-region, and among them, the second gain compensation pixel block 700 located in the first virtual region 30_1 is arranged in the third sub-region. At this time, the first clamping circuit can also extend from the second sub-region to the third sub-region at the same time.

[0108] Please refer to Figure 11 As shown, the image sensor further includes a control and drive circuit corresponding to each region.

[0109] In an example, the control and drive circuit 001 includes:

[0110] A pixel region drive circuit 40 corresponding to the pixel region 10; a black pixel drive circuit 50 corresponding to the black pixel region 20; and a virtual region drive circuit corresponding to the virtual region.

[0111] In a specific example, the virtual region drive circuit further includes:

[0112] A first virtual driving circuit 60_1, a second virtual driving circuit 60_2, and a third virtual driving circuit 60_3 corresponding to each sub-region of the first virtual region 30_1; a fourth virtual driving circuit 60_4 and a fifth virtual driving circuit 60_5 corresponding to each sub-region of the second virtual region 30_2; a sixth virtual driving circuit 60_6 and a seventh virtual driving circuit 60_7 corresponding to each sub-region of the third virtual region 30_3.

[0113] Specifically, the specific design method of the driving circuit can adopt the design of the existing image sensor driving stage xdec, and it can provide control signals to realize the control of different types of circuits in the corresponding region.

[0114] Please refer to Figure 12 As shown, as an example, the pixel region array of the image sensor further includes a focusing pixel group 002 composed of multiple pixel blocks. The pixel blocks of the focusing pixel group have m rows and n columns, and both m and n are integers greater than 1. Among them, the data processing period of the black pixel region 20 of the image sensor is a processing unit composed of m rows and n columns of black pixel blocks.

[0115] In one example, a focusing pixel group 002 includes a plurality of image pixels 70 and a plurality of focusing pixels 80 to implement phase focusing based on the focusing pixels 80. Among them, the focusing pixels 80 can adopt the existing design.

[0116] In this example, for the black pixel region 20, due to the adoption of the gain compensation design in the present application, therefore, all the pixels in the entire black pixel region 20 can participate in the BLC calculation without wasting the data information in this region. That is, based on the design of the present application, it can be realized that the pixel data in the black pixel region are all used for data processing. Further, for an image sensor with a phase focusing function, for example, having the focusing pixel group 002 in this example, the focusing repetition period is m rows and n columns. When data processing is performed on the corresponding melanin pixel region 20, preferably the data processing period is m rows and n columns, so as to be conducive to obtaining a prepared BLC processing result. In particular, based on the design of the present application, due to the adoption of the gain compensation design, all the data in the black pixel region can be used. Otherwise, for such an image sensor with a focusing pixel group, it will cause the data of the entire corresponding period (m rows and n columns) at the upper and lower boundaries of the black pixel region to be unusable due to gain defects, so that a large number of melanin pixels in the entire black pixel region are wasted more, which is not conducive to BLC processing.

[0117] Embodiment 2:

[0118] This embodiment also provides a control method for an image sensor. The control method provided in this embodiment is applicable to the image sensor described in any of the above solutions. The control method includes the following steps:

[0119] Control the turning on or off of the gain units in a pixel block with an equivalent shared gain unit to control the size of the floating diffusion node capacitance connected to the selected pixel block, so that the image sensor enters different gain modes. Among them, the first type of pixel block realizes the corresponding gain mode based on the first gain compensation pixel block, and the third type of pixel block realizes the corresponding gain mode based on the second gain compensation pixel block. The equivalent shared gain unit refers to the shared gain unit, the gain unit after being compensated by the first gain compensation unit for the first type of gain unit, and the gain unit after being compensated by the second gain compensation unit for the second type of gain unit.

[0120] As an example, different gain modes include at least one of the first gain mode, the second gain mode, and the third gain mode, where: in the first gain mode, the gain units of the selected pixel block are turned off; in the second gain mode LCG1, the gain units of the selected pixel block are turned on and the gain units of the pixel block with a shared gain unit are turned off, only the DCG of the current row itself is conducted, and the other DCG of share is turned off; in the third gain mode LCG0, the gain units of the selected pixel block and the pixel block with a shared gain unit with it are both turned on, and both DCG switches of share are conducted. Specifically, based on the design of the present application, all pixel blocks of the entire pixel array can achieve the above three gain modes. Among them, Figure 3 and Figure 7 the control signals in the example row are given, and the gain control can be achieved by using the corresponding control signals.

[0121] As an example, the control method further includes:

[0122] Provide a control signal to the voltage clamping circuit to achieve the control of the corresponding output bit line. Among them, in this example, the corresponding voltage clamping circuit provides the corresponding voltage to achieve the clamping control. For example, at least provide the transfer voltage Vclamp to the gate of the corresponding source follower transistor and provide the output control signal Vc to the gate of the corresponding pixel selection transistor, and obtain the clamping voltage based on the size of Vclamp for bit line control.

[0123] Embodiment 3:

[0124] The present invention also provides an electronic device, including the image sensor described in any one of the above solutions. The electronic device can be a security monitoring device, a vehicle-mounted electronic device, a mobile phone camera, a machine vision device, etc. The image sensor based on the present invention can obtain high-quality image information, and it can also be a device for infrared utilization.

[0125] In summary, for the image sensor and electronic device of the present utility model, through the improvement of the image sensor structure and the design of the gain compensation circuit, each pixel block in the pixel array can have an equivalent gain control effect, which is conducive to improving the pixel utilization rate and reducing area waste. In addition, it is possible to improve the area utilization rate by further improving based on the existing virtual area. Moreover, the present application can also perform the combined circuit design of the voltage clamping circuit to improve the overall performance of the device. Therefore, the present utility model effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0126] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. All equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that: The method comprises a plurality of pixel blocks arranged in an array, each of the pixel blocks being correspondingly configured with a photosensitive unit, a reset unit, a gain unit, an output unit and a selection unit, wherein at least a second type of pixel block is defined among the plurality of pixel blocks, and a first type of pixel block and / or a third type of pixel block is also defined among the plurality of pixel blocks; The first type pixel block has a first type gain unit, the second type pixel block has a shared gain unit, and the third type pixel block has a second type gain unit; Wherein, the image sensor includes a first gain compensation pixel block having a first gain compensation unit, and the first gain compensation unit is coupled to the first type of gain unit to correspond to the shared gain unit; and / or, the image sensor includes a second gain compensation pixel block having a second gain compensation unit, and the second gain compensation unit is coupled to the second type of gain unit to correspond to the shared gain unit.

2. The image sensor according to claim 1, wherein: The first type pixel block has a first type reset unit, and the first type reset unit and the gain unit of the first type pixel block constitute the first type gain unit; and / or, the gain unit of the third type pixel block constitutes the second type gain unit; and / or, the second type pixel block has a second type reset unit, and the gain units of the second type pixel blocks for gain sharing and the second type reset unit shared by the second type pixel blocks constitute the shared gain unit; and / or, the first type pixel block, the second type pixel block and the third type pixel block all include a photosensitive transfer unit and a readout unit; and / or, the image sensor includes a pixel array composed of the pixel blocks, and the pixel blocks corresponding to the pixel columns are arranged in a cross-sharing manner of reset units and readout units; and / or, the first gain compensation pixel block and the second gain compensation pixel block both include virtual photosensitive transfer units.

3. The image sensor according to claim 2, wherein: The first type reset unit of the first type pixel block includes a first reset transistor, the gain unit of the first type pixel block includes a first gain control transistor, and the first gain compensation unit of the first gain compensation pixel block includes a second gain control transistor, wherein the first gain control transistor and the second gain control transistor are connected in series and a series node therebetween is coupled to the first reset transistor.

4. The image sensor according to claim 3, wherein: The first gain compensation pixel block further includes a first compensation readout unit. The first compensation readout unit includes a source follower transistor. The control terminal of the source follower transistor is coupled to the first gain compensation unit in a source-drain common connection manner.

5. The image sensor according to claim 2, wherein: The gain unit of the third type pixel block includes a third gain control transistor, the second gain compensation pixel block also has a third type reset unit, the third type reset unit includes a second reset transistor, and the gain unit of the second gain compensation unit includes a fourth gain control transistor, wherein the third gain control transistor and the fourth gain control transistor are connected in series and the series node therebetween is coupled to the second reset transistor.

6. The image sensor according to claim 5, characterized in that The second gain compensation pixel block further includes a second compensation readout unit. The second compensation readout unit includes a source follower transistor. The control terminal of the source follower transistor is coupled to the second gain compensation unit in a source-drain common connection manner.

7. The image sensor according to claim 1, wherein: The image sensor further includes a first clamping circuit, which corresponds one-to-one to the first type pixel block; and / or the image sensor further includes a second clamping circuit, which corresponds one-to-one to the third type pixel block.

8. The image sensor according to claim 7, wherein: The structures of the first clamping circuit and the second clamping circuit both include: A starting control module, used for providing a starting voltage; a voltage transfer module, configured to receive the startup voltage and generate a clamping voltage, wherein a control terminal of the voltage transfer module receives the transfer voltage, a first terminal is coupled to the startup control module for receiving the startup voltage, and a second terminal is configured to output the clamping voltage; and An output module, wherein the control end receives an output control signal, the first end is coupled to the second end of the voltage transfer module, the second end is coupled to the output bit line, and is used to output the received clamping voltage to the output bit line; Alternatively, the first clamping circuit and the first type pixel block form a first clamping compensation circuit in one-to-one correspondence, and the second clamping circuit and the third type pixel block form a second clamping compensation circuit in one-to-one correspondence; wherein the first clamping compensation circuit and the second clamping circuit are arranged in a manner including: The first clamp compensation circuit includes a first clamp module and a first gain compensation module, and the first clamp module and the first gain compensation module share an output bit line, wherein: The first clamping module includes a first startup control module, a first voltage transfer module and a first output module, wherein the first output module is electrically connected to the output bit line; the first gain compensation module includes a first gain matching module and a first source follower module, wherein the control end of the first source follower module is coupled to the first gain matching module, the first end is coupled to the first voltage source, and the second end is electrically disconnected from the output bit line; The second clamping compensation circuit includes a second clamping module and a second gain compensation module, and the second clamping module and the second gain compensation module share an output bit line, wherein: The second clamping module includes a second startup control module, a second voltage transfer module and a second output module, the second output module is electrically connected to the output bit line, the second gain compensation module includes a second gain matching module and a second source follower module, the control end of the second source follower module is coupled to the second gain matching module, the first end is coupled to the second voltage source, and the second end is electrically disconnected from the output bit line.

9. The image sensor according to claim 8, wherein: The first gain matching module includes a first transistor, and the first source follower module includes a fourth transistor; the first startup control module includes a second transistor and a third transistor connected in series, and the control ends of the two and the first end of the series structure receive a startup voltage, the second end of the series structure is coupled to the first voltage transfer module, the first voltage transfer module includes a fifth transistor, and the first output module includes a sixth transistor; and / or, the second gain matching module includes an eighth transistor and a ninth transistor connected in series, and the second source follower module includes an eleventh transistor; the second startup control module includes a seventh transistor, and its control end and the first end receive a startup voltage, and the second end is coupled to the second voltage transfer module, the second voltage transfer module includes a tenth transistor, and the second output module includes a twelfth transistor.

10. The image sensor according to claim 1, wherein: The image sensor includes a pixel area and a first virtual area located at the periphery of the pixel area and / or a second virtual area located at the periphery of the pixel area. When both exist, the first virtual area and / or the second virtual area are located at opposite sides of the pixel area, wherein: There is a first boundary between the pixel area and the first virtual area, including the first type pixel block located in the pixel area and the first gain compensation pixel block located in the first virtual area; A second boundary is defined between the pixel region and the second virtual region, and includes the third type pixel block located in the pixel region and the second gain compensation pixel block located in the second virtual region.

11. The image sensor according to claim 10, wherein: The image sensor further includes a black pixel region, and the black pixel region is spaced apart from the pixel region, wherein: The black pixel area is located at a side of the first virtual area away from the pixel area, and a third boundary is defined between the black pixel area and the first virtual area, including the third type pixel block located in the black pixel area and the second gain compensation pixel block located in the first virtual area; and / or, The image sensor includes a third virtual area located on a side of the black pixel area away from the pixel area, with a fourth boundary between the black pixel area and the third virtual area, including the first type pixel block located in the black pixel area and the first gain compensation pixel block located in the third virtual area.

12. The image sensor according to claim 11, wherein: The first virtual area also includes a first clamping circuit layout area; and / or, the second virtual area also includes a second clamping circuit layout area; and / or, the third virtual area also includes a third clamping circuit layout area; and / or, the image sensor also includes a control driving circuit corresponding to each area to provide corresponding control signals for each area.

13. The image sensor according to claim 12, wherein: The first virtual area includes a first sub-area, a second sub-area and a third sub-area, the first clamp circuit layout area is located in the second sub-area and extends to the first sub-area and the third sub-area; the second virtual area includes a fourth sub-area and a fifth sub-area, the second clamp circuit layout area is located in the fifth sub-area and extends to the fourth sub-area; the third virtual area includes a sixth sub-area and a seventh sub-area, the third clamp circuit layout area is located in the seventh sub-area and extends to the sixth sub-area.

14. The image sensor according to any one of claims 1 to 13, characterized in that: The pixel area array of the image sensor includes a focus pixel group composed of a plurality of the pixel blocks, the focus pixel group has m rows and n columns, and m and n are both integers greater than 1; wherein the data processing cycle of the black pixel area of ​​the image sensor is a processing unit composed of black pixel blocks having m rows and n columns.

15. An electronic device, characterized in that: Comprising the image sensor as claimed in any one of claims 1-14.

Images