High-reliability via hole connection array substrate

Abstract

The utility model discloses a high-reliability array substrate connected by via holes. The high-reliability array substrate comprises a gate layer, an insulating layer, an isolating layer, a flat layer, a touch metal layer, a passivation layer, a common electrode layer, a pixel electrode layer and a substrate, the structure further comprises a first via hole, a second via hole, first filling metal and second filling metal. The gate layer is in lap joint with the common electrode layer through the first via hole, and the touch metal layer is in lap joint with the common electrode layer through the second via hole; the first through hole is filled with the first filling metal, so that the bottom end of the first through hole is flush with the bottom of the passivation layer; the second via hole is filled with the second filling metal, so that the top end of the second via hole is flush with the top of the passivation layer. By filling the metal in the via hole where the gate layer is lapped with the touch metal layer, the via hole can be shallower, the climbing phenomenon is reduced, and the reliability of via hole connection is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and particularly relates to an array substrate with highly reliable via connection. Background Art

[0002] A liquid crystal display screen includes an array substrate, a color filter substrate, and a liquid crystal layer located between the two substrates. On the side of the array substrate facing the liquid crystal layer, there are thin film transistors, pixel electrodes, etc. Among them, a thin film transistor generally includes a gate electrode, an active layer, a source electrode, and a drain electrode. It has the characteristics of small volume, low power consumption, no radiation, etc., and occupies a dominant position in the current flat panel display market.

[0003] The application scope of liquid crystal display screens in China is becoming wider and wider, and they have been widely applied in various industries, such as electronic consumer products, industrial production, smart home, artificial intelligence and other fields; and a liquid crystal module is a screen + backlight assembly, and the display component of a liquid crystal TV is a liquid crystal module, whose status is equivalent to the picture tube in a CRT.

[0004] Manufacturing the color filter substrate requires several processes such as deposition, exposure, etching, etc. Similarly, the array substrate also needs to go through several processes such as deposition, exposure, etching, etc. on a glass substrate to form the array substrate.

[0005] However, the array substrate of the existing liquid crystal display device uses a transparent electrode layer (VITO) for connection. This connection method often has the phenomenon of via connection failure at the via, because when the transparent electrode layer and the gate layer metal are performing deep via connection, process fluctuations may cause a risk of connection failure at the ramp position of the transparent electrode layer (VITO). Summary of the Utility Model

[0006] For the array substrate of the existing liquid crystal display device, there is a problem of connection failure at the ramp position of the deep via connection between the transparent electrode layer (VITO) and the gate layer metal.

[0007] In view of the above problems, an array substrate with highly reliable via connection is proposed. By filling metal in the via where the gate layer and the touch metal layer overlap, the via can be made shallower, reducing the ramp phenomenon and improving the reliability of via connection. By dividing the common electrode layer into two separate regions and filling metal in each via, even if one group of vias fails, the via connection between the gate layer and the touch metal layer can still be ensured, improving the display quality of the product.

[0008] In a first aspect, an array substrate with highly reliable via connection includes:

[0009] A gate layer, an insulating layer, an isolation layer, a planarization layer, a touch metal layer, a passivation layer, a common electrode layer, a pixel electrode layer, and a substrate.

[0010] The insulating layer, the isolation layer, the planarization layer, and the passivation layer are sequentially fabricated on the substrate from bottom to top;

[0011] The gate layer is fabricated in the insulating layer, the touch metal layer is fabricated in the planarization layer, the common electrode layer is fabricated in the passivation layer, and the pixel electrode layer is fabricated on the passivation layer;

[0012] Wherein, it further includes:

[0013] A first via hole and a second via hole;

[0014] A first filling metal and a second filling metal;

[0015] The gate layer is overlapped with the common electrode layer through the first via hole, and the touch metal layer is overlapped with the common electrode layer through the second via hole;

[0016] The first filling metal is filled in the first via hole to make the bottom end of the first via hole flush with the bottom of the passivation layer;

[0017] The second filling metal is filled in the second via hole to make the top end of the second via hole flush with the top of the passivation layer.

[0018] Combined with the array substrate with high-reliability via connection according to the first aspect of the present invention, in the first possible implementation manner, both the first filling metal and the second filling metal are gate layer metals.

[0019] Combined with the array substrate with high-reliability via connection according to the first aspect of the present invention, in the second possible implementation manner, both the first filling metal and the second filling metal are touch metal layer metals.

[0020] Combined with the array substrate with high-reliability via connection according to the first aspect of the present invention, in the third possible implementation manner, one of the first filling metal and the second filling metal is a gate layer metal, and the other is a touch metal layer metal.

[0021] In a second aspect, an array substrate with high-reliability via connection includes:

[0022] A gate layer, an insulating layer, an isolation layer, a planarization layer, a touch metal layer, a passivation layer, a common electrode layer, a pixel electrode layer, and a substrate;

[0023] The insulating layer, the isolation layer, the planarization layer, and the passivation layer are sequentially fabricated on the substrate from bottom to top;

[0024] The gate layer is fabricated in the insulating layer, the touch metal layer is fabricated in the planar layer, the common electrode layer is fabricated in the passivation layer, and the pixel electrode layer is fabricated on the passivation layer;

[0025] The common electrode layer includes separate:

[0026] A first separation region and a second separation region;

[0027] Wherein, it further includes:

[0028] A first group of vias and a second group of vias;

[0029] A third filling metal and a fourth filling metal;

[0030] The gate layer and the touch metal layer are overlapped with the first separation region of the common electrode layer through the first group of vias, and the gate layer and the touch metal layer are overlapped with the second separation region of the common electrode layer through the second group of vias;

[0031] The third filling metal is filled in the first group of vias to make the depth of the first group of vias shallower;

[0032] The fourth filling metal is filled in the second group of vias to make the depth of the second via shallower.

[0033] Combined with the array substrate with high-reliability via connection according to the second aspect of the present invention, in the first possible implementation manner, the first group of vias includes:

[0034] A third via and a fourth via;

[0035] The third filling metal is filled in the third via and the fourth via,

[0036] The third filling metal is filled in the third via to make the bottom end of the third via flush with the bottom of the passivation layer;

[0037] The third filling metal is filled in the fourth via to make the top end of the fourth via flush with the top of the passivation layer.

[0038] Combined with the first possible implementation manner of the second aspect of the present invention, in the second possible implementation manner, the third filling metal is:

[0039] One of the gate layer metal and the touch metal layer metal.

[0040] Combined with the array substrate with high-reliability via connection according to the second aspect of the present invention, in the third possible implementation manner, the second group of vias includes:

[0041] A fifth via and a sixth via;

[0042] Fill the fourth filling metal in the fifth via hole and the sixth via hole.

[0043] The fourth filling metal is filled in the fifth via hole, making the bottom end of the fifth via hole flush with the bottom of the passivation layer.

[0044] The fourth filling metal is filled in the sixth via hole, making the top end of the sixth via hole flush with the top of the passivation layer.

[0045] Combined with the first possible implementation manner of the second aspect of the present invention, in the fourth possible implementation manner, the fourth filling metal is:

[0046] One of the gate layer metal and the touch metal layer metal.

[0047] Implementing an array substrate with a highly reliable via connection according to the present invention. By filling metal in the vias where the gate layer and the touch metal layer overlap, the vias can be made shallower, reducing the ramp phenomenon and improving the reliability of the via connection. By dividing the common electrode layer into two separate regions and filling metal in each via, even if one group of vias fails, the via connection between the gate layer and the touch metal layer can still be ensured, improving the display quality of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0049] Figure 1 It is a schematic diagram of the film layer structure of the array substrate with a highly reliable via connection in Embodiment 1 of the present invention;

[0050] Figure 2 It is a schematic diagram of the metal via connection in the array substrate with a highly reliable via connection in Embodiment 1 of the present invention;

[0051] Figure 3 It is a schematic diagram of the film layer structure of the array substrate with a highly reliable via connection in Embodiment 2 of the present invention;

[0052] Figure 4 It is a schematic diagram of the metal via connection in the array substrate with a highly reliable via connection in Embodiment 2 of the present invention;

[0053] The names of the parts referred to by the numbers in the drawings are as follows: 10 - substrate, 101 - first filling metal, 102 - second filling metal, 103 - third filling metal, 104 - fourth filling metal, 20 - insulating layer, 30 - gate layer, 40 - isolation layer, 50 - planarization layer, 60 - touch metal layer, 61 - first via, 62 - second via, 63 - third via, 64 - fourth via, 65 - fifth via, 66 - sixth via, 70 - common electrode layer, 71 - first separation region, 72 - second separation region, 80 - passivation layer, 90 - pixel electrode layer. Detailed implementation manners

[0054] The technical solutions in the present utility model will be clearly and completely described below with reference to the accompanying drawings in the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0056] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0057] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0058] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.

[0059] In the existing array substrate of a liquid crystal display device, there is a problem of connection failure at the ramp position where the transparent electrode layer (VITO) is connected to the deep metal holes of the gate layer 30.

[0060] In view of the above problems, an array substrate with highly reliable via connection is proposed.

[0061] In a first aspect, as Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the film layer structure of the array substrate with highly reliable via connection in Embodiment 1 of the present utility model, Figure 2 is a schematic diagram of the metal via connection in the array substrate with highly reliable via connection in Embodiment 1 of the present utility model; an array substrate with highly reliable via connection includes a gate layer 30, an insulating layer 20, an isolation layer 40, a planarization layer 50, a touch control metal layer 60, a passivation layer 80, a common electrode layer 70 (VITO), a pixel electrode layer 90 (PITO) 90, and a substrate 10; the insulating layer 20, the isolation layer 40, the planarization layer 50, and the passivation layer 80 are sequentially fabricated on the substrate 10 from bottom to top; the gate layer 30 is fabricated in the insulating layer 20, the touch control metal layer 60 is fabricated in the planarization layer 50, the common electrode layer 70 (VITO) is fabricated in the passivation layer 80, and the pixel electrode layer 90 (PITO) 90 is fabricated on the passivation layer 80; wherein, it further includes a first via 61 and a second via 62, a first filling metal 101 and a second filling metal 102; the gate layer 30 is overlapped with the common electrode layer 70 (VITO) through the first via 61, and the touch control metal layer 60 is overlapped with the common electrode layer 70 (VITO) through the second via 62; the first filling metal 101 is filled in the first via 61 to make the bottom end of the first via 61 flush with the bottom of the passivation layer 80; the second filling metal 102 is filled in the second via 62 to make the top end of the second via 62 flush with the top of the passivation layer 80. By filling metal in the vias where the gate layer 30 is overlapped with the touch control metal layer 60, the vias can be made shallower, the ramp phenomenon can be reduced, and the reliability of the via connection can be improved.

[0062] In Embodiment 1, the touch control metal layer 60 is overlapped with the gate layer 30 through two vias, and by filling the first filling metal 101 or the second filling metal 102 in the two vias, the ramp phenomenon is reduced.

[0063] Preferably, both the first filling metal 101 and the second filling metal 102 are metals of the gate layer 30. That is, the metals of the gate layer 30 are filled in both vias.

[0064] Preferably, both the first filling metal 101 and the second filling metal 102 are metals of the touch control metal layer 60. That is, the metals of the touch control metal layer 60 are filled in both vias.

[0065] Preferably, one of the first filling metal 101 and the second filling metal 102 is a metal of the gate layer 30, and the other is a metal of the touch control metal layer 60. That is, the metals of the touch control metal layer 60 or the gate layer 30 are filled in both vias.

[0066] In a second aspect, as Figure 3 and Figure 4 , Figure 3 is a schematic diagram of the film layer structure of the array substrate with highly reliable via connection in Embodiment 2 of the present invention, Figure 4 is a schematic diagram of the metal via connection in the array substrate with highly reliable via connection in Embodiment 2 of the present invention; an array substrate with highly reliable via connection includes: a gate layer 30, an insulating layer 20, an isolation layer 40, a planarization layer 50, a touch control metal layer 60, a passivation layer 80, a common electrode layer 70 (VITO), a pixel electrode layer 90 (PITO) 90, and a substrate 10; the insulating layer 20, the isolation layer 40, the planarization layer 50, and the passivation layer 80 are sequentially formed on the substrate 10 from bottom to top; the gate layer 30 is formed in the insulating layer 20, the touch control metal layer 60 is formed in the planarization layer 50, the common electrode layer 70 (VITO) is formed in the passivation layer 80, and the pixel electrode layer 90 (PITO) 90 is formed on the passivation layer 80;

[0067] The common electrode layer 70 (VITO) includes separate: a first separation region 71 and a second separation region 72; wherein, it further includes a first group of vias and a second group of vias; a third filling metal 103 and a fourth filling metal 104; the gate layer 30 and the touch control metal layer 60 are overlapped with the first separation region 71 of the common electrode layer 70 (VITO) through the first group of vias, and the gate layer 30 and the touch control metal layer 60 are overlapped with the second separation region 72 of the common electrode layer 70 (VITO) through the second group of vias; the third filling metal 103 is filled in the first group of vias to make the depth of the first group of vias shallower; the fourth filling metal 104 is filled in the second group of vias to make the depth of the second via 62 shallower. By dividing the common electrode layer 70 (VITO) into two separate separation regions and filling metals in each via, even if one group of vias fails, the via connection between the gate layer 30 and the touch control metal layer 60 can still be ensured, improving the display quality of the product.

[0068] In Embodiment 2, the common electrode layer 70 (VITO) is divided into two separate regions for independent via connections. The touch control metal layer 60 and the gate layer 30 are independently overlapped through two groups of vias. By filling the first filling metal 101 and / or the second filling metal 102 in the two groups of vias, the ramp-up phenomenon is reduced.

[0069] Further, the first group of vias includes a third via 63 and a fourth via 64. The third filling metal 103 is filled in the third via 63 and the fourth via 64. The third filling metal 103 is filled in the third via 63 so that the bottom end of the third via 63 is flush with the bottom of the passivation layer 80. The third filling metal 103 is filled in the fourth via 64 so that the top end of the fourth via 64 is flush with the top of the passivation layer 80.

[0070] Preferably, the third filling metal 103 is one of the metals of the gate layer 30 and the touch control metal layer 60. The same metal or different metals can be filled in the third via 63 and the fourth via 64 respectively.

[0071] Further, the second group of vias includes a fifth via 65 and a sixth via 66. The fourth filling metal 104 is filled in the fifth via 65 and the sixth via 66. The fourth filling metal 104 is filled in the fifth via 65 so that the bottom end of the fifth via 65 is flush with the bottom of the passivation layer 80. The fourth filling metal 104 is filled in the sixth via 66 so that the top end of the sixth via 66 is flush with the top of the passivation layer 80.

[0072] Preferably, the fourth filling metal 104 is one of the metals of the gate layer 30 and the touch control metal layer 60. The same metal or different metals can be filled in the fifth via 65 and the sixth via 66 respectively.

[0073] For an array substrate with a highly reliable via connection implementing the present utility model, by filling metal in the vias where the gate layer 30 and the touch control metal layer 60 are overlapped, the vias can be made shallower, the ramp-up phenomenon can be reduced, and the reliability of the via connection can be improved. By dividing the common electrode layer 70 (VITO) into two separate regions and filling metal in each via, even if one group of vias fails, the via connection between the gate layer 30 and the touch control metal layer 60 can still be ensured, improving the display quality of the product.

[0074] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An array substrate with high reliability via connection, characterized in that: include: A gate layer, an insulating layer, an isolation layer, a planarization layer, a touch metal layer, a passivation layer, a common electrode layer, a pixel electrode layer and a base substrate; The insulating layer, the isolation layer, the planarization layer, and the passivation layer are sequentially formed on the substrate from bottom to top; The gate layer is formed in the insulating layer, the touch metal layer is formed in the flat layer, the common electrode layer is formed in the passivation layer, and the pixel electrode layer is formed on the passivation layer; Among them, it also includes: a first via hole and a second via hole; a first filler metal and a second filler metal; The gate layer is overlapped with the common electrode layer through the first via hole, and the touch metal layer is overlapped with the common electrode layer through the second via hole; The first filling metal is filled in the first via hole so that the bottom end of the first via hole is flush with the bottom of the passivation layer; The second filling metal is filled in the second via hole so that the top of the second via hole is flush with the top of the passivation layer.

2. The array substrate with high reliability via connection according to claim 1, characterized in that: The first filling metal and the second filling metal are both gate layer metals.

3. The array substrate with high reliability via connection according to claim 1, characterized in that: The first filling metal and the second filling metal are both touch metal layer metals.

4. The array substrate with high reliability via connection according to claim 1, characterized in that: One of the first filling metal and the second filling metal is a gate layer metal, and the other is a touch metal layer metal.

5. An array substrate with high reliability via connection, characterized in that: include: Gate layer, insulating layer, isolation layer, planarization layer, touch metal layer, passivation layer, common electrode layer, pixel electrode layer and base substrate; The insulating layer, the isolation layer, the planarization layer, and the passivation layer are sequentially formed on the substrate from bottom to top; The gate layer is formed in the insulating layer, the touch metal layer is formed in the flat layer, the common electrode layer is formed in the passivation layer, and the pixel electrode layer is formed on the passivation layer; The common electrode layer includes separate: A first separation region and a second separation region; Among them, it also includes: A first set of vias and a second set of vias; a third filler metal and a fourth filler metal; The gate layer and the touch metal layer are overlapped with the first separation area of ​​the common electrode layer through the first group of via holes, and the gate layer and the touch metal layer are overlapped with the second separation area of ​​the common electrode layer through the second group of via holes; The third filling metal is filled in the first group of via holes to make the depth of the first group of via holes shallower; The fourth filling metal is filled in the second group of via holes to reduce the depth of the second group of via holes.

6. The array substrate with high reliability via connection according to claim 5, characterized in that: The first set of vias includes: a third via hole and a fourth via hole; Fill the third via hole and the fourth via hole with the third filling metal, The third filling metal is filled in the third via hole so that the bottom end of the third via hole is flush with the bottom of the passivation layer; The third filling metal is filled in the fourth via hole so that the top of the fourth via hole is flush with the top of the passivation layer.

7. The array substrate with high reliability via connection according to claim 6, characterized in that: The third filler metal is: One of the gate layer metal and touch metal layer metal.

8. The array substrate with high reliability via connection according to claim 5, characterized in that: The second set of vias includes: a fifth via hole and a sixth via hole; Filling the fourth filling metal in the fifth via hole and the sixth via hole, The fourth filling metal is filled in the fifth via hole so that the bottom end of the fifth via hole is flush with the bottom of the passivation layer; The fourth filling metal is filled in the sixth via hole so that the top of the sixth via hole is flush with the top of the passivation layer.

9. The array substrate with high reliability via connection according to claim 8, characterized in that: The fourth filler metal is: One of the gate layer metal and touch metal layer metal.

Images