Planar gallium oxide MOSFET device
By adopting the design of planar gallium oxide MOSFET devices in SiC MOSFET devices, the problem of insufficient collapse voltage of existing SiC MOSFET devices is solved, and higher collapse voltage and better heat dissipation efficiency are achieved.
Patent Information
- Application Number
- CN202422007142.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-08-19
AI Technical Summary
Existing SiC MOSFET devices cannot meet the needs of higher voltage DC converters, and the crash voltage is not enough to cope with applications above 3000V.
The planar gallium oxide MOSFET device is adopted to set structures such as silicon ion implantation region, source and drain metal, gate etching region on the gallium oxide epitaxial layer, and a gate field plate metal layer is arranged above the gate metal contact layer to narrow the distance between the gate and the source, and reduce the electric field peak between the gate and the drain.
It significantly improves the device's collapse voltage, improves the voltage withstandability of high-power devices, prevents high current from damaging the gate, and improves heat dissipation efficiency and area utilization.
Smart Images
Figure CN222996954U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a planar gallium oxide MOSFET device. Background Art
[0002] SiC MOSFET is a relatively mature technology. The breakdown voltage of a conventional chip can reach the range of 650V to 1200V. Currently, SiC MOSFET devices are used in on-board chargers (OBC), high-voltage traction inverters (HVTraction Invertor), and high-voltage DC converters (HV DC / DC) in new energy vehicles. Among them, for the high-voltage DC converter in a series battery module, as the range of an electric vehicle increases, more series battery modules are required, and a higher-voltage DC converter above 3000V is needed.
[0003] The existing third-generation semiconductor wide-bandgap SiC MOSFET device is already a relatively mature technology. The breakdown voltage of a packaged chip can reach 1200V to 1500V. However, it still cannot meet the requirements of higher-voltage DC converters. It is necessary to improve and enhance from the design of the most basic unit transistor device in the SiC MOSFET chip to increase the breakdown voltage of the entire module. Summary of the Utility Model
[0004] The purpose of the utility model is to increase the breakdown voltage of the existing SiC MOSFET device, and a planar gallium oxide MOSFET device is provided.
[0005] The purpose of the utility model is achieved through the following technical solutions:
[0006] A planar gallium oxide MOSFET device is provided, including a substrate and a gallium oxide epitaxial layer provided on the substrate;
[0007] On the gallium oxide epitaxial layer, there are a silicon ion implantation region, source-drain metal, gate etching region, gate metal contact layer, source-drain-gate first via layer, gate field plate metal layer, source-drain-gate second via layer, thin film resistance layer, first connection metal layer, source-drain-gate third via layer, source-drain-gate fourth via layer, and second connection metal layer;
[0008] Among them, the gate field plate metal layer is arranged above the gate metal contact layer and is connected through the source-drain-gate first via layer.
[0009] As an optimal option, the substrate is bonded to the gallium oxide epitaxial layer through a nano silver glue layer.
[0010] As a preferred option, the substrate is a SiC substrate, a gallium oxide substrate, a silicon substrate, a sapphire substrate, a high-resistance silicon substrate, an alumina substrate, a silicon-based SOI substrate, a diamond substrate or a glass substrate.
[0011] As a preferred option, the substrate is of N type.
[0012] As a preferred option, the silicon ion implantation region is an N-type silicon ion implantation region.
[0013] As a preferred option, the first via layer of the source-drain-gate, the second via layer of the source-drain-gate, the third via layer of the source-drain-gate and the fourth via layer of the source-drain-gate all include an array of vias.
[0014] As a preferred option, a gate oxide layer is further included, and the gate oxide layer is disposed on the gate etching region.
[0015] As a preferred option, the gate oxide layer is a silicon dioxide oxide layer.
[0016] As a preferred option, the size of the substrate is 6 inches, and the size of the gallium oxide epitaxial layer is 4 inches.
[0017] As a preferred option, a top protective layer is further included.
[0018] As a preferred option, a source field plate metal layer is further included.
[0019] It should be further noted that the technical features corresponding to the above options can be combined or replaced with each other to form a new technical solution without conflict.
[0020] Compared with the prior art, the beneficial effects of the present utility model are as follows:
[0021] (1) The present utility model uses gallium oxide, a super wide bandgap semiconductor material, to make an epitaxial structure, which significantly improves the breakdown voltage of high-power devices. At the same time, a gate field plate metal layer is disposed above the gate metal contact layer to shorten the distance between the gate and the source, reduce the peak value of the electric field between the gate and the drain, and achieve the effect of improving the gate and drain breakdown voltages of the device.
[0022] (2) In one example, the first via layer of the source-drain-gate, the second via layer of the source-drain-gate, the third via layer of the source-drain-gate and the fourth via layer of the source-drain-gate all include an array of vias. Through the via array design on the source, drain and gate of the device, when a large current passes through the device, the current can be effectively dispersed at the gate end to prevent the gate from being burned by the large current.
[0023] (3) In one example, the second connecting metal layer is disposed above the gallium oxide epitaxial layer, so that the metal pads on the top layer can be designed on the die. On the one hand, it can dissipate heat and improve the heat dissipation efficiency of the device. On the other hand, it can save the die area and improve the area utilization rate.
[0024] (4) In one example, by using the structural design of the source field plate on the source electrode, the distance between the source and drain electrodes is shortened, the electric field between the source field plate and the drain end is increased, and the electric field intensity between the gate and drain electrodes is dispersed, so as to achieve the purpose of improving the breakdown voltage of the device without damaging the device. Description of the Drawings
[0025] Figure 1 It is a schematic cross-sectional structure diagram of a planar gallium oxide MOSFET device shown in an embodiment of the present invention;
[0026] Figure 2 It is a schematic top view structure diagram of a planar gallium oxide MOSFET device shown in an embodiment of the present invention;
[0027] Figures 3 - 18 It is a schematic cross-sectional structure process diagram of manufacturing a planar gallium oxide MOSFET device shown in an embodiment of the present invention;
[0028] Figures 19 - 32 It is a schematic top view structure process diagram of manufacturing a planar gallium oxide MOSFET device shown in an embodiment of the present invention.
[0029] Reference numerals in the figures: 1 - gallium oxide epitaxial layer; 2 - silicon ion implantation region; 3 - source-drain metal; 4 - gate etching region; 5 - nano silver glue layer; 6 - gate metal contact layer; 7 - first via layer for source-drain-gate; 8 - gate field plate metal layer; 9 - second via layer for source-drain-gate; 10 - thin film resistor layer; 11 - first connecting metal layer; 12 - third via layer for source-drain-gate; 13 - fourth via layer for source-drain-gate; 14 - second connecting metal layer; 15 - top protective layer; 16 - source field plate metal layer. Detailed Embodiments
[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0031] In the description of the present utility model, it should be noted that the directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings. This is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model. In addition, "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.
[0032] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0033] In addition, the technical features involved in different embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.
[0034] Refer to Figures 1 - 2 , in an exemplary embodiment, a planar gallium oxide MOSFET device is provided, including a substrate and a gallium oxide epitaxial layer 1 provided on the substrate;
[0035] On the gallium oxide epitaxial layer 1, there are a silicon ion implantation region 2, source-drain metal 3, a gate etching region 4, a gate metal contact layer 6, a source-drain-gate first via layer 7, a gate field plate metal layer 8, a source-drain-gate second via layer 9, a thin film resistance layer 10, a first connection metal layer 11, a source-drain-gate third via layer 12, a source-drain-gate fourth via layer 13, and a second connection metal layer 14;
[0036] Among them, the gate field plate metal layer 8 is disposed above the gate metal contact layer 6 and is connected through the source-drain-gate first via layer 7.
[0037] Specifically, using gallium oxide, a semiconductor material with an ultra-wide bandgap, as the epitaxial structure can significantly improve the breakdown voltage of high-power devices. At the same time, by disposing the gate field plate metal layer 8 above the gate metal contact layer 6, the distance between the gate and the source is shortened, and the peak value of the electric field between the gate and the drain is reduced, achieving the effect of improving the gate-drain breakdown voltage of the device.
[0038] Further, the substrate is bonded to the gallium oxide epitaxial layer 1 through a nano silver glue layer 5. In other embodiments, the high-temperature-resistant bonding material for the bonding process is not limited to high-temperature nano silver glue. For example, it can be an 80-20% alloy of gold and tin.
[0039] Further, the substrate is a SiC substrate, a gallium oxide substrate, a silicon substrate, a sapphire substrate, a high-resistance silicon substrate, an alumina substrate, a silicon-based SOI substrate, a diamond substrate, a glass substrate, etc.
[0040] Further, the substrate is N-type. The silicon ion implantation region 2 is an N-type silicon ion implantation region.
[0041] Further, the first via layer 7 of the source-drain-gate, the second via layer 9 of the source-drain-gate, the third via layer 12 of the source-drain-gate, and the fourth via layer 13 of the source-drain-gate all include an array of vias. Through the design of the via array on the source, drain, and gate of the device, when a large current passes through the device, the current can be effectively dispersed at the gate end, preventing the gate from being burned by the large current.
[0042] Further, a gate oxide layer is further included, and the gate oxide layer is disposed on the gate etching region 4. The gate oxide layer is a silicon dioxide oxide layer and / or an alumina thin film layer.
[0043] Further, the size of the substrate is 6 inches, and the size of the gallium oxide epitaxial layer 1 is 4 inches.
[0044] Further, a top protective layer 15 is further included.
[0045] Further, a source field plate metal layer 16 is further included. By using the structural design of the source field plate on the source electrode, the distance between the source and drain electrodes is shortened, the electric field between the source field plate and the drain end is increased, and the electric field intensity between the gate and drain electrodes is dispersed, so as to achieve the purpose of improving the breakdown voltage of the device without damaging the device.
[0046] Further, the second connection metal layer 14 is disposed above the gallium oxide epitaxial layer 1, so that the top metal pad can be designed on the die. On the one hand, it can dissipate heat and improve the heat dissipation efficiency of the device. On the other hand, it can save the die area and improve the area utilization rate.
[0047] Refer to Figures 3 - 18 (or Figures 19 - 32 ), the process flow of a single gallium oxide device is given, specifically including:
[0048] S1. Sputter metal on the 4-inch gallium oxide epitaxial layer 1 substrate as the first alignment layer, such as Figure 3 ;
[0049] S2. Etch and distinguish the active and passive regions of the device on the gallium oxide epitaxial layer 1 platform, such as Figure 4 ;
[0050] S3. Define the photolithography pattern of the source and drain regions on the gallium oxide epitaxial layer 1, perform N-type silicon ion implantation in the N-type silicon ion implantation region 2, with an ion implantation energy of approximately KeV, an implantation dose of approximately 1E14 - 5E15 / cm2, and a deep implantation depth to form the ohmic contact regions of the device source and drain electrodes, as shown in Figure 5 ;
[0051] S4. After defining the photolithography pattern of the source and drain regions with the photolithography process, depositing nickel and silver ohmic metals, and removing the photoresist, perform a metal annealing at 460 degrees to form the ohmic contact, thus obtaining the source-drain electrode metal 3, as shown in Figure 6 ;
[0052] S5. After defining the photolithography pattern of the photoresist for the gate etching region 4 with the photolithography process, etch the gallium oxide and then remove the photoresist, and then deposit silicon dioxide and aluminum oxide as the gate oxide layer of the device, as shown in Figure 7 ;
[0053] S6. Use a heat-resistant nano silver paste, coat it on a 6-inch silicon carbide substrate, and bond a 4-inch gallium oxide epitaxial wafer to the 6-inch silicon carbide substrate, as shown in Figure 8 ;
[0054] S7. After defining the gate metal region with the photolithography process, deposit titanium, nickel, and gold metals, the gate metal contact layer 6, and then deposit a silicon nitride protective layer after removing the photoresist, as shown in Figure 9 ;
[0055] S8. After defining the first layer of array vias on the device source, drain, and gate metals with the photolithography process, form the source-drain-gate first via layer 7, then etch the silicon nitride thin film, and then remove the photoresist, as shown in Figure 10 ;
[0056] S9. After defining the photolithography pattern of the gate field plate with the photolithography process, deposit the upper gate field plate metal to form the gate field plate metal layer 8, then remove the photoresist, and deposit a silicon nitride thin film with a thickness of approximately 500 nm, as shown in Figure 11 ;
[0057] S10. After defining the second layer of array vias on the device source, drain, and gate metals with the photolithography process, form the source-drain-gate second via layer 9, etch the 500-nm silicon nitride thin film, and then remove the photoresist, as shown in Figure 12 ;
[0058] S11. After defining the region of the thin film resistor with the photolithography process, sputter-deposit tantalum nitride material as the thin film resistor, and then remove the photoresist to form the thin film resistor layer 10, as shown in Figure 13 ;
[0059] S12. Define the first-layer connection metal area using photolithography technology, evaporate and deposit a 1-μm-thick metal layer to form the first connection metal layer 11 for connecting devices, resistors, and capacitors, and then remove the photoresist. For example, Figure 14 ;
[0060] S13. Deposit a 1000-A-thick silicon nitride layer as the capacitor dielectric layer, define the third-layer array via layer using photolithography technology to form the source-drain-gate third via layer 12. After etching 1000-A-thick silicon nitride, remove the photoresist. For example, Figure 15 ;
[0061] S14. Coating a 3-μm-thick photosensitive PBO polymer material and baking it dry, define the fourth-layer via area using photolithography technology to form the source-drain-gate fourth via layer 13. For example, Figure 16 ;
[0062] S15. Define the second-layer connection metal area using photolithography technology, evaporate and deposit a 4-μm-thick metal layer to form the second connection metal layer 14 for connecting devices and the first connection metal layer 11, and then remove the photoresist. For example, Figure 17 ( Figure 31 )
[0063] S16. Coating a photosensitive PBO polymer material with a thickness greater than 5 μm and baking it dry, define the opening area of the top protective layer 15. For example, Figure 18 .
[0064] This process enables wafers with an epitaxial layer smaller than 6 inches, such as 4-inch epitaxial wafers, to be compatible with the 6-inch semiconductor process flow. Not only can the fourth-generation semiconductor material replace the third-generation semiconductor material to increase the breakdown voltage of the device, but it can also be compatible with epitaxial wafers of different sizes. This manufacturing method will break the traditional process that can only develop processes on epitaxial wafers of the same size.
[0065] The above specific embodiments are detailed descriptions of the present invention. It cannot be determined that the specific embodiments of the present invention are only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions and substitutions can still be made, which should all be regarded as falling within the protection scope of the present invention.
Claims
1. A planar gallium oxide MOSFET device, characterized in that: It includes a substrate and a gallium oxide epitaxial layer disposed on the substrate; The gallium oxide epitaxial layer is provided with a silicon ion implantation region, a source-drain metal, a gate etching region, a gate metal contact layer, a source-drain gate first through hole layer, a gate field plate metal layer, a source-drain gate second through hole layer, a thin film resistor layer, a first connection metal layer, a source-drain gate third through hole layer, a source-drain gate fourth through hole layer and a second connection metal layer; Wherein, the gate field plate metal layer is arranged above the gate metal contact layer and is connected through the source, drain, gate and first through-hole layer.
2. A planar gallium oxide MOSFET device according to claim 1, characterized in that: The substrate is bonded to the gallium oxide epitaxial layer through a nano silver glue layer.
3. A planar gallium oxide MOSFET device according to claim 1, characterized in that: The substrate is a SiC substrate, a gallium oxide substrate, a silicon substrate, a sapphire substrate, a high-resistance silicon substrate, an aluminum oxide substrate, a silicon-based SOI substrate, a diamond substrate or a glass substrate.
4. A planar gallium oxide MOSFET device according to claim 1, characterized in that: The substrate is of N type; and the silicon ion implantation region is an N type silicon ion implantation region.
5. A planar gallium oxide MOSFET device according to claim 1, characterized in that: The first source-drain gate through hole layer, the second source-drain gate through hole layer, the third source-drain gate through hole layer and the fourth source-drain gate through hole layer all include arrays of through holes.
6. A planar gallium oxide MOSFET device according to claim 1, characterized in that: It also includes a gate oxide layer, which is arranged on the gate etching region.
7. A planar gallium oxide MOSFET device according to claim 6, characterized in that: The gate oxide layer is a silicon dioxide oxide layer.
8. The planar gallium oxide MOSFET device according to claim 1, characterized in that: The size of the substrate is 6 inches, and the size of the gallium oxide epitaxial layer is 4 inches.
9. The planar gallium oxide MOSFET device according to claim 1, characterized in that: A top protective layer is also included.
10. The planar gallium oxide MOSFET device according to claim 1, characterized in that: A source field plate metal layer is also included.