SiC field effect transistor with reduced switching loss
By adopting a unique isolation dielectric layer layout in SiC MOSFET devices, the gate-source capacitance Cgs is reduced, which solves the problem of large switching losses of the device and achieves the effect of improving switching characteristics.
Patent Information
- Application Number
- CN202422072742.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-08-26
AI Technical Summary
In SiC MOSFET devices, gate leakage capacitor Cgd and gate source capacitor Cgs affect the device's turn-on process, resulting in large switching losses, and it is difficult for the prior art to effectively reduce these capacitor parameters.
By adopting a unique isolation dielectric layer layout in SiC MOSFET devices, the coupling area between the gate electrode and the source electrode is reduced, thereby reducing gate and source capacitance Cgs.
It effectively reduces the switching loss of SiC MOSFET devices and improves the switching characteristics of the devices.
Smart Images
Figure CN222996955U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor technology, in particular to a SiC field effect transistor for reducing switching losses. Background Art
[0002] The voltage-controlled switching device SiC MOSFET, due to the advantages of the single-polarity structure of MOSFET and the physical property advantages of the third-generation wide-bandgap material SiC, shows better performance than Si MOSFET and Si IGBT devices in both static conduction characteristics, such as reverse breakdown voltage, on-resistance, leakage current, etc., and switching characteristics, such as switching time, switching loss, etc. Especially with the development of new energy vehicles towards the 800V high-voltage platform, SiC MOSFET is considered to be the core device in the future.
[0003] In a SiC MOSFET device, the parameters that determine the switching characteristics of the device are the internal parasitic capacitances, namely the gate-drain capacitance Cgd, the gate-source capacitance Cgs, and the source-drain capacitance Cds. Among them, the gate-drain capacitance Cgd and the gate-source capacitance Cgs affect the turn-on process of the device. When the MOSFET device switches from the off negative voltage to the on positive voltage, it is necessary to first charge the gate-drain capacitance Cgd and the gate-source capacitance Cgs. When the charging reaches the turn-on threshold voltage Vth, the SiC MOSFET device turns on. Therefore, reducing the parameters of the gate-drain capacitance Cgd or the gate-source capacitance Cgs to improve the switching characteristics of the device and reduce the switching loss of the device is a technical problem that the industry urgently needs to solve. Summary of the Utility Model
[0004] In view of the above problems, the utility model provides a SiC field effect transistor for reducing switching losses, which reduces the gate-source capacitance Cgs, improves the switching characteristics of the device, and reduces the switching loss.
[0005] The technical solution of the utility model is as follows:
[0006] The SiC field effect transistor for reducing switching losses includes a back electrode metal layer, a back ohmic contact alloy layer, a SiC Sub layer, a SiC Drift layer, a gate oxide layer, a Poly layer, an isolation dielectric layer, and a front electrode metal layer, which are arranged in sequence from bottom to top;
[0007] The SiC Drift layer is provided with:
[0008] A JFET region extending downward from the top surface of the SiC Drift layer;
[0009] A Pwell region extending downward from the top surface of the JFET region;
[0010] An NP region extending downward from the top surface of the Pwell region;
[0011] The PP region is arranged in the middle of the N&P source electrode contact region NP region;
[0012] The bottom surface of the gate oxide layer is respectively connected to the JFET region, the Pwell region and the NP region;
[0013] The Poly layer is arranged on the top surface of the gate oxide layer;
[0014] The isolation dielectric layer is arranged on the top surface of the Poly layer and is connected to the NP region;
[0015] The ohmic contact alloy layer is arranged on the top surface of the JFET region in the N&P source electrode contact region, and the bottom is respectively connected to the NP region and the PP region;
[0016] The bottom surface of the front electrode metal layer in the N source electrode contact region is connected to the top surface of the isolation dielectric layer; the bottom surface of the front electrode metal layer in the N&P source electrode contact region is respectively connected to the isolation dielectric layer and the ohmic contact alloy layer.
[0017] Specifically, the bottom surface depth of the Pwell region is 0.8um - 1um.
[0018] Specifically, the bottom surface depth of the NP region is 0.3um - 0.5um.
[0019] Specifically, the bottom surface depth of the PP region is 0.6um - 0.8um.
[0020] Specifically, the bottom surface depth of the JFET region > the bottom surface depth of the P-well region by 0.1um - 0.5um.
[0021] Specifically, the thickness of the gate oxide layer is 40nm - 50nm.
[0022] Specifically, the deposition thickness of the Poly layer is 500nm - 1000nm.
[0023] Advantages of the present utility model:
[0024] In a planar gate SiC MOSFET device, one of the components of the gate-source capacitance Cgs is the Cgs composed of the gate electrode - isolation dielectric layer - source electrode, and the size of the Cgs here depends on the thickness of the isolation dielectric layer and the coupling area between the gate electrode and the source electrode. The present utility model adopts a unique layout of the isolation dielectric layer, which greatly reduces the coupling area between the gate electrode and the source electrode in the SiC MOSFET device, thereby reducing the gate-source capacitance Cgs, improving the switching characteristics of the device, and reducing the switching loss. Description of the drawings
[0025] Figure 1It is a top view of the SiC MOSFET device of the present utility model (the JFET region 6, gate oxide layer 7, Poly layer 8, ohmic contact alloy layer 10, and front electrode metal layer 11 are hidden in the figure);
[0026] Figure 2 is Figure 1 The structural diagram in the AA cross-section direction;
[0027] Figure 3 is Figure 1 The structural diagram in the BB cross-section direction;
[0028] Figure 4 It is a top view of a conventional SiC MOSFET device;
[0029] Figure 5 is Figure 4 The structural diagram in the CC cross-section direction;
[0030] In the figure, 1 is the SiC Sub layer, 2 is the SiC Drift layer, 3 is the Pwell region, 4 is the NP region, 5 is the PP region, 6 is the JFET region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the ohmic contact alloy layer, 11 is the front electrode metal layer, 12 is the back ohmic contact alloy layer, and 13 is the back electrode metal layer. Detailed implementation mode
[0031] The present utility model will be described in detail below in combination with specific actual cases. The examples of the embodiments are shown in the drawings, and the schematic implementation modes and descriptions of the present utility model are only used to explain the present utility model and are not used as a limitation to the present utility model.
[0032] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present utility model. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more.
[0033] In the following text, the N-source electrode contact area is Figure 1 The A-A gray area in ; the N&P source electrode contact area is the B-B white area.
[0034] A method for fabricating a SiC field effect transistor with reduced switching losses includes the following steps:
[0035] S100, homoepitaxially grow the SiC Drift layer 2 on the SiC Sub layer 1. The SiC Sub layer 1 serves as a support, and the SiC Drift layer 2 serves as a protection.
[0036] Both the SiC Sub layer 1 and the SiC Drift layer 2 in step S100 have an N-type conductivity type. The thickness of the SiC Sub layer 1 is 170um - 350um, and the doping concentration is 1E19cm -2 ; The thickness of the SiC Drift layer 2 is 5um - 16um, and the doping concentration range is 5E16 - 1.2E16cm -2 .
[0037] S200, after depositing through a mask layer, patterning lithography of the Pwell region, and removing the glue and cleaning on the SiC Drift layer 2, form the Pwell region 3 by Al ion implantation on a medium beam current ion implanter;
[0038] The Pwell region 3 in step S200 has a P-type conductivity type, the bottom depth is 0.8um - 1um, and the doping concentration is 1E17 - 3E18cm -2 . There is a spacing between the bottom surface of the Pwell region 3 and the bottom surface of the SiC Drift layer 2.
[0039] S300, after depositing through a mask layer, etching the mask layer, and removing the glue and cleaning in the Pwell region 3, form the sidewall Spacer layer, and form the NP region 4 by N ion implantation on a large beam current ion implanter. The NP region 4 and the Pwell region 3 together form the device channel region;
[0040] The NP region 4 in step S300 has an N-type conductivity type, the bottom depth is 0.3um - 0.5um, and the doping concentration is 1E18 - 1E19cm -2 . There is a spacing between the bottom surface of the NP region 4 and the bottom surface of the Pwell region 3.
[0041] S400, after depositing through a mask layer, patterning lithography of the PP region, and removing the glue and cleaning on the NP region 4 in the N&P source electrode contact region, form the PP region 5 by Al ion implantation on a large beam current ion implanter. The function of the PP region 5 is to improve the reverse breakdown voltage of the device and at the same time form a parasitic PN junction body diode inside the device as a freewheeling diode;
[0042] The PP region 5 in step S400 has a P-type conductivity type, the bottom depth is 0.6um - 0.8um, and the doping concentration is 1E18 - 1E19cm -2 . The PP region 5 is located in the middle of the NP region 4, and its bottom surface is lower than the bottom surface of the NP region 4.
[0043] In S500, after depositing through a mask layer, lithographing the JFET region pattern, and removing the photoresist and cleaning on the SiC Drift layer 2, the JFET region 6 is formed by N ion implantation on a medium beam current ion implanter. The function of the JFET region 6 is to reduce the device resistance and improve the device performance.
[0044] The conductivity type of the JFET region 6 in step S500 is N-type, the bottom depth > the bottom depth of the P-well region 3 by 0.1 um - 0.5 um, and the doping concentration range is 5E16 - 7E16 cm -2 。
[0045] In S600, after coating and photoresist carbonization on the SiC Drift layer 2, the Pwell region 3, NP region 4, PP region 5, and JFET region 6 are activated and formed by high-temperature ion activation;
[0046] The high-temperature ion activation temperature range in step S600 is 1600 °C - 1700 °C.
[0047] In S700, a gate oxide layer 7 is formed on the SiC Drift layer 2 by dry oxygen oxidation in a gate oxide annealing furnace, and NO gas is introduced for annealing during the process to improve the quality of the gate oxide layer 7;
[0048] The thickness of the gate oxide layer 7 in step S700 is 40 nm - 50 nm.
[0049] In S800, polysilicon Poly is deposited on the SiC Drift layer 2 and the gate oxide layer 7 through an LPCVD device. After that, through pattern lithography, polysilicon Poly etching removal, and photoresist removal and cleaning, the required Poly layer 8 is formed. The function of the Poly layer 8 is to be used as the gate electrode of the device;
[0050] The deposition thickness of the Poly layer 8 in step S800 is 500 nm - 1000 nm.
[0051] In S900, an isolation dielectric layer 9 is formed by depositing an oxide and densifying it on the NP region 4 and the Poly layer 8 through a PECVD device. The function of the isolation dielectric layer 9 is to be used as the dielectric for isolating the gate electrode and the source electrode at the source of the device to avoid short-circuiting between the two;
[0052] The bottom surface of the isolation dielectric layer 9 in the N source electrode contact region is connected to the middle NP region 4;
[0053] The isolation dielectric layer 9 in the N&P source electrode contact region is connected to the NP region 4 on the side of the PP region 5.
[0054] In S1000, an ohmic contact alloy layer 10 is formed by Ni metal sputtering and then rapid thermal annealing on the SiC Drift layer 2 in the N&P source electrode contact region;
[0055] The sputtering thickness of Ni metal in step S1000 is 100 nm.
[0056] S1100, form an electrode layer by Ti / AlCu metal sputtering above the device, and then form the required front electrode metal layer 11 through pattern lithography, etching, and resist stripping and cleaning, which is used as the source electrode of the device.
[0057] The sputtering thickness of Ti / AlCu metal in step S1100 is 100 nm / 5000 nm.
[0058] The bottom surfaces of the front electrode metal layer 11 in the N&P source electrode contact regions are respectively in contact with the isolation dielectric layer 9 and the ohmic contact alloy layer 10.
[0059] S1200, form a back ohmic contact alloy layer 12 on the bottom surface of the SiC Sub layer 1 by Ni metal sputtering and then by laser thermal annealing;
[0060] The sputtering thickness of Ni metal in step S1200 is 100 nm.
[0061] S1300, form a back electrode metal layer 13 on the bottom surface of the back ohmic contact alloy layer 12 by Ti / Ni / Ag metal evaporation, which is used as the drain electrode of the device;
[0062] The evaporation thickness of Ti / Ni / Ag metal in step S1300 is 30 nm / 300 nm / 1200 nm.
[0063] A SiC field effect transistor for reducing switching loss, including a back electrode metal layer 13, a back ohmic contact alloy layer 12, a SiC Sub layer 1, a SiC Drift layer 2, a gate oxide layer 7, a Poly layer 8, an isolation dielectric layer 9, and a front electrode metal layer 11 arranged in sequence from bottom to top;
[0064] The SiC Drift layer 2 is provided with:
[0065] A JFET region 6 extending downward from the top surface of the SiC Drift layer 2; the bottom surface of the JFET region 6 is located above the bottom surface of the SiC Drift layer 2;
[0066] A Pwell region 3 extending downward from the top surface of the JFET region 6, with a spacing between the side and bottom and the JFET region 6;
[0067] An NP region 4 extending downward from the top surface of the Pwell region 3, with a spacing between the bottom surface and the bottom surface of the Pwell region 3;
[0068] The PP region 5 is arranged in the middle of the N&P source electrode contact region NP region 4, and the depth of its downward extension is greater than the depth of the NP region 4;
[0069] The bottom surface of the gate oxide layer 7 is respectively connected to the JFET region 6, the Pwell region 3 and the NP region 4;
[0070] The Poly layer 8 is arranged on the top surface of the gate oxide layer 7;
[0071] The isolation dielectric layer 9 is arranged on the top surface of the Poly layer 8 and is connected to the NP region 4;
[0072] The ohmic contact alloy layer 10 is arranged on the top surface of the JFET region 6 in the N&P source electrode contact region, and the bottom is respectively connected to the NP region 4 and the PP region 5;
[0073] The bottom surface of the front electrode metal layer 11 in the N source electrode contact region is connected to the top surface of the isolation dielectric layer 9; the bottom surface of the front electrode metal layer 11 in the N&P source electrode contact region is respectively connected to the isolation dielectric layer 9 and the ohmic contact alloy layer 10.
[0074] In the planar gate SiC MOSFET device, due to the existence of gate-drain capacitance Cgd, gate-source capacitance Cgs, and source-drain capacitance Cds inside, there are turn-on and turn-off times during the switching process of the device, resulting in switching losses of the device. Among them, the gate-drain capacitance Cgd and the gate-source capacitance Cgs affect the turn-on process of the SiC MOSFET device, and one of the components of the gate-source capacitance Cgs is Cgs composed of the gate electrode - isolation dielectric layer - source electrode. And the size of Cgs here depends on the thickness of the isolation dielectric layer and the coupling area between the gate electrode and the source electrode. The present invention adopts a unique layout of the isolation dielectric layer to cover the N source electrode contact region in the SiC MOSFET device with the isolation dielectric layer 9, thereby greatly reducing the coupling area between the gate electrode and the source electrode here, thereby reducing the gate-source capacitance Cgs, improving the switching characteristics of the device, and reducing the switching losses.
Claims
1. A SiC field effect transistor with reduced switching losses, characterized in that: It comprises a back electrode metal layer (13), a back ohmic contact alloy layer (12), a SiC Sub layer (1), a SiC Drift layer (2), a gate oxide layer (7), a Poly layer (8), an isolation dielectric layer (9) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The SiC Drift layer (2) includes: A JFET region (6) extending downward from the top surface of the SiC Drift layer (2); A Pwell region (3) extending downward from a top surface of the JFET region (6); An NP region (4) extending downward from the top surface of the Pwell region (3); A PP region (5) is arranged in the middle of the N&P source electrode contact region NP region (4); The bottom surface of the gate oxide layer (7) is respectively connected to the JFET region (6), the Pwell region (3) and the NP region (4); The Poly layer (8) is arranged on the top surface of the gate oxide layer (7); The isolation dielectric layer (9) is arranged on the top surface of the Poly layer (8) and is connected to the NP region (4); The ohmic contact alloy layer (10) is arranged on the top surface of the JFET region (6) of the N&P source electrode contact region, and the bottom is respectively connected to the NP region (4) and the PP region (5); The bottom surface of the front electrode metal layer (11) in the N source electrode contact area is connected to the top surface of the isolation dielectric layer (9); and the bottom surfaces of the front electrode metal layer (11) in the N&P source electrode contact area are respectively connected to the isolation dielectric layer (9) and the ohmic contact alloy layer (10).
2. The SiC field effect transistor with reduced switching loss according to claim 1, characterized in that: The bottom surface depth of the Pwell region (3) is 0.8um-1um.
3. The SiC field effect transistor with reduced switching loss according to claim 1, characterized in that: The bottom surface depth of the NP region (4) is 0.3um-0.5um.
4. The SiC field effect transistor with reduced switching loss according to claim 1, characterized in that: The bottom surface depth of the PP region (5) is 0.6um-0.8um.
5. The SiC field effect transistor with reduced switching loss according to claim 1, characterized in that: The bottom depth of the JFET region (6) is greater than the bottom depth of the P-well region (3) by 0.1 um to 0.5 um.
6. The SiC field effect transistor with reduced switching loss according to claim 1, characterized in that: The gate oxide layer (7) has a thickness of 40nm-50nm.
7. The SiC field effect transistor with reduced switching loss according to claim 1, characterized in that: The deposition thickness of the Poly layer (8) is 500nm-1000nm.