IBC battery back structure and IBC battery
By adopting alternate P and N zone structures in IBC batteries, using low-temperature processes and specific layer structures, the problem of high-temperature processes destroying tunneling layers and low-temperature processes is solved, and the mass production and efficiency of the battery are improved.
Patent Information
- Application Number
- CN202421858916.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2034-08-02
AI Technical Summary
In existing IBC batteries, the passivation contact structure of tunneled silicon oxide + doped polysilicon in high-temperature process can easily destroy the tunneling layer, and the low-temperature process film layer is prone to thermal attenuation effect during local laser etching, limiting the mass production and efficiency of the battery.
Alternately arranged P and N regions structures are adopted, wherein the P regions include a second intrinsic amorphous silicon layer arranged from the inside to the outside, a second boron-doped nanocrystalline silicon oxide layer, a second boron-doped nanocrystalline silicon layer and a second TCO transparent conductive layer; the N regions include a tunneling oxide layer arranged from the inside to the outside, a phosphorus-doped polysilicon layer and a SiNx isolation layer, which avoids high temperature defects through low temperature processes and does not rely on laser processing to reduce the thermal attenuation effect.
The back structure of the IBC battery is stably prepared under low temperature processes, avoiding the risk of high-temperature processes destroying the tunnel layer, and reducing the thermal attenuation effect caused by laser processing, thereby improving the mass production and efficiency of the battery.
Smart Images
Figure CN223007834U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of solar cells, and particularly relates to a back structure of an IBC cell and an IBC cell. Background Art
[0002] For the interdigitated back contact cell (IBC), since there is no light shielding on the front side, the conversion efficiency that can be achieved is significantly higher than that of other types of solar cells. In particular, it can be stacked with a tunneling passivation contact structure, thereby further improving the conversion efficiency of the cell, and has a very high application prospect.
[0003] At present, there are mainly two types of back passivation contact structures used in IBC cells. One is a passivation contact structure of tunneling silicon oxide + doped polysilicon (TBC), which requires a high-temperature process. However, the high temperature required for boron doping in the process of preparing IBC cells not only easily damages the tunneling layer, but also the doping amount of B is affected by the subsequent etching rate. These reasons limit the mass production and efficiency of TBC cells; the other is a passivation contact structure of intrinsic amorphous silicon + doped amorphous silicon / microcrystalline silicon (HBC), which uses a low-temperature process. However, when using the method of laser local etching to obtain the isolated P region and N region, the film layer is relatively sensitive to the thermal effect of the laser, and the thermal attenuation effect is likely to occur. Summary of the Utility Model
[0004] The purpose of the utility model is to provide a back structure of an IBC cell and an IBC cell to solve the above technical problems.
[0005] To solve the above technical problems, the utility model provides a back structure of an IBC cell, including: P regions and N regions that are alternately arranged and spaced on the back side of the silicon wafer; wherein
[0006] The P region includes a second intrinsic amorphous silicon layer, a second boron-doped nanocrystalline silicon oxide layer, a second boron-doped nanocrystalline silicon layer, and a second TCO transparent conductive layer arranged from the inside to the outside;
[0007] The N region includes a tunneling oxide layer, a phosphorus-doped polysilicon layer, and a SiNx isolation layer arranged from the inside to the outside.
[0008] In an embodiment of the present application, the N region further includes a first intrinsic amorphous silicon layer, a first boron-doped nanocrystalline silicon oxide layer, a first boron-doped nanocrystalline silicon layer, and a first TCO transparent conductive layer that are sequentially arranged outside the SiNx isolation layer.
[0009] In an embodiment of the present application, the thickness of the second intrinsic amorphous silicon layer is 3-8 nm.
[0010] In an embodiment of the present application, the thickness of the second boron-doped nanocrystalline silicon oxide layer is 1-3 nm.
[0011] In one embodiment of the present application, the thickness of the second boron-doped nanocrystalline silicon layer is 25 - 35 nm.
[0012] In one embodiment of the present application, the thickness of the tunneling oxide layer is 1 - 2 nm;
[0013] The thickness of the phosphorus-doped polysilicon layer is 80 - 150 nm;
[0014] The thickness of the SiNx isolation layer is 60 - 80 nm.
[0015] In one embodiment of the present application, the thickness of the first intrinsic amorphous silicon layer is 3 - 8 nm.
[0016] In one embodiment of the present application, the back structure of the IBC cell further includes an isolation region located between the P region and the N region; SiNx is provided in the isolation region.
[0017] In one embodiment of the present application, electrodes are provided in both the P region and the N region;
[0018] The end of the electrode in the P region is disposed in the second TCO transparent conductive layer, and the end of the electrode in the N region is disposed in the phosphorus-doped polysilicon layer.
[0019] Correspondingly, the present application also provides an IBC cell, including: a silicon wafer, and the back structure of the IBC cell as described above; wherein
[0020] On the front side of the silicon wafer, a boron diffusion layer, an AlOx passivation layer, and a SiNx passivation and antireflection layer are sequentially provided from inside to outside.
[0021] The beneficial effects of the present utility model are that the back structure of the IBC cell of the present utility model includes: a P region and an N region that are alternately arranged and spaced on the back side of the silicon wafer; wherein the P region includes a second intrinsic amorphous silicon layer, a second boron-doped nanocrystalline silicon oxide layer, a second boron-doped nanocrystalline silicon layer, and a second TCO transparent conductive layer provided from inside to outside; the N region includes a tunneling oxide layer, a phosphorus-doped polysilicon layer, and a SiNx isolation layer provided from inside to outside. The structure of the P region of the back structure of the IBC cell of the present utility model can adopt a low-temperature process, overcoming the defect that the high temperature required for boron doping in the process of preparing an IBC cell by a high-temperature process in the prior art is likely to damage the tunneling layer; in addition, the functional layers in the P region do not need to be laser processed, overcoming the defect that the film layers prepared by a low-temperature process in the prior art are prone to thermal attenuation effects in the method of local laser etching.
[0022] Other features and advantages of the present utility model will be described in the subsequent specification, and in part, will become apparent from the specification or will be understood by implementing the present utility model. The objectives and other advantages of the present utility model are achieved and obtained by the structures specifically pointed out in the specification and the drawings.
[0023] In order to make the above-mentioned objectives, features, and advantages of the present utility model more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Brief Description of the Drawings
[0024] In order to more clearly illustrate the specific embodiments of the present utility model or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0025] Figure 1 is a schematic diagram of a preferred embodiment of the IBC battery of the present utility model.
[0026] In the figure:
[0027] Silicon wafer 1;
[0028] P region 2, second intrinsic amorphous silicon layer 21, second boron-doped nanocrystalline silicon oxide layer 22, second boron-doped nanocrystalline silicon layer 23, second TCO transparent conductive layer 24;
[0029] N region 3, tunneling oxide layer 31, phosphorus-doped polysilicon layer 32, SiNx isolation layer 33, first intrinsic amorphous silicon layer 34, first boron-doped nanocrystalline silicon oxide layer 35, first boron-doped nanocrystalline silicon layer 36, first TCO transparent conductive layer 37;
[0030] Isolation region 4, boron diffusion layer 5, AlOx passivation layer 6, SiNx passivation and antireflection layer 7, electrode 8. Detailed Description of the Embodiments
[0031] In order to make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the following will clearly and completely describe the technical solutions of the present utility model in conjunction with the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present utility model.
[0032] See Figure 1, in an embodiment of the present application, the back structure of the IBC cell includes: a P region 2 and an N region 3 that are alternately arranged and spaced on the back of the silicon wafer 1; wherein the P region 2 includes a second intrinsic amorphous silicon layer 21, a second boron-doped nanocrystalline silicon oxide layer 22, a second boron-doped nanocrystalline silicon layer 23, and a second TCO transparent conductive layer 24 arranged from the inside out; the N region 3 includes a tunneling oxide layer 31, a phosphorus-doped polysilicon layer 32, and a SiNx isolation layer 33 arranged from the inside out.
[0033] Furthermore, the N region 3 further includes a first intrinsic amorphous silicon layer 34, a first boron-doped nanocrystalline silicon oxide layer 35, a first boron-doped nanocrystalline silicon layer 36, and a first TCO transparent conductive layer 37 that are sequentially arranged outside the SiNx isolation layer 33.
[0034] In this embodiment, the P region 2 can be a heterojunction structure.
[0035] Optionally, the thickness of the second intrinsic amorphous silicon layer 21 is 3 - 8 nm; it can be obtained by the PECVD deposition method.
[0036] Optionally, the thickness of the second boron-doped nanocrystalline silicon oxide layer 22 is 1 - 3 nm; it can be obtained by the PECVD deposition method.
[0037] Optionally, the thickness of the second boron-doped nanocrystalline silicon layer 23 is 25 - 35 nm; it can be obtained by the PECVD deposition method.
[0038] Of course, in some embodiments, the second intrinsic amorphous silicon layer 21, the second boron-doped nanocrystalline silicon oxide layer 22, and the second boron-doped nanocrystalline silicon layer 23 can be obtained in one step by the PECVD method.
[0039] In this embodiment, the P region can use the HJT low-temperature preparation method to prepare the second boron-doped nanocrystalline silicon layer 23, and its thickness is much thinner than that of the boron-doped Poly-Si prepared by the high-temperature process. The thickness of the boron-doped Poly-Si prepared by the high-temperature process is generally between 200 nm and 300 nm. Moreover, in the high-temperature process, the doped boron atoms are likely to pass through the tunneling oxide layer and damage passivation. Therefore, the P region structure of this embodiment can overcome the defects of the high-temperature process.
[0040] Furthermore, in this embodiment, the N region 3 can be a high-temperature TOPCon structure.
[0041] In this embodiment, optionally, the thickness of the tunneling oxide layer 31 can be 1 - 2 nm; the thickness of the phosphorus-doped polysilicon layer 32 can be 80 - 150 nm.
[0042] Preferably, the thickness of the first intrinsic amorphous silicon layer 34 is 3 - 8 nm; the intrinsic amorphous silicon has a low light transmittance in the wavelength range from 300 nm to 600 nm in the ultraviolet region. Therefore, during the process of laser patterning to remove the boron-doped nanocrystalline silicon in the N region, the first intrinsic amorphous silicon layer 34 can prevent light from passing through the isolation layer and the amorphous silicon layer to reach the phosphorus-doped polysilicon layer, thus avoiding damage to the phosphorus-doped polysilicon layer. Optionally, this first intrinsic amorphous silicon layer 34 can be obtained by PECVD method.
[0043] Furthermore, the thickness of the SiNx isolation layer 33 is 60 - 80 nm.
[0044] In this embodiment, the SiNx isolation layer 33 not only serves to isolate the P and N regions, but also acts as a back surface passivation layer.
[0045] In this embodiment, optionally, the back surface structure of the IBC cell further includes an isolation region 4 located between the P region 2 and the N region 3; SiNx is provided in the isolation region 4.
[0046] In this embodiment, optionally, electrodes 8 are provided in both the P region 2 and the N region 3. The end of the electrode 8 in the P region 2 is disposed within the second TCO transparent conductive layer 24, and the end of the electrode 8 in the N region 3 is disposed within the phosphorus-doped polysilicon layer 32.
[0047] See Figure 1 , based on the above embodiments, this embodiment further provides an IBC cell, including: a silicon wafer 1, and the back surface structure of the IBC cell as described above.
[0048] In this embodiment, the silicon wafer 1 can be an N-type silicon substrate.
[0049] Furthermore, on the front surface of the silicon wafer 1, a boron diffusion layer 5, an AlOx passivation layer 6, and a SiNx passivation and antireflection layer 7 are sequentially provided from the inside out.
[0050] In an application scenario, the manufacturing process steps of an IBC cell using the back surface structure of the IBC cell in this embodiment are as follows:
[0051] 1. Texturing;
[0052] 2. Boron diffusion;
[0053] 3. Back surface polishing;
[0054] 4. Deposit a tunneling oxide layer 31 and an intrinsic polysilicon layer on the back surface;
[0055] 5. Perform phosphorus diffusion on the back surface to form a phosphorus-doped polysilicon layer 32 and PSG in the intrinsic polysilicon layer;
[0056] 6. Modify the PSG in the P region or directly remove it;
[0057] 7. Remove the N+Poly, tunneling oxide layer in the P region, and the remaining PSG on the back surface by alkaline etching;
[0058] 8. Deposit the SiNx isolation layer 33 on the entire back surface;
[0059] 9. Remove the SiNx isolation layer in the P region by laser;
[0060] 10. By PECVD method, first deposit an intrinsic amorphous silicon layer (34, 21) on the back surface, then deposit a boron-doped nanocrystalline silicon oxide layer (35, 22), and finally deposit a boron-doped nanocrystalline silicon layer (36, 23);
[0061] 11. By magnetron sputtering method, deposit the transparent conductive film TCO (37, 24) on the entire back surface;
[0062] 12. Utilize the characteristics of laser patterning to remove, in the metallization region of the N region, the first boron-doped nanocrystalline silicon layer 36, the first boron-doped nanocrystalline silicon oxide layer 35, and the first intrinsic amorphous silicon layer 34, with the laser etching width being 200 - 300 um; at the same time, remove the TCO layer, boron-doped nanocrystalline silicon layer, boron-doped nanocrystalline silicon oxide layer, and amorphous silicon layer in the isolation region, and the laser etching width < the width of the isolation region;
[0063] 13. Remove the BSG on the front surface and the SiNx isolation layer in the laser opening region of the N region by HF cleaning;
[0064] 14. Deposit the AlOx passivation layer and the SiNx passivation and antireflection layer on the front surface;
[0065] 15. Metallization, curing, and optical injection.
[0066] During the above preparation process, the functional layer structure of the N region can be prepared through steps 1 - 9, that is, forming the tunneling oxide layer 31, the phosphorus-doped polysilicon layer 32, and the SiNx isolation layer 33; the structure of the P region functional layer can be prepared by low-temperature processes through steps 10 and 11, that is, forming the second intrinsic amorphous silicon layer 21, the second boron-doped nanocrystalline silicon oxide layer 22, the second boron-doped nanocrystalline silicon layer 23, and the second TCO transparent conductive layer 24.
[0067] The structure of the P region functional layer overcomes the defect that in the process of preparing IBC cells by high-temperature processes in the prior art, the high temperature required for boron doping is likely to damage the tunneling layer; in addition, the P region functional layer does not require laser processing, overcoming the defect that the film layers prepared by low-temperature processes in the prior art are prone to thermal attenuation effects in the method of laser local etching.
[0068] All components (components without specific structures) selected in this application are common standard components or components known to those skilled in the art, and their structures and principles can be learned by those skilled in the art through technical manuals or obtained through conventional experimental methods.
[0069] In the description of the embodiments of the present utility model, unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0070] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present utility model. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0071] Taking the above ideal embodiments of the present utility model as an inspiration, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of the present utility model. The technical scope of the present utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. An IBC battery back structure, characterized in that: include: P regions (2) and N regions (3) are alternately arranged and spaced apart on the back side of the silicon wafer (1); in The P region (2) comprises a second intrinsic amorphous silicon layer (21), a second boron-doped nanocrystalline silicon oxide layer (22), a second boron-doped nanocrystalline silicon layer (23) and a second TCO transparent conductive layer (24) arranged from the inside to the outside; The N region (3) comprises a tunneling oxide layer (31), a phosphorus-doped polysilicon layer (32), and a SiNx isolation layer (33) arranged from the inside to the outside.
2. The IBC battery back structure according to claim 1, characterized in that: The N region (3) further comprises a first intrinsic amorphous silicon layer (34), a first boron-doped nanocrystalline silicon oxide layer (35), a first boron-doped nanocrystalline silicon layer (36) and a first TCO transparent conductive layer (37) which are sequentially arranged outside the SiNx isolation layer (33).
3. The IBC battery back structure according to claim 1, characterized in that: The thickness of the second intrinsic amorphous silicon layer (21) is 3-8 nm.
4. The IBC battery back structure according to claim 1, characterized in that: The thickness of the second boron-doped nanocrystalline silicon oxide layer (22) is 1-3 nm.
5. The IBC battery back structure according to claim 1, characterized in that: The thickness of the second boron-doped nanocrystalline silicon layer (23) is 25-35 nm.
6. The IBC battery back structure according to claim 1, characterized in that: The thickness of the tunneling oxide layer (31) is 1-2 nm; The thickness of the phosphorus-doped polysilicon layer (32) is 80-150 nm; The thickness of the SiNx isolation layer (33) is 60-80 nm.
7. The IBC battery back structure according to claim 2, characterized in that: The thickness of the first intrinsic amorphous silicon layer (34) is 3-8 nm.
8. The IBC battery back structure according to claim 1, characterized in that: It also includes an isolation region (4) located between the P region (2) and the N region (3); SiNx is arranged in the isolation region (4).
9. The IBC battery back structure according to claim 1, characterized in that: Electrodes (8) are provided in both the P region (2) and the N region (3); The end of the electrode (8) in the P region (2) is arranged in the second TCO transparent conductive layer (24), and the end of the electrode (8) in the N region (3) is arranged in the phosphorus-doped polysilicon layer (32).
10. An IBC battery, characterized in that: include: A silicon wafer (1), and an IBC battery back structure as claimed in any one of claims 1 to 8; in The front side of the silicon wafer (1) is provided with a boron diffusion layer (5), an AlOx passivation layer (6) and a SiNx passivation anti-reflection layer (7) in sequence from the inside to the outside.