Mask plate of groove type MOSFET wafer
By designing alternating transverse and longitudinal trench patterns in the mask plate of the trench type MOSFET wafer, the problem of severe warping due to excessive internal stress is solved, and the effect of reducing warpage and improving production convenience is achieved.
Patent Information
- Application Number
- CN202422243091.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2034-09-12
AI Technical Summary
During the trench MOSFET wafer production process, the internal stress caused by the deep trench etching and subsequent filling process is too large, resulting in severe warping of the wafer, affecting the normal operation of the production equipment and the integrity of the wafer.
A mask plate is designed that contains two patterns: a transverse groove pattern and a longitudinal groove pattern, which are arranged alternately with each other and are laid out on the same mask plate to form an alternating groove layer structure.
Through this mask design, transverse and longitudinal trenches can be formed on the wafer at the same time, reducing the internal stress of the wafer during processing, reducing warpage, improving the convenience of wafer production, and reducing the risk of chipping.
Smart Images
Figure CN223022529U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor power devices, in particular to a mask plate for a trench MOSFET wafer. Background Art
[0002] With the growth of the demand for electronic consumer products, the demand for MOSFET devices is increasing. The trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is widely used in the low-voltage power field because of its high device integration, low gate-drain charge density, large current capacity, and low switching loss.
[0003] The trench layer mask plate of the traditional trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is in a single direction, such as a single horizontal trench mask plate or a single vertical trench mask plate. In the production process of large-size wafers of trench MOSFETs, due to the etching of deep trenches and the filling of subsequent different materials, large internal stress will be generated in the wafers, resulting in serious warping of the wafers, and the production equipment cannot process the wafers normally, leading to wafer fragmentation and even production suspension.
[0004] Therefore, there is an urgent need for a way to relieve the warping of wafers. Summary of the Utility Model
[0005] In view of at least some of the problems and defects in the prior art, the embodiments of the utility model disclose a mask plate for a trench MOSFET wafer to relieve the problem that the wafers of the existing trench MOSFETs generate large internal stress and are severely warped.
[0006] Specifically, a mask plate for a trench MOSFET wafer provided by an embodiment of the utility model includes: a mask substrate; a lithography pattern disposed on the mask substrate, the lithography pattern being used to form a trench layer on the wafer during lithography; wherein the lithography pattern includes a first trench pattern and a second trench pattern, the first trench pattern contains a plurality of first lines arranged at intervals, the first lines extend in a first direction, the second trench pattern contains a plurality of second lines arranged at intervals, the second lines extend in a second direction, and the first direction is perpendicular to the second direction.
[0007] The mask for the trench MOSFET wafer provided by the embodiment of the present utility model is composed of two patterns, and the two patterns are a lateral trench pattern and a longitudinal trench pattern respectively. Thus, the wafer obtained by lithography using the mask provided by the embodiment of the present utility model can have both lateral trenches and longitudinal trenches at the same time, which can reduce the internal stress during the wafer processing, reduce the wafer warpage, and not only facilitate the wafer production, but also reduce the risk of chip breakage. In addition, arranging the two single-direction trench patterns on the same mask is more convenient for the layout of other layers compared with the way of having multiple partitions or multiple line directions in a single trench pattern in the prior art mask, thus avoiding affecting the source area after wafer lithography.
[0008] In an embodiment of the present utility model, the size of the first trench pattern is the same as that of the second trench pattern.
[0009] In an embodiment of the present utility model, the number of the lithography patterns is multiple, and two adjacent lithography patterns are different.
[0010] In an embodiment of the present utility model, in the first direction, the first trench pattern and the second trench pattern are arranged alternately.
[0011] In an embodiment of the present utility model, in the second direction, the first trench pattern and the second trench pattern are arranged alternately.
[0012] In an embodiment of the present utility model, there is a gap between two adjacent lithography patterns.
[0013] In an embodiment of the present utility model, in the first direction, there is a first gap between the first trench pattern and the second trench pattern; in the second direction, there is a second gap between the first trench pattern and the second trench pattern; the distance of the first gap is equal to the distance of the second gap.
[0014] In an embodiment of the present utility model, the number of the first trench patterns is multiple, the number of the second trench patterns is multiple, and the number of the first trench patterns is the same as that of the second trench patterns.
[0015] In an embodiment of the present utility model, it further includes: a dicing groove, which is arranged on the mask substrate and located between the first trench pattern and the second trench pattern.
[0016] As can be seen from the above, the above technical features of the present utility model may have one or more of the following beneficial effects: The mask plate of the trench MOSFET wafer provided by the embodiment of the present utility model is composed of two patterns, and the two patterns are a horizontal trench pattern and a vertical trench pattern respectively. Therefore, the wafer obtained by lithography using the mask plate provided by the embodiment of the present utility model can have both horizontal trenches and vertical trenches at the same time, which can reduce the internal stress during the wafer processing, reduce the wafer warpage, facilitate wafer production, and reduce the risk of wafer breakage. In addition, by arranging the two single-direction trench patterns on the same mask plate, it is more convenient for other layer layouts compared with the prior art method in which a single trench pattern in the mask plate has multiple partitions or multiple line directions, thus avoiding affecting the source area after wafer lithography. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present utility model, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.
[0018] Figure 1 FIG. is a schematic structural diagram of a mask plate of a trench MOSFET wafer provided by an embodiment of the present utility model.
[0019] Figure 2 FIG. is another schematic structural diagram of a mask plate of a trench MOSFET wafer provided by an embodiment of the present utility model.
[0020] DESCRIPTION OF REFERENCE NUMERALS:
[0021] 10 - Mask plate of trench MOSFET wafer; 100 - Mask substrate; 200 - Lithography pattern; 210 - First trench pattern; 220 - Second trench pattern; 400 - Spacing; 410 - First spacing; 420 - Second spacing; 500 - Dicing slot. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0022] In order to make the objectives, technical solutions, and advantages of the present utility model clearer, the technical solutions of the present utility model will be clearly and completely described below in conjunction with the specific embodiments of the present utility model and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.
[0023] It should be noted that the directional terms mentioned in the embodiments of the present utility model, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model. For the sake of understanding and description convenience, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, but the present utility model is not limited thereto.
[0024] It can be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" another component, the component can be directly on the other component, or there can also be an intermediate component. Additionally, in the specification, unless explicitly described to the contrary, the word "comprising" will be understood to mean including the component, but not excluding any other components. Furthermore, in the specification, "on..." means located above or below the target component, and does not mean that it must be located on the top above based on gravity.
[0025] The following will describe in detail some embodiments of the present utility model with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0026] As Figure 1 shown, an embodiment of the present utility model provides a mask 10 for a trench-type MOSFET wafer. The mask 10 for a trench-type MOSFET wafer provided by the embodiment of the present utility model is, for example, applied to the lithography process in wafer production. Specifically, the mask 10 for a trench-type MOSFET wafer, for example, includes a mask substrate 100 and a lithography pattern 200. The lithography pattern 200 is, for example, disposed on the mask substrate 100, and the lithography pattern 200 is, for example, used to form a trench layer on the wafer during lithography. In the lithography process of wafer production, light, for example, passes through the lithography pattern 200 to transfer the lithography pattern 200 onto the photoresist to form a trench layer on the wafer. Among them, the material of the mask substrate 100 is, for example, quartz glass, and quartz glass has advantages such as good light transmittance, good chemical stability, and low thermal expansion coefficient, so as to improve the quality and yield after wafer lithography.
[0027] Furthermore, referring again to Figure 1 , the lithography pattern 200, for example, includes a first trench pattern 210 and a second trench pattern 220. Among them, the first trench pattern 210, for example, includes a plurality of first lines arranged at intervals, the first lines, for example, extend along a first direction, the second trench pattern 220, for example, includes a plurality of second lines arranged at intervals, the second lines, for example, extend along a second direction, and the first direction is, for example, perpendicular to the second direction. For example, the first direction is, for example, the Figure 1 x direction in Figure 1In the y direction, the x direction is perpendicular to the y direction, for example. Among them, the first trench pattern 210 is used to form a first trench layer on the wafer during lithography, for example Figure 1 As shown in, the first trench pattern 210 can be defined as a longitudinal trench pattern, for example, and the first trench layer formed on the wafer by using it can be defined as a longitudinal trench layer. The second trench pattern 220 is used to form a second trench layer on the wafer during lithography, for example Figure 1 As shown in, the second trench pattern 220 can be defined as a transverse trench pattern, for example, and the second trench layer formed on the wafer by using it can be defined as a transverse trench layer.
[0028] The mask of the trench-type MOSFET wafer provided by the embodiment of the present invention is composed of two patterns, and the two patterns are a transverse trench pattern and a longitudinal trench pattern respectively. Thus, the wafer obtained by lithography using the mask provided by the embodiment of the present invention can have both transverse trenches and longitudinal trenches at the same time, and further can reduce the internal stress of the wafer during the processing, reduce the warpage of the wafer, which is not only convenient for wafer production, but also can reduce the risk of chip breakage. In addition, arranging the two single-direction trench patterns on the same mask is more convenient for the layout of other layers than the way of having multiple partitions or multiple line directions in a single trench pattern in the existing mask, thus avoiding affecting the source area of the wafer after lithography.
[0029] In a specific embodiment, the size of the first trench pattern 210 is the same as that of the second trench pattern 220, for example, so that the widths of the first trench layer and the second trench layer formed after wafer lithography are consistent.
[0030] Continuing from the above, the number of the lithography patterns 200 is multiple, and two adjacent lithography patterns 200 are different. Specifically, in the first direction (for example Figure 1 the x direction in), the first trench pattern 210 and the second trench pattern 220 are alternately arranged, and in the second direction (for example Figure 1 the y direction in), the first trench pattern 210 and the second trench pattern 220 are alternately arranged. For example, for example, see Figure 1 , the lithography pattern 200 is four, for example, and any two adjacent lithography patterns 200 are different. In this way, the first trench pattern 210 and the second trench pattern 220 can be alternately arranged, so that the first trench layer and the second trench layer on the lithographed wafer can be alternately arranged, and further the internal stress of the wafer during the processing can be reduced, thereby reducing the warpage of the wafer.
[0031] Furthermore, see again Figure 1, there is a gap 400 between two adjacent lithography patterns 200, so that there is a spacing between adjacent trench layers on the wafer after lithography. Specifically, in the first direction (e.g., the x-direction in Figure 1 ), there is a first gap 410 between the first trench pattern 210 and the second trench pattern 220; in the second direction (e.g., the y-direction in Figure 1 ), there is a second gap 420 between the first trench pattern 210 and the second trench pattern 220; the distance of the first gap 410 is equal to the distance of the second gap 420. In this way, the spacing between the first trench layer and the second trench layer formed on the wafer after lithography can be made equal, thereby improving the regularity of the distribution of the trench layers on the wafer, and thus reducing the warpage degree of the wafer.
[0032] In a specific embodiment, the number of the first trench patterns 210 is, for example, multiple, the number of the second trench patterns 220 is, for example, multiple, and the number of the first trench patterns 210 is the same as the number of the second trench patterns 220. For example, referring to Figure 1 , the first trench pattern 210 is, for example, two, and the second trench pattern is also, for example, two. In this way, the areas of the first trench layer and the second trench layer on the wafer after lithography are the same, and each of them accounts for 50% of the trench layer area, that is, the first trench layer and the second trench layer are 1:1. Thus, such a design can further reduce the internal stress during the wafer processing, that is, further reduce the warpage degree of the wafer.
[0033] In addition, referring to Figure 2 , the mask 10 of the trench MOSFET wafer further includes, for example, a dicing slot 500. The dicing slot 500 is disposed on the mask substrate 100 and is located between the first trench pattern 210 and the second trench pattern 220. Specifically, the dicing slot 500 is, for example, located in the gap between the first trench pattern 210 and the second trench pattern 220, so as to separate the first trench pattern 210 and the second trench pattern 220. For example, the width of the dicing slot 500 is, for example, 40 microns to 150 microns. The dicing slot 500 is, for example, an interval structure for separating the first trench layer and the second trench layer on the wafer after lithography. Thus, during the subsequent wafer processing, if the wafer needs to be cut, it can be accurately cut at the position of the dicing slot 500.
[0034] In summary, the mask of the trench MOSFET wafer provided by the embodiment of the present invention is composed of two patterns, namely a horizontal trench pattern and a vertical trench pattern. Therefore, the wafer obtained by lithography using the mask provided by the embodiment of the present invention can have both horizontal trenches and vertical trenches at the same time, which can reduce the internal stress during the wafer processing and reduce the wafer warpage. This not only facilitates wafer production but also reduces the risk of wafer breakage. In addition, by arranging the two single-direction trench patterns on the same mask, it is more convenient for the layout of other layers compared to the prior art method where a single trench pattern in the mask has multiple partitions or multiple line directions, thus avoiding affecting the source area after wafer lithography.
[0035] It can be understood that the foregoing embodiments are only exemplary descriptions of the present invention. On the premise that there is no conflict in technical features, no contradiction in structure, and no violation of the invention purpose of the present invention, the technical solutions of each embodiment can be arbitrarily combined and used.
[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A mask for a trench MOSFET wafer, characterized in that: include: Mask substrate; A photolithography pattern is arranged on the mask substrate, and the photolithography pattern is used to form a groove layer on the wafer during photolithography; The photolithography pattern includes a first groove pattern and a second groove pattern, the first groove pattern contains a plurality of first lines arranged at intervals, the first lines extend along a first direction, the second groove pattern contains a plurality of second lines arranged at intervals, the second lines extend along a second direction, and the first direction is perpendicular to the second direction.
2. The mask for a trench MOSFET wafer as claimed in claim 1, characterized in that: A size of the first groove pattern is the same as a size of the second groove pattern.
3. The mask for a trench MOSFET wafer as claimed in claim 1, characterized in that: There are multiple photolithography patterns, and two adjacent photolithography patterns are different.
4. The mask for a trench MOSFET wafer as claimed in claim 3, characterized in that: In the first direction, the first groove patterns and the second groove patterns are arranged alternately.
5. The mask for a trench MOSFET wafer as claimed in claim 3, characterized in that: In the second direction, the first groove patterns and the second groove patterns are arranged alternately.
6. The trench MOSFET wafer mask as claimed in claim 3, characterized in that: There is a gap between two adjacent photolithography patterns.
7. The mask for a trench MOSFET wafer as claimed in claim 6, characterized in that: In the first direction, there is a first interval between the first groove pattern and the second groove pattern; in the second direction, there is a second interval between the first groove pattern and the second groove pattern; and the distance of the first interval is equal to the distance of the second interval.
8. The mask for a trench MOSFET wafer as claimed in claim 3, characterized in that: The number of the first groove patterns is plural, the number of the second groove patterns is plural, and the number of the first groove patterns is the same as the number of the second groove patterns.
9. The mask for a trench MOSFET wafer according to any one of claims 1 to 8, characterized in that: Also includes: The scribing groove is disposed on the mask substrate and is located between the first groove pattern and the second groove pattern.