High-voltage-resistant isolation serial interface circuit
By designing a high-voltage isolation serial interface circuit and using a serial isolation structure of transformers and high-voltage isolation capacitors, the problem that the existing technology cannot meet the 15KV high-voltage isolation is solved, and the maximum withstand voltage reaches 22KV is achieved, which is suitable for high-voltage isolation applications in a large range.
Patent Information
- Application Number
- CN202422044068.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2034-08-22
AI Technical Summary
The existing technology cannot meet the needs of 15KV high-voltage isolation, and the isolation voltage of existing isolation chips and optoelectronic isolation circuits is limited, which cannot meet the requirements of high-voltage isolation applications.
A high-voltage isolation serial interface circuit is designed, and the serial isolation of devices such as transformer T1, transformer T2, high-voltage isolation capacitors C1 to C4 is used to increase the isolation voltage by increasing the magnetic ring diameter of the transformer and the diameter of the high-voltage isolation capacitor, so as to achieve the maximum withstand voltage reaching 22KV.
It achieves the satisfaction of 15KV high-voltage isolation, and further improves the voltage withstandness by adjusting the design parameters, adapting to high-voltage isolation applications within a large range, with strong practical flexibility.
Smart Images
Figure CN223022677U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical isolation interface circuits, and particularly relates to a high-voltage-resistant isolation serial interface circuit. Background Art
[0002] For the equipment on the electrical railway track line, since the power supply voltage of the electrical railway is as high as 15 KV, a serial interface is used when connecting two independent devices on two rails. The electrical railway requires that the two rails be absolutely electrically isolated, so the two serial interfaces must meet the requirement of 15 KV high-voltage isolation.
[0003] The high-voltage isolation function is related to technologies such as isolation interface chips and optoelectronic isolation. Among them, the isolation interface chip actually integrates a miniaturized isolation capacitor in the chip. The advantages are low price, simple circuit, and small volume. Common models include ADUM1201, π121M31, etc.; the circuit solution using optocouplers to complete optoelectronic isolation is more widely used. Its circuit is not complex and requires 2 optocouplers and supporting triodes or operational amplifier circuits to cooperate to complete the function.
[0004] The isolation voltage of the existing technical solutions is limited. Generally, the isolation voltage of the isolation chip type is 3 KV, and the highest can reach 6 KV for a short time; the main high-voltage isolation ability of the optoelectronic isolation circuit comes from the optocoupler. The withstand voltage level of the low-voltage model is 50 - 500 V, and the high-voltage one is 1000 V - 3000 V. These two existing solutions cannot meet the needs of 15 KV high-voltage isolation applications. Therefore, a high-voltage-resistant isolation serial interface circuit is proposed. Summary of the Utility Model
[0005] The purpose of the utility model is to provide a high-voltage-resistant isolation serial interface circuit, the circuit is relatively simple, its highest withstand voltage can meet the 15 KV high-voltage isolation application; various schemes can be adopted to adjust the highest withstand voltage value, which can meet the high-voltage isolation applications in a wide range, and it has strong practical flexibility, so as to solve the problems raised in the above background art.
[0006] To achieve the above object, the present utility model provides the following technical solutions: A high-voltage-resistant isolated serial interface circuit includes a modulation signal transmission circuit, a modulation signal reception circuit, CPU1, and CPU2. The input end of the modulation signal transmission circuit is connected to the input end of CPU1, the output end of the modulation signal transmission circuit is connected to the input end of the modulation signal reception circuit, the output end of the modulation signal reception circuit is connected to the signal input end of the modulation signal reception circuit, and the output end of the modulation signal reception circuit is connected to the signal end of CPU2; The modulation signal transmission circuit includes a transformer T1, a transformer T2, high-voltage isolation capacitors C1, C2, C3, and C4. The 1st terminal of the transformer T1 is connected to the I / 01 terminal input of the CPU, the 2nd terminal of the transformer T1 is connected to the I / 02 terminal input of the CPU, the 3rd terminal of the transformer T1 is connected to the input end of the capacitor C1, the output end of the capacitor C1 is connected to the input end of the capacitor C2, and the output end of the capacitor C2 is connected to the 1st terminal of the transformer T2; The 4th terminal of the transformer T1 is connected to the input end of the capacitor C3, the output end of the capacitor C3 is connected to the input end of the capacitor C4, and the capacitor C4 of the capacitor C4 is connected to the 2nd terminal of the transformer T2; The modulation signal reception circuit includes an amplification and detection circuit and a comparison circuit. The 3rd terminal of the transformer T2 is connected to the 1st terminal of the amplification and detection circuit U1, the 4th terminal of the transformer T2 is connected to the 2nd terminal of the amplification and detection circuit, the output end of the amplification and detection circuit is connected to the input end of the comparison circuit, and the output end of the comparison circuit is connected to the USART_RX terminal of CPU2.
[0007] Preferably, the variable modulation signal transmitting circuit further includes a power amplifier Q1, a power amplifier Q2, and a connecting wire rubber head J6. The base of the power amplifier Q1 is connected to the output terminal of the resistor R285 and is connected to the input terminal of the resistor R288. The output terminal of the resistor R288 is grounded. The input terminal of the resistor R285 is connected to the output terminal of the capacitor C1, and the input terminal of the capacitor C1 is connected to the input of the DRV_TTL_TX+ terminal of the CPU2; the emitter of the power amplifier Q1 is grounded, and the collector of the power amplifier Q1 is connected to the 3rd terminal of the transformer T3; the base of the power amplifier Q2 is connected to the output terminal of the resistor R286 and is connected to the input terminal of the resistor R287. The output terminal of the resistor R287 is grounded. The input terminal of the resistor R286 is connected to the output terminal of the capacitor C3, and the input terminal of the capacitor C3 is connected to the input of the DRV_TTL_TX- terminal of the CPU2; the emitter of the power amplifier Q2 is grounded, and the collector of the power amplifier Q2 is connected to the 6th terminal of the transformer T3. The 4th terminal of the transformer T3 is connected to the output terminal of the resistor R284, the input terminal of the resistor R284 is connected to the +5V power supply input. The 1st terminal of the transformer T3 is connected to the input terminal of the capacitor C2, the output terminal of the capacitor C2 is connected to the 4th terminal of the connecting wire rubber head J6. The 2nd terminal of the transformer T3 is connected to the input terminal of the capacitor C4 and is connected to the input terminal of the resistor R283. The output terminal of the resistor R283 is grounded. The output terminal of the capacitor C4 is connected to the 3rd terminal of the connecting wire rubber head J6; the 3rd terminal of the transformer T2 is connected to the output terminal of the capacitor C67, the input terminal of the capacitor C67 is connected to the 2nd terminal of the connecting wire rubber head J6. The 4th terminal of the transformer T2 is connected to the output terminal of the capacitor C68 and is connected to the input terminal of the resistor R264. The output terminal of the resistor R264 is grounded. The input terminal of the capacitor C68 is connected to the 1st terminal of the connecting wire rubber head J6. The 1st terminal of the transformer T2 is grounded. The 2nd terminal of the transformer T2 is connected to the input terminal of the resistor R263.
[0008] Preferably, the variable modulation signal receiving circuit includes an amplification circuit and a comparison circuit. The amplification circuit includes amplifiers U14.1, U14.2, and U13.1. The negative terminal of amplifier U14.1 is sequentially connected in series with resistor R278 and capacitor C76 and then connected to the output terminal of capacitor C76. The output terminal of resistor R278 is connected to the input terminal of resistor R277 and the input terminal of capacitor C73. The output terminal of resistor R277 is connected to the output terminal of capacitor C73 and then connected to the output terminal of amplifier U14.1. The positive terminal of amplifier U14.1 is connected to the output terminal of resistor R279. Resistor R279 is connected to the input of VREF1 terminal. The 8th terminal of amplifier U14.1 is connected to the input of +VCC_A. The output terminal of amplifier U14.1 is sequentially connected in series with capacitor C75 and resistor R280 and then connected to the input terminal of amplifier U14.2. The output terminal of resistor R280 is connected to the input terminal of resistor R281 and the input terminal of capacitor C74. The output terminal of resistor R281 is connected to the output terminal of capacitor C74 and then connected to the output terminal of amplifier U14.2. The positive terminal of amplifier U14.2 is connected to the output terminal of resistor R282. Resistor R282 is connected to the input of VREF1 terminal. The output terminal of amplifier U14.2 is sequentially connected in series with resistor R276, capacitor C71, diode D13, and resistor R270 and then connected to the positive terminal of amplifier U13.1. The output terminal of resistor R270 is connected with capacitor C70 and resistor R269. The output terminals of capacitor C70 and resistor R269 are connected together and then grounded. The negative terminal of amplifier U13.1 is connected to the input terminal of resistor R268 and connected to the input terminal of resistor R267. The output terminal of resistor R268 is grounded. The output terminal of resistor R267 is connected to the output terminal of amplifier U13.1. The 8th terminal of amplifier U13.1 is connected to the input of +VCC_A. The 4th terminal of amplifier U13.1 is grounded. The comparison circuit includes comparator U12.1, resistors R265, R273, R273, R274, and R274. The input terminal of comparator U12.1 is connected in series with resistor R265 and then connected to the output terminal of amplifier U13.1. The positive terminal of comparator U12.1 is connected to the output terminal of resistor R273 and connected to the input terminal of resistor R266. The input terminal of resistor R273 is connected to the input of +VCC_A. The output terminal of resistor R266 is connected to the 4th terminal of comparator U12.1 and then grounded. The 8th terminal of comparator U12.1 is connected to the input of +VCC_A. The input-output terminal of +VCC_A is connected to the input terminal of resistor R274. The output terminal of resistor R274 is connected to the output terminal of resistor R275 and connected to the USART_RX terminal of CPU2.
[0009] Preferably, the number of capacitors connected in series between the variable transformer T1 and the transformer T2 is not limited to the high-voltage isolation capacitors C1, C2, C3, and C4.
[0010] Preferably, the diameters φ of the variable high-voltage isolation capacitor C1, high-voltage isolation capacitor C2, high-voltage isolation capacitor C3, and high-voltage isolation capacitor C4 can be any value.
[0011] Preferably, the magnetic ring diameters of the transformers T1 and T2 can be any value.
[0012] Preferably, the model of the CPU2 is STM32F407IGT6.
[0013] Compared with the prior art, the beneficial effects of the present utility model are as follows:
[0014] The high-voltage isolation serial interface circuit of the present invention has a maximum withstand voltage of up to 22 KV, and the circuit is relatively simple. Its maximum withstand voltage can meet the high-voltage isolation application of 15 KV; and the withstand voltage can be further improved in the following ways: 1. By increasing the magnetic ring diameters of the transformers T1 and T2 to increase the insulation distance. Therefore, the magnetic ring diameters of the transformers T1 and T2 can be any value, and their magnetic ring diameters can be set according to requirements; 2. Increasing the diameter φ of the high-voltage isolation capacitor to improve the withstand voltage, and more high-voltage isolation capacitors can be connected in series between the transformers T1 and T2; in addition, to enable the transformers T1 and T2 to have higher withstand voltage, the transformers T1 and T2 no longer adopt the stacked winding method, and the receiving and transmitting windings are respectively wound at one end of the transformer, increasing the insulation distance, which can meet the high-voltage isolation requirements; by adjusting the maximum withstand voltage value using the above scheme, it can meet the high-voltage isolation applications in a large range, and has strong practical flexibility. Description of the Drawings
[0015] Figure 1 It is the topology diagram of the high-voltage isolation interface loop of the present utility model;
[0016] Figure 2 It is the circuit diagram for transmitting the modulation signal of the present utility model;
[0017] Figure 3 It is the wiring diagram of the CPU2 of the present utility model;
[0018] Figure 4 It is the circuit diagram for receiving the modulation signal of the present utility model;
[0019] Figure 5 It is the schematic diagram of the modulation conversion of the transmitted signal of the present utility model;
[0020] Figure 6 It is the schematic diagram of the winding of the high-voltage isolation transformer of the present utility model. Detailed Embodiments
[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0022] Please refer to Figures 1-6 , a high-voltage-resistant isolation serial interface circuit, including a modulation signal sending circuit, a modulation signal receiving circuit, CPU1 and CPU2. The model of CPU2 is STM32F407IGT6. The input end of the modulation signal sending circuit is connected to the input end of CPU1, the output end of the modulation signal sending circuit is connected to the input end of the modulation signal receiving circuit, the output end of the modulation signal receiving circuit is connected to the signal input end of the modulation signal receiving circuit, and the output end of the modulation signal receiving circuit is connected to the signal end of CPU2; the modulation signal sending circuit includes a transformer T1, a transformer T2, high-voltage isolation capacitors C1, C2, C3 and C4. The 1st terminal of the transformer T1 is connected to the I / 01 terminal of the CPU for input, the 2nd terminal of the transformer T1 is connected to the I / 02 terminal of the CPU for input, the 3rd terminal of the transformer T1 is connected to the input end of the capacitor C1, the output end of the capacitor C1 is connected to the input end of the capacitor C2, and the output end of the capacitor C2 is connected to the 1st terminal of the transformer T2; the 4th terminal of the transformer T1 is connected to the input end of the capacitor C3, the output end of the capacitor C3 is connected to the input end of the capacitor C4, and the capacitor C4 is connected to the 2nd terminal of the transformer T2; the modulation signal receiving circuit includes an amplification and detection circuit and a comparison circuit. The 3rd terminal of the transformer T2 is connected to the 1st terminal of the amplification and detection circuit U1, the 4th terminal of the transformer T2 is connected to the 2nd terminal of the amplification and detection circuit, the output end of the amplification and detection circuit is connected to the input end of the comparison circuit, and the output end of the comparison circuit is connected to the USART_RX terminal of CPU2.
[0023] Devices such as the above-mentioned transformer T1, transformer T2, high-voltage isolation capacitor C1, high-voltage isolation capacitor C2, high-voltage isolation capacitor C3, and high-voltage isolation capacitor C4 are serially isolated. Among them, the isolation voltage of transformer T1 and transformer T2 is greater than 8 kV, and the high-voltage isolation capacitors C1, C2, C3, and C4 use high-voltage isolation capacitors with a withstand voltage of 3 kV. According to this standard, the maximum withstand voltage of the circuit reaches 22 kV. If further improvement of the withstand voltage is required, it can be achieved through the following methods: 1. By increasing the magnetic ring diameter of transformer T1 and transformer T2 to increase the insulation distance. Therefore, the magnetic ring diameter of transformer T1 and transformer T2 can be any value, and its magnetic ring diameter can be set according to requirements; 2. Increase the diameter φ of the high-voltage isolation capacitor. For example, the diameter φ of a 3 kV isolation capacitor is 10 mm, and the diameter φ of a 6 kV isolation capacitor is 20 mm. Here, the high-voltage isolation capacitor is not limited to using high-voltage isolation capacitors C1, C2, C3, and C4. More high-voltage isolation capacitors can be connected in series between transformer T1 and transformer T2; in addition, to enable transformer T1 and transformer T2 to have a higher withstand voltage, the method of using laminated winding for transformer T1 and transformer T2 is cancelled, and the transceiver windings are each wound at one end of the transformer, increasing the insulation distance, which can meet the requirements of high-voltage isolation. The winding method of the high-voltage isolation transformer is as follows Figure 6 As shown
[0024] Among them: The modulation signal transmitting circuit further includes a power amplifier Q1, a power amplifier Q2, and a connecting wire rubber head J6. The base of the power amplifier Q1 is connected to the output terminal of the resistor R285 and is also connected to the input terminal of the resistor R288. The output terminal of the resistor R288 is grounded. The input terminal of the resistor R285 is connected to the output terminal of the capacitor C1, and the input terminal of the capacitor C1 is connected to the input of the DRV_TTL_TX+ terminal of the CPU2; the emitter of the power amplifier Q1 is grounded, and the collector of the power amplifier Q1 is connected to the 3rd terminal of the transformer T3; the base of the power amplifier Q2 is connected to the output terminal of the resistor R286 and is also connected to the input terminal of the resistor R287. The output terminal of the resistor R287 is grounded. The input terminal of the resistor R286 is connected to the output terminal of the capacitor C3, and the input terminal of the capacitor C3 is connected to the input of the DRV_TTL_TX- terminal of the CPU2; the emitter of the power amplifier Q2 is grounded, and the collector of the power amplifier Q2 is connected to the 6th terminal of the transformer T3. The 4th terminal of the transformer T3 is connected to the output terminal of the resistor R284, the input terminal of the resistor R284 is connected to the +5V power supply input, the 1st terminal of the transformer T3 is connected to the input terminal of the capacitor C2, the output terminal of the capacitor C2 is connected to the 4th terminal of the connecting wire rubber head J6, the 2nd terminal of the transformer T3 is connected to the input terminal of the capacitor C4 and is also connected to the input terminal of the resistor R283. The output terminal of the resistor R283 is grounded, and the output terminal of the capacitor C4 is connected to the 3rd terminal of the connecting wire rubber head J6; the 3rd terminal of the transformer T2 is connected to the output terminal of the capacitor C67, the input terminal of the capacitor C67 is connected to the 2nd terminal of the connecting wire rubber head J6, the 4th terminal of the transformer T2 is connected to the output terminal of the capacitor C68 and is also connected to the input terminal of the resistor R264. The output terminal of the resistor R264 is grounded, the input terminal of the capacitor C68 is connected to the 1st terminal of the connecting wire rubber head J6, the 1st terminal of the transformer T2 is grounded, and the 2nd terminal of the transformer T2 is connected to the input terminal of the resistor R263.
[0025] Among them: The modulation signal receiving circuit includes an amplifying circuit and a comparing circuit. The amplifying circuit includes amplifiers U14.1, U14.2, and U13.1. The negative pole of amplifier U14.1 is sequentially connected in series with resistor R278 and capacitor C76 and then connected to the output terminal of capacitor C76. The output terminal of resistor R278 is connected to the input terminal of resistor R277 and the input terminal of capacitor C73. The output terminal of resistor R277 is connected to the output terminal of capacitor C73 and then connected to the output terminal of amplifier U14.1. The positive pole of amplifier U14.1 is connected to the output terminal of resistor R279. Resistor R279 is connected to the input of VREF1 terminal. The 8th terminal of amplifier U14.1 is connected to +VCC_A input. The output terminal of amplifier U14.1 is sequentially connected in series with capacitor C75 and resistor R280 and then connected to the input terminal of amplifier U14.2. The output terminal of resistor R280 is connected to the input terminal of resistor R281 and the input terminal of capacitor C74. The output terminal of resistor R281 is connected to the output terminal of capacitor C74 and then connected to the output terminal of amplifier U14.2. The positive pole of amplifier U14.2 is connected to the output terminal of resistor R282. Resistor R282 is connected to the input of VREF1 terminal. The output terminal of amplifier U14.2 is sequentially connected in series with resistor R276, capacitor C71, diode D13, and resistor R270 and then connected to the positive pole of amplifier U13.1. The output terminal of resistor R270 is connected with capacitor C70 and resistor R269. The output terminals of capacitor C70 and resistor R269 are connected and then grounded. The negative pole of amplifier U13.1 is connected to the input terminal of resistor R268 and connected to the input terminal of resistor R267. The output terminal of resistor R268 is grounded. The output terminal of resistor R267 is connected to the output terminal of amplifier U13.1. The 8th terminal of amplifier U13.1 is connected to +VCC_A input. The 4th terminal of amplifier U13.1 is grounded. The comparing circuit includes comparator U12.1, resistors R265, R273, R273, R274, and R274. The input terminal of comparator U12.1 is connected in series with resistor R265 and then connected to the output terminal of amplifier U13.1. The positive pole of comparator U12.1 is connected to the output terminal of resistor R273 and connected to the input terminal of resistor R266. The input terminal of resistor R273 is connected to +VCC_A input. The output terminal of resistor R266 is connected to the 4th terminal of comparator U12.1 and then grounded. The 8th terminal of comparator U12.1 is connected to +VCC_A input. The +VCC_A input and output terminal is connected to the input terminal of resistor R274. The output terminal of resistor R274 is connected to the output terminal of resistor R275 and connected to the USART_RX terminal of CPU2.
[0026] The above serial signal is converted into an amplitude-modulated signal of 150KHz at the sending end. This signal can be directly sent differentially through two I / O pins of CPU2 by programming CPU2, without the need to specially design a waveform modulation conversion circuit. The waveform conversion is as follows Figure 5As shown, a high-frequency wave emission represents logic low, and no waveform emission represents logic high. As long as programming is used to make the frequency of the high-frequency wave differentially emitted by the I / O pin reach 10 times or more of the serial port baud rate and data is sent according to the serial port protocol. The specific transmitting end circuit is as follows Figure 2 As shown; a modulation signal receiving circuit is set for this modulation signal, such as Figure 4 As shown, the modulation signal receiving circuit receives the signal from the secondary of the transformer T2, amplifies the signal through the two-stage amplification circuit composed of the amplifier U14.1 and the amplifier U14.2, uses the diode D13 to detect the half-wave of the signal, extracts the envelope of the signal through low-pass filtering, and finally sends the extracted envelope into the comparator U12.1 after being amplified by the amplification circuit composed of the amplifier U13.1 for comparison with the threshold level for output, restoring the modulation waveform to the original serial port waveform, and this waveform can be directly received by the serial interface of the CPU2.
[0027] In this high-voltage isolation serial interface circuit, devices such as the transformer T1, the transformer T2, the high-voltage isolation capacitor C1, the high-voltage isolation capacitor C2, the high-voltage isolation capacitor C3, and the high-voltage isolation capacitor C4 are serially isolated. Among them, the isolation voltage of the transformer T1 and the transformer T2 is greater than 8KV, and the high-voltage isolation capacitors C1, C2, C3, and C4 use high-voltage isolation capacitors with a withstand voltage of 3KV. According to this standard, the maximum withstand voltage of the circuit reaches 22KV. This circuit is relatively simple, and its maximum withstand voltage can meet the high-voltage isolation application of 15KV; and the withstand voltage can be further improved in the following ways: 1. By increasing the magnetic ring diameter of the transformer T1 and the transformer T2 to increase the insulation distance. Therefore, the magnetic ring diameter of the transformer T1 and the transformer T2 can be any value, and its magnetic ring diameter can be set according to requirements; 2. Increase the diameter φ of the high-voltage isolation capacitor. For example, the φ of the 3kV isolation capacitor is 10mm, and the φ of the 6kV isolation capacitor is 20mm. Here, the high-voltage isolation capacitor is not limited to using the high-voltage isolation capacitors C1, C2, C3, and C4. More high-voltage isolation capacitors can be serially connected between the transformer T1 and the transformer T2; in addition, to make the transformer T1 and the transformer T2 have a higher withstand voltage, the transformer T1 and the transformer T2 cancel the method of using laminated winding. The receiving and transmitting windings are each wound at one end of the transformer, increasing the insulation distance, which can meet the high-voltage isolation requirements. The winding method of the high-voltage isolation transformer is as follows Figure 6 As shown, by adopting the above scheme to adjust the maximum withstand voltage value, it can meet the high-voltage isolation application in a large range, and has strong practical flexibility.
[0028] The above are only the preferred specific embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model, according to the technical solution of the present utility model and its inventive concept, makes equivalent substitutions or changes, and should be covered within the protection scope of the present utility model.
Claims
1. A high voltage resistant isolated serial interface circuit, comprising a modulation signal transmitting circuit, a modulation signal receiving circuit, a CPU1 and a CPU2, characterized in that: The input end of the modulation signal sending circuit is connected to the input end of CPU1, the output end of the modulation signal sending circuit is connected to the input end of the modulation signal receiving circuit, the output end of the modulation signal receiving circuit is connected to the signal input end of the modulation signal receiving circuit, and the output end of the modulation signal receiving circuit is connected to the signal end of CPU2; the modulation signal sending circuit includes a transformer T1, a transformer T2, a high-voltage isolation capacitor C1, a high-voltage isolation capacitor C2, a high-voltage isolation capacitor C3 and a high-voltage isolation capacitor C4, terminal 1 of the transformer T1 is connected to the I / 01 terminal input of the CPU, terminal 2 of the transformer T1 is connected to the I / 02 terminal input of the CPU, and terminal 3 of the transformer T1 is connected to capacitor C1 The input end of the capacitor C1 is connected to the input end of the capacitor C2, and the output end of the capacitor C2 is connected to the terminal 1 of the transformer T2; the terminal 4 of the transformer T1 is connected to the input end of the capacitor C3, the output end of the capacitor C3 is connected to the input end of the capacitor C4, and the capacitor C4 is connected to the terminal 2 of the transformer T2; the modulated signal receiving circuit includes an amplifying and detecting circuit and a comparing circuit, the terminal 3 of the transformer T2 is connected to the terminal 1 of the amplifying and detecting circuit U1, the terminal 4 of the transformer T2 is connected to the terminal 2 of the amplifying and detecting circuit, the output end of the amplifying and detecting circuit is connected to the input end of the comparing circuit, and the output end of the comparing circuit is connected to the USART_RX terminal of CPU2.
2. A high voltage isolation serial interface circuit as claimed in claim 1, characterized in that: The modulation signal sending circuit also includes a power amplifier Q1, a power amplifier Q2 and a connecting wire rubber head J6, the base of the power amplifier Q1 is connected to the output end of the resistor R285, and is connected to the input end of the resistor R288, the output end of the resistor R288 is grounded, the input end of the resistor R285 is connected to the output end of the capacitor C1, and the input end of the capacitor C1 is connected to the DRV_TTL_TX+ terminal input of the CPU2; the emitter of the power amplifier Q1 is grounded, and the collector of the power amplifier Q1 is connected to the No. 3 terminal of the transformer T3; the base of the power amplifier Q2 is connected to the output end of the resistor R286, and is connected to the input end of the resistor R287, the output end of the resistor R287 is grounded, the input end of the resistor R286 is connected to the output end of the capacitor C3, and the input end of the capacitor C3 is connected to the DRV_TTL_TX- terminal input of the CPU2; the emitter of the power amplifier Q2 is grounded, and the collector of the power amplifier Q2 is connected to Terminal 6 of transformer T3 and terminal 4 of transformer T3 are connected to the output end of resistor R284, the input end of resistor R284 is connected to the +5V power input, terminal 1 of transformer T3 is connected to the input end of capacitor C2, the output end of capacitor C2 is connected to terminal 4 of connecting wire rubber head J6, terminal 2 of transformer T3 is connected to the input end of capacitor C4 and connected to the input end of resistor R283, the output end of resistor R283 is grounded, and the output end of capacitor C4 is connected to terminal 3 of connecting wire rubber head J6; terminal 3 of transformer T2 is connected to the output end of capacitor C67, the input end of capacitor C67 is connected to terminal 2 of connecting wire rubber head J6, terminal 4 of transformer T2 is connected to the output end of capacitor C68 and connected to the input end of resistor R264, the output end of resistor R264 is grounded, the input end of capacitor C68 is connected to terminal 1 of connecting wire rubber head J6, terminal 1 of transformer T2 is grounded, and terminal 2 of transformer T2 is connected to the input end of resistor R263.
3. A high voltage isolation serial interface circuit as claimed in claim 1, characterized in that: The modulation signal receiving circuit includes an amplifier circuit and a comparison circuit. The amplifier circuit includes an amplifier U14.1, an amplifier U14.2, and an amplifier U13.
1. The negative electrode of the amplifier U14.1 is connected in series with a resistor R278 and a capacitor C76 in sequence and then connected to the output end of the capacitor C76. The output end of the resistor R278 is connected to the input end of the resistor R277 and to the input end of the capacitor C73. The output end of the resistor R277 is connected to the output end of the capacitor C73 and then connected to the output end of the amplifier U14.
1. The positive electrode of the amplifier U14.1 is connected to the output end of the resistor R279, and the resistor R279 is connected to the VREF1 terminal input. Terminal 8 is connected to +VCC_A input, the output end of amplifier U14.1 is connected in series with capacitor C75 and resistor R280 in sequence, and then connected to the input end of amplifier U14.2, the output end of resistor R280 is connected to the input end of resistor R281 and the input end of capacitor C74, the output end of resistor R281 is connected to the output end of capacitor C74 and then connected to the output end of amplifier U14.2, the positive electrode of amplifier U14.2 is connected to the output end of resistor R282, resistor R282 is connected to VREF1 terminal input, the output end of amplifier U14.2 is connected in series with resistor R276, capacitor C71, diode D13 and resistor R270 in sequence, and then connected to amplifier The positive electrode of the amplifier U13.1, the output end of the resistor R270 is connected to the capacitor C70 and the resistor R269, the output ends of the capacitor C70 and the resistor R269 are connected and then grounded; the negative electrode of the amplifier U13.1 is connected to the input end of the resistor R268 and the input end of the resistor R267, the output end of the resistor R268 is grounded, the output end of the resistor R267 is connected to the output end of the amplifier U13.1, the terminal 8 of the amplifier U13.1 is connected to the +VCC_A input, and the terminal 4 of the amplifier U13.1 is grounded; the comparison circuit includes a comparator U12.1, a resistor R265, a resistor R273, a resistor R274, and Resistor R274, the input end of comparator U12.1 is connected in series with resistor R265 and then connected to the output end of amplifier U13.1, the positive pole of comparator U12.1 is connected to the output end of resistor R273 and connected to the input end of resistor R266, the input end of resistor R273 is connected to +VCC_A input, the output end of resistor R266 is connected to terminal 4 of comparator U12.1 and then grounded, terminal 8 of comparator U12.1 is connected to +VCC_A input, the +VCC_A input and output ends are connected to the input end of resistor R274, the output end of resistor R274 is connected to the output end of resistor R275, and is connected to the USART_RX terminal of CPU2.
4. The high voltage isolation serial interface circuit according to claim 1, characterized in that: The number of capacitors connected in series between the transformer T1 and the transformer T2 is not limited to the high-voltage isolation capacitor C1 , the high-voltage isolation capacitor C2 , the high-voltage isolation capacitor C3 and the high-voltage isolation capacitor C4 .
5. The high voltage isolation serial interface circuit according to claim 1, characterized in that: The diameters φ of the high-voltage isolation capacitors C1 , C2 , C3 and C4 are arbitrary values.
6. A high voltage isolation serial interface circuit as claimed in claim 1, characterized in that: The diameters of the magnetic rings of the transformers T1 and T2 can be any values.
7. The high voltage isolation serial interface circuit according to claim 1, characterized in that: The model of the CPU2 is STM32F407IGT6.