Memory sharing circuit and electronic device

Abstract

The utility model provides a memory sharing circuit and electronic equipment, and relates to the technical field of electronic circuits. A memory circuit in the memory sharing circuit is connected with a single-chip microcomputer through a work indication circuit and a data transmission circuit. The input end of the work indication circuit is connected with the work indication end of the main single-chip microcomputer, the output end of the work indication circuit is connected with the storage circuit, and the work indication circuit is used for triggering a single-chip microcomputer indication signal corresponding to the output work indication signal when receiving the work indication signal output by the work indication end; the input end of the data transmission circuit is connected with the data transmission ends of the at least two single-chip microcomputers and the work indication end of the main single-chip microcomputer, and the output end of the data transmission circuit is connected with the storage circuit, so that a data transmission path is formed between the storage circuit and the single-chip microcomputer corresponding to the work indication signal. According to the embodiment of the invention, a plurality of single-chip microcomputers can share one storage circuit for data storage and reading, so that the cost of the single-chip microcomputers is effectively reduced.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits. Specifically, this application relates to a memory sharing circuit and an electronic device. Background Art

[0002] In the prior art, in order to achieve the intelligent operation of devices and meet the performance requirements of devices, many devices use multiple single-chip microcomputers as the core control modules.

[0003] However, when setting multiple single-chip microcomputers, a large amount of data is also generated due to the communication between the single-chip microcomputers and the operations they perform respectively. Moreover, the storage space of each single-chip microcomputer is limited and it is difficult to store this data. To ensure the normal operation of the device, it is necessary to purchase single-chip microcomputers with large storage space or set up a memory for each single-chip microcomputer separately. Both of these methods will increase the production cost of the device. Summary of the Utility Model

[0004] Embodiments of this application provide a memory sharing circuit and an electronic device, which can solve the problem of using single-chip microcomputers with large storage space or setting up a memory for each single-chip microcomputer separately, thereby increasing the production cost of the device. To achieve this purpose, the embodiments of this application provide the following several solutions.

[0005] According to one aspect of the embodiments of this application, there is provided a memory sharing circuit, including: a working indication circuit and a data transmission circuit. At least one storage circuit is connected to at least two single-chip microcomputers through the working indication circuit and the data transmission circuit. The storage circuit is provided with a memory, and the at least two single-chip microcomputers include a main single-chip microcomputer;

[0006] The input end of the working indication circuit is connected to the working indication end of the main single-chip microcomputer, and the output end is connected to the storage circuit. The working indication circuit is configured to trigger and output a single-chip microcomputer indication signal corresponding to the working indication signal when receiving the working indication signal output from the working indication end. The single-chip microcomputer indication signal is used to indicate the single-chip microcomputer that is currently transmitting data;

[0007] The input end of the data transmission circuit is connected to the data transmission ends of the at least two single-chip microcomputers and the working indication end of the main single-chip microcomputer, and the output end is connected to the storage circuit. The data transmission circuit is configured to form a data transmission path between the storage circuit and the single-chip microcomputer corresponding to the working indication signal.

[0008] In a possible implementation, the at least two single-chip microcontrollers further include a slave single-chip microcontroller. The working indication circuit includes a first logic chip circuit. The input end of the first logic chip circuit is connected to the working indication end, the clock signal end of the master single-chip microcontroller, and the clock signal end of the slave single-chip microcontroller. The output end of the first logic chip circuit is connected to the storage circuit.

[0009] In a possible implementation, the first logic chip circuit includes a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate, and a fourth two-input NAND gate. The working indication end of the master single-chip microcontroller is connected to the second input end of the first two-input NAND gate and the input end of the third two-input NAND gate. The first input end of the first two-input NAND gate is connected to the clock signal end of the master single-chip microcontroller. The output end of the first two-input NAND gate is connected to the first input end of the second two-input NAND gate. The output end of the third two-input NAND gate is connected to the first input end of the fourth two-input NAND gate. The second input end of the fourth two-input NAND gate is connected to the clock signal end of the slave single-chip microcontroller. The output end of the fourth two-input NAND gate is connected to the second input end of the second two-input NAND gate. The output end of the second two-input NAND gate is connected to the storage circuit.

[0010] In a possible implementation, the working indication end includes a first indication end. The input end of the first logic chip circuit is connected to the first indication end. The data transmission circuit includes a second logic chip circuit. The input end of the second logic chip circuit is connected to the first indication end, the data output end of the master single-chip microcontroller, and the data output end of the slave single-chip microcontroller.

[0011] In a possible implementation, the second logic chip circuit includes a fifth two-input NAND gate, a sixth two-input NAND gate, a seventh two-input NAND gate, and an eighth two-input NAND gate. The first indication end is connected to the second input end of the fifth two-input NAND gate and the input end of the seventh two-input NAND gate. The output end of the seventh two-input NAND gate is connected to the first input end of the eighth two-input NAND gate. The second input end of the eighth two-input NAND gate is connected to the data output end of the slave single-chip microcontroller. The output end of the eighth two-input NAND gate is connected to the second input end of the sixth two-input NAND gate. The first input end of the fifth two-input NAND gate is connected to the data output end of the master single-chip microcontroller. The output end of the fifth two-input NAND gate is connected to the first input end of the sixth two-input NAND gate. The output end of the sixth two-input NAND gate is connected to the storage circuit.

[0012] In a possible implementation, the working indication circuit includes a second indication terminal and a third indication terminal, and the data transmission circuit further includes a third logic chip circuit. The input end of the third logic chip circuit is connected to the data output end of the storage circuit, the second indication terminal, and the third indication terminal, and the output end of the third logic chip circuit is connected to the data receiving end of the main single-chip microcomputer and the data receiving end of the slave single-chip microcomputer.

[0013] In a possible implementation, the third logic circuit includes a ninth dual-input NAND gate, a tenth dual-input NAND gate, an eleventh dual-input NAND gate, and a one-hundred-and-forty-fifth resistor. The first input end of the ninth dual-input NAND gate is connected to the second indication terminal. The input ends of the tenth dual-input NAND gate are connected to the data output end of the storage circuit and the first end of the one-hundred-and-forty-fifth resistor. The second end of the one-hundred-and-forty-fifth resistor is grounded. The output end of the tenth dual-input NAND gate is connected to the second input end of the ninth dual-input NAND gate and the first input end of the eleventh dual-input NAND gate. The second input end of the eleventh dual-input NAND gate is connected to the third indication terminal. The output end of the eleventh dual-input NAND gate is connected to the data receiving end of the main single-chip microcomputer. The output end of the ninth dual-input NAND gate is connected to the data receiving end of the slave single-chip microcomputer.

[0014] In a possible implementation, it further includes at least one storage indication circuit, and the storage indication circuits are in one-to-one correspondence with the storage circuits;

[0015] The input end of the storage indication circuit is connected to the single-chip microcomputer, and the output end is connected to the corresponding storage circuit. The storage indication circuit is used to output a signal indicating whether the connected storage circuit is selected.

[0016] In a possible implementation, the input end of the storage indication circuit is connected to the working indication terminal, chip select signal terminal of the main single-chip microcomputer, and the chip select signal terminal of the slave single-chip microcomputer, and the output end is connected to the memory.

[0017] According to one aspect of the embodiments of the present application, there is provided an electronic device, which includes at least two single-chip microcomputers, at least one storage circuit, and the memory sharing circuit as described above. The memory sharing circuit is electrically connected to the single-chip microcomputer and the storage circuit respectively.

[0018] The beneficial effects brought by the technical solution provided by the embodiments of the present application are:

[0019] In the memory sharing circuit provided by this application, at least one memory circuit is connected to at least two single-chip microcomputers through a working indication circuit and a data transmission circuit; the input end of the working indication circuit is connected to the working indication end of the main single-chip microcomputer, and the output end is connected to the memory circuit. The working indication circuit is used to receive the working indication signal output by the working indication end and trigger the single-chip microcomputer indication signal corresponding to the output working indication signal. The single-chip microcomputer indication signal is used to indicate the single-chip microcomputer that is currently transmitting data; the input end of the data transmission circuit is connected to the data transmission ends of at least two single-chip microcomputers and the working indication end of the main single-chip microcomputer, and the output end is connected to the memory circuit. The data transmission circuit is used to form a data transmission path between the memory circuit and the single-chip microcomputer corresponding to the working indication signal. The embodiments of this application can enable multiple single-chip microcomputers to share a memory circuit for data storage and reading, thereby avoiding the problems of the storage space of the single-chip microcomputer and the need to set multiple memories, and effectively reducing the production cost of the device. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following briefly introduces the drawings required for description in the embodiments of this application.

[0021] Figure 1 It is the structural diagram of the memory sharing circuit provided by the embodiment of this application;

[0022] Figure 2 It is the circuit diagram of the first logic chip circuit provided by this application;

[0023] Figure 3 It is the circuit diagram of the second logic chip circuit provided by the embodiment of this application;

[0024] Figure 4 It is the circuit diagram of the third logic chip circuit provided by the embodiment of this application;

[0025] Figure 5 It is the circuit diagram of the storage indication circuit provided by the embodiment of this application;

[0026] Figure 6 It is the circuit diagram of the memory circuit provided by the embodiment of this application;

[0027] Figure 7 It is the circuit diagram of the main single-chip microcomputer provided by the embodiment of this application;

[0028] Figure 8 It is the circuit diagram of the slave single-chip microcomputer provided by the embodiment of this application;

[0029] Figure 9 It is the circuit diagram of the electronic device provided by the embodiment of this application.

[0030] Description of reference numerals: U2, main single-chip microcomputer; U1, slave single-chip microcomputer; U21, memory; U22A, first dual-input NAND gate; U22B, second dual-input NAND gate; U22C, third dual-input NAND gate; U22D, fourth dual-input NAND gate; U30A, fifth dual-input NAND gate; U30B, sixth dual-input NAND gate; U30C, seventh dual-input NAND gate; U30D, eighth dual-input NAND gate; U31A, ninth dual-input NAND gate; U31B, tenth dual-input NAND gate; U31C, eleventh dual-input NAND gate; R145, one hundred and forty-fifth resistor; U27A, twelfth dual-input NAND gate; U27B, thirteenth dual-input NAND gate; U27C, fourteenth dual-input NAND gate; U27D, fifteenth dual-input NAND gate. Detailed implementation manners

[0031] The embodiments of the present application will be described below in conjunction with the accompanying drawings in the present application. It should be understood that the implementation manners described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0032] Those skilled in the art of the present technology can understand that unless specifically stated otherwise, the singular forms "a", "an", "the", and "said" used herein may also include the plural forms. It should be further understood that the terms "comprising" and "including" used in the embodiments of the present application mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements, and / or components, but do not exclude being implemented as other features, information, data, steps, operations, elements, components, and / or their combinations supported by the art of the present technology. It should be understood that when we say that an element is "connected" or "coupled" to another element, this element can be directly connected or coupled to the other element, or it can mean that this element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include a wireless connection or a wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" indicates being implemented as "A", or being implemented as "A", or being implemented as "A and B".

[0033] To make the objectives, technical solutions, and advantages of the present utility model clearer, the implementation manners of the present utility model will be further described in detail below in conjunction with the accompanying drawings.

[0034] The technical solutions of the embodiments of the present utility model and the technical effects produced by the technical solutions of the present utility model will be described below through the description of several exemplary implementation manners. It should be noted that the following implementation manners can be referred to, learned from, or combined with each other. For the same terms, similar features, and similar implementation steps in different implementation manners, they will not be described repeatedly.

[0035] The memory sharing circuit and electronic device provided by this application aim to solve at least one technical problem existing in the prior art.

[0036] In an embodiment of this application, a memory sharing circuit is provided, as Figures 1-8 shown. The memory sharing circuit includes: a working indication circuit, a data transmission circuit. At least one storage circuit is connected to at least two single-chip microcomputers through the working indication circuit and the data transmission circuit. The storage circuit is provided with a memory U21. The at least two single-chip microcomputers include a main single-chip microcomputer U2. The input end of the working indication circuit is connected to the working indication end of the main single-chip microcomputer U2, and the output end is connected to the storage circuit. The working indication circuit is used for triggering and outputting a single-chip microcomputer indication signal corresponding to the working indication signal when receiving the working indication signal output from the working indication end. The single-chip microcomputer indication signal is used to indicate the single-chip microcomputer currently transmitting data. The input end of the data transmission circuit is connected to the data transmission ends of at least two single-chip microcomputers and the working indication end of the main single-chip microcomputer U2, and the output end is connected to the storage circuit. The data transmission circuit is used for forming a data transmission path between the storage circuit and the single-chip microcomputer corresponding to the working indication signal.

[0037] In one embodiment, the number of single-chip microcomputers is two, and the two single-chip microcomputers are connected to the same storage circuit.

[0038] Optionally, one or more memories U21 are provided in the storage circuit, and the single-chip microcomputer connected to the storage circuit stores or reads data through the memory U21 in the storage circuit.

[0039] Optionally, the at least two single-chip microcomputers further include a slave single-chip microcomputer U1. The working indication circuit includes a first logic chip circuit. The input end of the first logic chip circuit is connected to the working indication end, clock signal end of the main single-chip microcomputer U2 and the clock signal end of the slave single-chip microcomputer U1. The output end of the first logic chip circuit is connected to the storage circuit. Information indicating the single-chip microcomputer that currently needs to perform data transmission is output through the first logic chip circuit.

[0040] Optionally, as Figures 6-8 shown, the models of the main single-chip microcomputer U2 and the slave single-chip microcomputer U1 can both be STM32F103C8T6, and the model of the memory U21 in the storage circuit is W25Q32FVDAIQ.

[0041] In one embodiment, as Figure 2As shown in the figure, the first logic chip circuit includes the first dual-input NAND gate U22A, the second dual-input NAND gate U22B, the third dual-input NAND gate U22C, and the fourth dual-input NAND gate U22D. The working indication terminal of the main microcontroller U2 is connected to the second input terminal of the first dual-input NAND gate U22A and the input terminal of the third dual-input NAND gate U22C. The first input terminal of the first dual-input NAND gate U22A is connected to the clock signal terminal of the main microcontroller U2. The output terminal of the first dual-input NAND gate U22A is connected to the first input terminal of the second dual-input NAND gate U22B. The output terminal of the third dual-input NAND gate U22C is connected to the first input terminal of the fourth dual-input NAND gate U22D. The second input terminal of the fourth dual-input NAND gate U22D is connected to the clock signal terminal of the slave microcontroller U1. The output terminal of the fourth dual-input NAND gate U22D is connected to the second input terminal of the second dual-input NAND gate U22B. The output terminal of the second dual-input NAND gate U22B is connected to the storage circuit. The first dual-input NAND gate U22A, the second dual-input NAND gate U22B, the third dual-input NAND gate U22C, and the fourth dual-input NAND gate U22D constitute the first logic chip, and this first logic chip triggers and outputs a microcontroller indication signal based on the signals output by the main microcontroller U2 and the slave microcontroller U1.

[0042] Optionally, the working indication terminal includes a first indication terminal. The input terminal of the first logic chip circuit is connected to the first indication terminal. The data transmission circuit includes a second logic chip circuit, and the input terminal of the second logic chip circuit is connected to the first indication terminal, the data output terminal of the main microcontroller U2, and the data output terminal of the slave microcontroller U1.

[0043] In one embodiment, the first indication terminal is the GPIO port of the main microcontroller U2, and the model of the first logic chip constituted by the first dual-input NAND gate U22A, the second dual-input NAND gate U22B, the third dual-input NAND gate U22C, and the fourth dual-input NAND gate U22D is SN74HC00D. The working process of this first logic chip is as follows:

[0044] The first logic chip collects the clock signal SCLK2 and the GPIO port signal DATA_CON1 of the main microcontroller U2, and the collected signals pass through the first dual-input NAND gate U22A to obtain signal A. The signal obtained by passing the GPIO port signal DATA_CON1 through the third dual-input NAND gate U22C and the clock signal SCLK1 of the slave microcontroller U1 pass through the third dual-input NAND gate U22C to obtain signal B. Signal A and signal B pass through the second dual-input NAND gate U22B to obtain signal SCK_1, and this signal SCK_1 is input to pin 6 (clock signal pin CLK) of the memory U21.

[0045] When the clock signal SCLK2 output by the master microcontroller U2 is at high level 1, the GPIO port signal DATA_CON1 is at high level 1, and the clock signal SCLK1 output by the slave microcontroller U1 is also at high level 1, at this time, signal A is at low level 0, signal B is at high level 1, then the signal SCK_1 finally output to the memory U21 is at high level 1. When the clock signal SCLK2 output by the master microcontroller U2 is at high level 1, the GPIO port signal DATA_CON1 is at low level 0, and the signal SCLK1 output by the slave microcontroller U1 is also at high level 1, at this time, signal A is at high level 1, signal B is at low level 0, and the signal SCK_1 finally output to the memory U21 is at high level 1. When the clock signal SCLK2 output by the master microcontroller U2 is at low level 0, the GPIO port signal DATA_CON1 is at high level 1, and the clock signal SCLK1 output by the slave microcontroller U1 is also at high level 1, at this time, signal A is at high level 1, signal B is at high level 1, then the signal SCK_1 finally output to the memory U21 is at low level 0. When the clock signal SCLK2 output by the master microcontroller U2 is at high level 1, the GPIO port signal DATA_CON1 is at high level 1, and the clock signal output by the microcontroller is also at low level 0, at this time, signal A is at low level 0, signal B is at high level 1, then the signal SCK_1 finally output to the memory U21 is at high level 1.

[0046] Then it can be determined that: only when the clock signal SCLK2 output by the microcontroller and the GPIO port signal DATA_CON1 are both at high level 1, it can be judged that the master microcontroller U2 is to work.

[0047] Optionally, as Figure 3 shown, the second logic chip circuit includes the fifth two-input NAND gate U30A, the sixth two-input NAND gate U30B, the seventh two-input NAND gate U30C, and the eighth two-input NAND gate U30D. The first indication end is connected to the second input end of the fifth two-input NAND gate U30A and the input end of the seventh two-input NAND gate U30C. The output end of the seventh two-input NAND gate U30C is connected to the first input end of the eighth two-input NAND gate U30D. The second input end of the eighth two-input NAND gate U30D is connected to the data output end of the slave microcontroller U1. The output end of the eighth two-input NAND gate U30D is connected to the second input end of the sixth two-input NAND gate U30B. The first input end of the fifth two-input NAND gate U30A is connected to the data output end of the master microcontroller U2. The first input ends of the fifth two-input NAND gate U30A and the sixth two-input NAND gate U30B are connected. The output end of the sixth two-input NAND gate U30B is connected to the storage circuit.

[0048] In one embodiment, the fifth NAND gate with two inputs U30A, the sixth NAND gate with two inputs U30B, the seventh NAND gate with two inputs U30C, and the eighth NAND gate with two inputs U30D form a second logic chip, and the model of the second logic chip can be SN74HC00D. The second logic chip obtains the data output signal MOSI2 and the GPIO port signal DATA_CON1 output by the master microcontroller U2 through the data output terminal. These two signals pass through the fifth NAND gate with two inputs U30A to obtain the signal E. The GPIO port signal DATA_CON1 is input to the seventh NAND gate with two inputs U30C, and the signal output by the seventh NAND gate with two inputs U30C and the data output signal MOSI1 of the slave microcontroller U1 pass through the eighth NAND gate with two inputs U30D to obtain the signal F. The signal E and the signal F pass through the sixth NAND gate with two inputs U30B to obtain the signal MOSI_1, and the signal MOSI_1 is received by the memory U21.

[0049] From the circuit structure of the second logic chip circuit, it can be seen that when both the data output signal MOSI2 of the microcontroller and the GPIO port signal DATA_CON1 are at the high level 1, it can be determined at this time that the master microcontroller U2 is to work, transfer the data of the master microcontroller U2U2 to the storage circuit, and limit the data transfer of the slave microcontroller U1. When the data output signal MOSI1 of the slave microcontroller U1 is at the high level 1 and the signal DATA_CON1 is at the low level 0, it can be determined at this time that the slave microcontroller U1 is to work, transfer the data transmitted by the slave microcontroller U1 to the storage circuit, and correspondingly limit the data transfer of the master microcontroller U2. Through this circuit, the master microcontroller U2 and the slave microcontroller U1 store data in the storage circuit, and when one of them transfers data, the other is restricted from transferring data.

[0050] Optionally, for the convenience of reading the data stored in the memory U21 in the storage circuit, the working indication circuit includes a second indication terminal and a third indication terminal, and the data transfer circuit further includes a third logic chip circuit. The input end of the third logic chip circuit is connected to the data output end, the second indication terminal, and the third indication terminal of the storage circuit, and the output end of the third logic chip circuit is connected to the data receiving end of the master microcontroller U2 and the data receiving end of the slave microcontroller U1.

[0051] Optionally, as Figure 4As shown, the third logic circuit includes the ninth two-input NAND gate U31A, the tenth two-input NAND gate U31B, the eleventh two-input NAND gate U31C, and the one hundred and forty-fifth resistor R145. The first input terminal of the ninth two-input NAND gate U31A is connected to the second indication terminal. The input terminals of the tenth two-input NAND gate U31B are connected to the data output terminal of the storage circuit and the first terminal of the one hundred and forty-fifth resistor R145. The second terminal of the one hundred and forty-fifth resistor R145 is grounded. The output terminal of the tenth two-input NAND gate U31B is connected to the second input terminal of the ninth two-input NAND gate U31A and the first input terminal of the eleventh two-input NAND gate U31C. The second input terminal of the eleventh two-input NAND gate U31C is connected to the third indication terminal. The output terminal of the eleventh two-input NAND gate U31C is connected to the data receiving terminal of the main microcontroller U2. The output terminal of the ninth two-input NAND gate U31A is connected to the data receiving terminal of the slave microcontroller U1.

[0052] In one embodiment, the ninth two-input NAND gate U31A, the tenth two-input NAND gate U31B, and the eleventh two-input NAND gate U31C form a third logic chip, and the model of the third logic chip can be SN74HC00D. Among them, the data output signal MISO1_1 of the memory U21 is input to the tenth two-input NAND gate U31B in a double-input manner. The signals U1_A / U2_A output by the main microcontroller U2 pass through the ninth two-input NAND gate U31A and the eleventh two-input NAND gate U31C respectively. The ninth two-input NAND gate U31A and the eleventh two-input NAND gate U31C output the signals MISO1 and MISO2 respectively. The signal MISO1 is input to the SPI interface of the slave microcontroller U1. The signal MISO2 is input to the SPI interface of the main microcontroller U2. The signals U1_A / U2_A are both output by the main microcontroller U2. When the slave microcontroller U1 reads data, the signal U1_A can be set to high level 1 and U2_A to low level 0. At this time, only the slave microcontroller U1 can read data. When the main microcontroller U2 reads data, the signal U2_A can be set to high level 1 and U1_A to low level 0. At this time, only the main microcontroller U2 can read data.

[0053] Optionally, when there are multiple storage circuits or multiple memory U21s, to facilitate the microcontroller to select the corresponding storage circuit or memory U21. The memory sharing circuit further includes at least one storage indication circuit, and the storage indication circuits are in one-to-one correspondence with the storage circuits; the input terminal of the storage indication circuit is connected to the microcontroller, and the output terminal is connected to the corresponding storage circuit. The storage indication circuit is used to output a signal indicating whether the connected storage circuit is selected. Among them, the input terminal of the storage indication circuit is connected to the working indication terminal, chip select signal terminal of the main microcontroller U2, and the chip select signal terminal of the slave microcontroller U1. The output terminal is connected to the memory U21, and the memory U21 judges whether it is selected according to the signal transmitted by the storage indication circuit.

[0054] In one embodiment, as Figure 5 shown, the storage indication circuit includes the twelfth dual-input NAND gate U27A, the thirteenth dual-input NAND gate U27B, the fourteenth dual-input NAND gate U27C, and the fifteenth dual-input NAND gate U27D. The twelfth dual-input NAND gate U27A, the thirteenth dual-input NAND gate U27B, the fourteenth dual-input NAND gate U27C, and the fifteenth dual-input NAND gate U27D form the fourth logic chip. The chip select signal SS2 and the GPIO port signal DATA_CON1 output by the main microcontroller U2 pass through the twelfth dual-input NAND gate U27A to obtain the signal C. The signal obtained by the GPIO port signal DATA_CON1 passing through the fourteenth dual-input NAND gate U27C and the chip select signal SS1 of the slave microcontroller U1 pass through the fifteenth dual-input NAND gate U27D to obtain the signal D. The signal C and the signal D pass through the thirteenth dual-input NAND gate U27B to obtain the signal SS_1, and the signal SS_1 is input to the SS_1 memory U21. The memory U21 determines whether it is selected according to the signal SS_1. When the signal SS_1 is at a low level of 0, it indicates that the memory U21 is selected and data reading and writing operations can be performed; when the signal SS_1 is 1, it indicates that the memory U21 is not selected.

[0055] Therefore, as can be seen from the above embodiments, the memory sharing circuit restricts the working state of the slave microcontroller U1 when the main microcontroller U2 needs to read or store, and restricts the working state of the main microcontroller U2 when the slave microcontroller U1 reads or stores. Thus, when a certain microcontroller reads or stores, the reading and storage of the memory U21 by the remaining microcontrollers are blocked, which is equivalent to each microcontroller having its own memory U21. The main microcontroller U2 outputs the signals U1_A and U2_A, so as to determine whether the slave microcontroller U1 or the main microcontroller U2 receives information when the memory U21 chip outputs the data output signal MISO1_1. The main microcontroller U2 and the slave microcontroller U1 can also read the mutually stored programs through the memory U21 in the storage circuit, greatly expanding the storage space, reducing the use of the GPIO ports of the main microcontroller U2, greatly increasing the working ability of the microcontroller, and effectively solving the problem of limited storage space of the microcontroller and reducing the cost of the microcontroller.

[0056] According to one aspect of the embodiments of the present application, an electronic device is further provided, as Figure 9 shown, the electronic device includes at least two microcontrollers, at least one storage circuit, and the memory sharing circuit as described in the above embodiment items. The memory sharing circuit is electrically connected to the microcontrollers and the storage circuit respectively. The microcontrollers realize storing data in the storage circuit and reading data in the storage circuit through the memory sharing circuit.

[0057] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the description, claims and the above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in words.

[0058] It should be understood that although the flowchart of the embodiments of the present application indicates each operation step by an arrow, the execution order of these steps is not limited to the order indicated by the arrow. Unless otherwise clearly stated in this document, in some implementation scenarios of the embodiments of the present application, the implementation steps in each flowchart can be executed in other orders according to requirements. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage of these sub-steps or stages can also be executed at different times respectively. In the scenario where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and the embodiments of the present application do not limit this.

[0059] The above are only optional implementation manners of some implementation scenarios of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the technical concept of the solution of the present application, adopting other similar implementation means based on the technical idea of the present application also belongs to the protection scope of the embodiments of the present application.

Claims

1. A memory sharing circuit, characterized in that: include: A working indication circuit, a data transmission circuit, at least one storage circuit connected to at least two single-chip microcomputers through the working indication circuit and the data transmission circuit, the storage circuit is provided with a memory, and the at least two single-chip microcomputers include a main single-chip microcomputer; The input end of the work indication circuit is connected to the work indication end of the main single-chip microcomputer, and the output end is connected to the storage circuit. The work indication circuit is used to trigger the output of the single-chip microcomputer indication signal corresponding to the work indication signal when receiving the work indication signal output by the work indication end. The single-chip microcomputer indication signal is used to indicate the single-chip microcomputer currently transmitting data; The input end of the data transmission circuit is connected to the data transmission ends of the at least two single-chip microcomputers and the working indication end of the main single-chip microcomputer, and the output end is connected to the storage circuit. The data transmission circuit is used to form a data transmission path between the storage circuit and the single-chip microcomputer corresponding to the working indication signal.

2. The memory sharing circuit according to claim 1, wherein: The at least two single-chip microcomputers also include a slave single-chip microcomputer, and the working indication circuit includes a first logic chip circuit, the input end of the first logic chip circuit is connected to the working indication end, the clock signal end and the clock signal end of the slave single-chip microcomputer, and the output end of the first logic chip circuit is connected to the storage circuit.

3. The memory sharing circuit according to claim 2, characterized in that: The first logic chip circuit includes a first double-input NAND gate, a second double-input NAND gate, a third double-input NAND gate and a fourth double-input NAND gate. The working indication terminal of the master single-chip microcomputer is connected to the second input terminal of the first double-input NAND gate and the input terminal of the third double-input NAND gate. The first input terminal of the first double-input NAND gate is connected to the clock signal terminal of the master single-chip microcomputer. The output terminal of the first double-input NAND gate is connected to the first input terminal of the second double-input NAND gate. The output terminal of the third double-input NAND gate is connected to the first input terminal of the fourth double-input NAND gate. The second input terminal of the fourth double-input NAND gate is connected to the clock signal terminal of the slave single-chip microcomputer. The output terminal of the fourth double-input NAND gate is connected to the second input terminal of the second double-input NAND gate. The output terminal of the second double-input NAND gate is connected to the storage circuit.

4. The memory sharing circuit according to claim 2, wherein: The working indication end includes a first indication end, the input end of the first logic chip circuit is connected to the first indication end, the data transmission circuit includes a second logic chip circuit, the input end of the second logic chip circuit is connected to the first indication end and the data output end of the master microcontroller and the data output end of the slave microcontroller.

5. The memory sharing circuit according to claim 4, characterized in that: The second logic chip circuit includes a fifth dual-input NAND gate, a sixth dual-input NAND gate, a seventh dual-input NAND gate and an eighth dual-input NAND gate, the first indication end is connected to the second input end of the fifth dual-input NAND gate and the input end of the seventh dual-input NAND gate, the output end of the seventh dual-input NAND gate is connected to the first input end of the eighth dual-input NAND gate, the second input end of the eighth dual-input NAND gate is connected to the data output end of the slave microcontroller, the output end of the eighth dual-input NAND gate is connected to the second input end of the sixth dual-input NAND gate, the first input end of the fifth dual-input NAND gate is connected to the data output end of the master microcontroller, the output end of the fifth dual-input NAND gate is connected to the first input end of the sixth dual-input NAND gate, and the output end of the sixth dual-input NAND gate is connected to the storage circuit.

6. The memory sharing circuit according to claim 4, characterized in that: The working indication circuit includes a second indication terminal and a third indication terminal, and the data transmission circuit also includes a third logic chip circuit, the input terminal of the third logic chip circuit is connected to the data output terminal of the storage circuit, the second indication terminal, and the third indication terminal, and the output terminal of the third logic chip circuit is connected to the data receiving terminal of the master microcontroller and the data receiving terminal of the slave microcontroller.

7. The memory sharing circuit according to claim 6, wherein: The third logic chip circuit includes a ninth dual-input NAND gate, a tenth dual-input NAND gate, an eleventh dual-input NAND gate and a one-hundred-and-forty-fifth resistor, the first input end of the ninth dual-input NAND gate is connected to the second indication end, the input end of the tenth dual-input NAND gate is connected to the data output end of the storage circuit and the first end of the one-hundred-and-forty-fifth resistor, the second end of the one-hundred-and-forty-fifth resistor is grounded, the output end of the tenth dual-input NAND gate is connected to the second input end of the ninth dual-input NAND gate and the first input end of the eleventh dual-input NAND gate, the second input end of the eleventh dual-input NAND gate is connected to the third indication end, the output end of the eleventh dual-input NAND gate is connected to the data receiving end of the master microcontroller, and the output end of the ninth dual-input NAND gate is connected to the data receiving end of the slave microcontroller.

8. The memory sharing circuit according to claim 2, wherein: Also comprising at least one storage indication circuit, wherein the storage indication circuit corresponds one-to-one with the storage circuit; The input end of the storage indication circuit is connected to the single chip microcomputer, and the output end is connected to the corresponding storage circuit. The storage indication circuit is used to output a signal indicating whether the connected storage circuit is selected.

9. The memory sharing circuit according to claim 8, characterized in that: The input end of the storage indication circuit is connected to the working indication end, the chip selection signal end and the chip selection signal end of the master single chip microcomputer, and the output end is connected to the memory.

10. An electronic device, characterized in that: The electronic device comprises at least two single-chip microcomputers, at least one storage circuit and a memory sharing circuit as claimed in any one of claims 1 to 9, wherein the memory sharing circuit is electrically connected to the single-chip microcomputers and the storage circuit respectively.

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