Substrate structure

Abstract

The utility model provides a substrate structure which comprises a substrate connected between a chip and a circuit board, one side of the substrate is provided with a first pin structure and a second pin structure which are connected with the circuit board, the first pin structure is connected with a digital power supply end of the chip, and the second pin structure is connected with a digital power supply end of the chip. The second pin structure is connected with an analog power supply end of the chip; the inductor structure is electrically connected between the first pin structure and the second pin structure; according to the substrate structure provided by the utility model, the problem that the control accuracy of a chip switch is easily influenced by noise generated by a substrate circuit under the influence of a high-frequency signal due to the fact that pins corresponding to various power supply types are arranged on the substrate is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a substrate structure. Background Art

[0002] The description of this part only provides background information related to the disclosure of the utility model, and does not constitute prior art.

[0003] In the technical field of chip packaging, considering the miniaturization of chips and the problem of signal interference between the digital power supply and the analog power supply of chips, single-chip packaging is generally adopted. The effects and functions to be achieved by each chip are relatively single. Therefore, usually only one type of power supply is set for a single chip. If multiple functions are required, function modules are usually added on the PCB board to realize the function integration of the system.

[0004] With the complexity of chip functions and the increasing demand for solving problems, the quality requirements for chip transmission signals are also getting higher and higher. The density of integrated chips on the PCB board is low, and the signal transmission distance is too long, which will seriously affect the signal quality output by highly integrated chips. Products such as Flash (flash memory chip), sensor (image sensor), DRAM (Dynamic Random Access Memory), etc. require more functions and need to integrate multiple functions on the same chip and output multiple signals. Therefore, in the trend of chip miniaturization and high integration, analog signals, digital signals, and high-speed signals will appear on the same chip at the same time.

[0005] Furthermore, when the output signals on the same chip include both analog signals and digital signals, the digital signal is a pulse signal, which has a large tolerance for noise, while the analog signal is a linear signal. The pulse of the digital signal can be decomposed into multiple sine / cosine waves of different frequencies through Fourier transform, that is, noise. This leads to the fact that if the pins of the digital signal and the pins of the analog signal are connected, the noise of the digital signal will affect the analog signal, and these noises will enter the pins of the analog signal through coupling or resonance, etc., affecting the output result of the analog signal.

[0006] Furthermore, when there are also high-speed IO signals among the output signals on the same chip, due to the high frequency of the high-speed IO signals, in the high-frequency state, in addition to being transmitted within the IO lines, the IO signals will also generate loop signals coupled with the IO signals within the IO lines. Therefore, even if there is an insulating material filled between the IO traces and other traces, in the high-frequency state, the insulating material will be approximated as a capacitor, and other traces will be approximated as inductors. Among them, the flow path of the loop signal needs to be judged based on the reference plane of the substrate or circuit board. If there is a split band designed on the reference plane due to different power supplies or functions, and the IO trace becomes a cross-split trace on the reference plane, then the signal loop of the high-frequency IO signal needs to bypass the split band on the reference plane, which means that the loop area of the high-frequency IO signal increases, and further the intensity of the interfering electric field increases; in an environment with a relatively high-intensity interfering electric field, the output voltages of the IO signals and power supply signals of the chip will oscillate due to the interfering electric field, resulting in unstable output results.

[0007] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0008] The purpose of the present invention is to provide a substrate structure, which solves the problem that the noise generated by the substrate circuit under the influence of high-frequency signals easily affects the accuracy of the chip power supply control due to the pins corresponding to multiple power supply types being provided on the substrate.

[0009] The above implementation purpose of the present invention is mainly achieved by the following technical solutions:

[0010] The present invention provides a substrate structure, including:

[0011] A substrate, connected between the chip and the circuit board. On one side of the substrate, there are provided a first pin structure and a second pin structure for connecting the circuit board. The first pin structure is connected to the digital power supply terminal of the chip, and the second pin structure is connected to the analog power supply terminal of the chip;

[0012] An inductance structure, electrically connected between the first pin structure and the second pin structure.

[0013] In a specific embodiment, the first pin structure includes a first electrical pin and a first ground pin arranged at intervals. The first electrical pin is connected to the electrical output point of the digital power supply terminal, and the first ground pin is connected to the ground output point of the digital power supply terminal;

[0014] The second pin structure includes a second electrical pin and a second ground pin which are spaced apart. The second electrical pin is connected to the electrical output point of the analog power supply terminal, and the second ground pin is connected to the ground output point of the analog power supply terminal;

[0015] The inductor structure has a first inductor and a second inductor. The first electrical pin and the second electrical pin are electrically connected through at least one of the first inductors, and the first ground pin and the second ground pin are electrically connected through at least one of the second inductors.

[0016] In a specific embodiment, among the first electrical pin, the first ground pin, the second electrical pin, and the second ground pin, the number of pins of at least one of them is multiple.

[0017] In a specific embodiment, the number of pins of the first electrical pin, the first ground pin, the second electrical pin, and the second ground pin are all multiple, and the multiple pins are electrically connected to form a pin group.

[0018] In a specific embodiment, multiple first electrical pins are electrically connected to form a first pin group, and multiple second electrical pins are electrically connected to form a second pin group. The first pin group and the second pin group are electrically connected through at least one of the first inductors arranged at adjacent positions thereof;

[0019] And / or, multiple first ground pins are electrically connected to form a third pin group, and multiple second ground pins are electrically connected to form a fourth pin group. The third pin group and the fourth pin group are electrically connected through at least one of the second inductors arranged at adjacent positions thereof.

[0020] In a specific embodiment, the substrate further has a third inductor and a fourth inductor;

[0021] Multiple first electrical pins for accessing different voltages are electrically connected through the third inductor; multiple first ground pins for accessing different voltage differences are electrically connected through the fourth inductor;

[0022] Multiple second electrical pins for accessing different voltages are electrically connected through the third inductor; multiple second ground pins for accessing different voltage differences are electrically connected through the fourth inductor.

[0023] In a specific embodiment, multiple first electrical pins for accessing different voltages are electrically connected to the first electrical pin connected to the first inductor through the third inductor, and multiple second electrical pins for accessing different voltages are electrically connected to the second electrical pin connected to the first inductor through the third inductor;

[0024] A plurality of the first ground pins for accessing different pressure differences are electrically connected to the first ground pin connected to the second inductor through the fourth inductor, and a plurality of the second ground pins for accessing different pressure differences are electrically connected to the second ground pin connected to the second inductor through the fourth inductor.

[0025] In a specific embodiment, the substrate further has a conductor plate and a ground conductor plate;

[0026] A plurality of the first electrical pins for accessing the same voltage or a plurality of the second electrical pins for accessing the same voltage are electrically connected through the conductor plate;

[0027] A plurality of the first ground pins for accessing the same pressure difference or a plurality of the second ground pins for accessing the same pressure difference are electrically connected through the ground conductor plate.

[0028] In a specific embodiment, the impedance values of the conductor plate are respectively less than the impedance values of the first inductor and the third inductor;

[0029] The impedance values of the ground conductor plate are respectively less than the impedance values of the second inductor and the fourth inductor.

[0030] In a specific embodiment, the first pin structure and the second pin structure are disposed on opposite sides of the surface of the substrate facing the circuit board.

[0031] In a specific embodiment, a plurality of the first ground pins for accessing the same pressure difference are disposed adjacent to each other and form a first pin group with the same pressure, and a plurality of the first electrical pins for accessing the corresponding voltage are disposed adjacent to each other and form a second pin group with the same pressure, and the second pin group with the same pressure surrounds the first pin group with the same pressure on the outside;

[0032] A plurality of the second ground pins for accessing the same pressure difference are disposed adjacent to each other and form a third pin group with the same pressure, and a plurality of the second electrical pins for accessing the corresponding voltage are disposed adjacent to each other and form a fourth pin group with the same pressure, and the fourth pin group with the same pressure surrounds the third pin group with the same pressure on the outside.

[0033] In a specific embodiment, the distance between adjacent conductor plates is greater than or equal to twice the designed line width of the circuit board, and / or, the distance between adjacent ground conductor plates is greater than or equal to twice the designed line width of the circuit board.

[0034] In a specific embodiment, the projection of the edge line where the chip is connected to the substrate forms a projection line on the surface of the substrate on the side connected to the circuit board, and the first electrical pin and the second electrical pin are both disposed close to the projection line.

[0035] Compared with the prior art, the technical solution of the present utility model has the following characteristics and advantages:

[0036] For the substrate structure provided by the present utility model, an inductance structure is arranged between the first pin structure connected to the digital power supply terminal and the second pin structure connected to the analog power supply terminal, realizing the erection of an inductance structure on the cross-segmented trace between the digital power module and the analog power module on the circuit board reference plane. When the chip outputs a high-frequency signal at the IO point, the loop signal of the IO trace connecting the substrate to the chip high-frequency signal can cross the cross-segmented trace on the circuit board reference plane along the inductance structure, avoiding the problem that the loop signal still needs to bypass the cross-segmented trace on the circuit board reference plane.

[0037] Furthermore, for the substrate structure provided by the utility model, by arranging an inductance structure between the first pin structure connected to the digital power supply terminal and the second pin structure connected to the analog power supply terminal, it is possible to avoid the interference of the digital frequency amplitude accessed by the first pin structure on the analog frequency amplitude accessed by the second pin structure, improving the signal shielding ability of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a package structure diagram provided with the substrate structure of the present utility model;

[0039] Figure 2 It is a top view of the chip;

[0040] Figure 3 It is a structure diagram of the first embodiment of the package structure provided with the substrate structure of the present utility model;

[0041] Figure 4 It is a structure diagram of the second embodiment of the package structure provided with the substrate structure of the present utility model;

[0042] Figure 5 It is a structure diagram of the first embodiment of the substrate structure of the present utility model;

[0043] Figure 6 It is a structure diagram of the second embodiment of the substrate structure of the present utility model;

[0044] Figure 7 It is a structure diagram of the third embodiment of the substrate structure of the present utility model;

[0045] Figure 8 It is a structure diagram of the fourth embodiment of the substrate structure of the present utility model;

[0046] Figure 9 It is a structure diagram of the fifth embodiment of the substrate structure of the present utility model;

[0047] Figure 10Structural diagram of the sixth embodiment of the substrate structure of the present utility model;

[0048] Figure 11 Structural diagram of the seventh embodiment of the substrate structure of the present utility model;

[0049] Figure 12 Structural diagram of the first partial embodiment of the substrate structure of the present utility model;

[0050] Figure 13 Structural diagram of the second partial embodiment of the substrate structure of the present utility model;

[0051] Figure 14 Structural diagram of the third partial embodiment of the substrate structure of the present utility model;

[0052] Figure 15 Structural diagram of the fourth partial embodiment of the substrate structure of the present utility model;

[0053] Figure 16 Structural diagram of the eighth embodiment of the substrate structure of the present utility model;

[0054] Figure 17 Structural diagram of the ninth embodiment of the substrate structure of the present utility model.

[0055] Explanation of the reference numerals in the attached drawings:

[0056] 1. Substrate; 11. First pin structure; 111. First electrical pin; 112. First ground pin; 12. Second pin structure; 121. Second electrical pin; 122. Second ground pin; 13. Third inductor; 14. Fourth inductor; 15. Trace; 16. Cross-segment trace

[0057] 2. Chip; 21. Digital power supply terminal; 211. Electrical output point of the digital power supply terminal; 212. Ground output point of the digital power supply terminal; 22. Analog power supply terminal; 221. Electrical output point of the analog power supply terminal; 222. Ground output point of the analog power supply terminal; 23. IO point; 24. Projection line; 25. Bonding wire

[0058] 3. Circuit board;

[0059] 4. Inductor structure; 41. First inductor; 42. Second inductor;

[0060] 51. Electrical conductor plate; 52. Ground conductor plate;

[0061] A1. First pin group; A2. First pin group with the same voltage;

[0062] B1. Second pin group; B2. Second pin group with the same voltage;

[0063] C1. The third pin group; C2. The third pin group with the same voltage;

[0064] D1. The fourth pin group; D2. The fourth pin group with the same voltage. Detailed implementation manners

[0065] In order to enable those skilled in the art to better understand the technical solutions in the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0066] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only embodiments.

[0067] It should also be understood that in the embodiments herein, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the front and rear associated objects.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present utility model belongs. The terms used in the description of the present utility model herein are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0069] As Figures 1 to 4 shown, the present utility model provides a substrate structure, including:

[0070] A substrate 1, connected between a chip 2 and a circuit board 3. A first pin structure 11 and a second pin structure 12 for connecting to the circuit board 3 are provided on one side of the substrate 1. The first pin structure 11 is connected to the digital power supply terminal 21 of the chip 2, and the second pin structure 12 is connected to the analog power supply terminal 22 of the chip 2.

[0071] An inductance structure 4 is electrically connected between a first pin structure 11 and a second pin structure 12.

[0072] The intensity of the interfering electric field within the substrate 1 of the substrate structure provided by the present utility model is determined by the area of the working loop. In the existing design of the substrate 1, the loop signal needs to bypass the cross - split trace 16 on the reference plane of the circuit board 3, increasing the area of the working loop and the intensity of the interfering electric field. This results in an interfering electric field with a large electric field intensity in the working loop of the high - frequency signal. Since the circuit of the chip 2 is composed of MOS transistors and the gate flip - flop is achieved through charge and discharge, under the influence of the large interfering electric field, the voltages received by the MOS transistors of the chip 2 fluctuate continuously, leading to abnormal charge and discharge, that is, abnormal flipping of the electric gates of the chip 2, and incorrect output results of the chip 2.

[0073] In the substrate structure provided by the present utility model, by arranging the inductance structure 4 between the first pin structure 11 connected to the digital power supply terminal 21 and the second pin structure 12 connected to the analog power supply terminal 22, an inductance structure 4 is erected on the cross - split trace 16 between the digital power supply module and the analog power supply module on the reference plane of the circuit board 3. When the chip 2 outputs a high - frequency signal at the IO point 23, the loop signal of the IO trace connecting the substrate 1 to the high - frequency signal of the chip 2 can cross the cross - split trace 16 on the reference plane of the circuit board 3 along the inductance structure 4, avoiding the problem that the loop signal still needs to bypass the cross - split trace 16 on the reference plane of the circuit board 3.

[0074] Furthermore, in the substrate structure provided by the utility model, by arranging the inductance structure 4 between the first pin structure 11 connected to the digital power supply terminal 21 and the second pin structure 12 connected to the analog power supply terminal 22, it is possible to avoid the interference effect of the digital frequency amplitude accessed by the first pin structure 11 on the analog frequency amplitude accessed by the second pin structure 12, and improve the signal shielding ability of the substrate 1.

[0075] In this embodiment, the circuit board 3, the substrate 1, and the chip 2 are stacked in sequence. One side of the bottom surface of the substrate 1 is attached to the circuit board 3, and one side of the top surface of the substrate 1 is used to place the chip 2. Among them, a plurality of pins are provided on both the top surface and the bottom surface of the substrate 1. The plurality of pins on the top surface of the substrate 1 are electrically connected to the plurality of pins on the bottom surface of the substrate 1 through a plurality of traces 15 within the substrate 1. The plurality of pins on the top surface of the substrate 1 are connected to the plurality of output points of the chip 2 through wire bonding 25, and the plurality of pins on the bottom surface of the substrate 1 are connected to the connection points on the circuit board 3.

[0076] In this embodiment, multiple pins on the bottom surface of the substrate 1 can be divided into a first pin structure 11 connecting to the digital power supply terminal 21 of the chip 2 and a second pin structure 12 connecting to the analog power supply terminal 22 of the chip 2. Among them, the first pin structure 11 has multiple pins connecting to the digital power supply terminal 21 of the chip 2, and the second pin structure 12 has multiple pins connecting to the analog power supply terminal 22 of the chip 2. In this embodiment, an inductance structure 4 is provided between the first pin structure 11 and the second pin structure 12.

[0077] In this embodiment, multiple like pins of the first pin structure 11 are electrically connected to each other, and multiple like pins of the second pin structure 12 are electrically connected to each other. In other embodiments, the connection relationships of multiple pins within the first pin structure 11 and the connection relationships of multiple pins within the second pin structure 12 are not specifically limited.

[0078] In one embodiment, with reference to Figure 3 as shown, multiple pins within the first pin structure 11 can be electrically connected to each other on the bottom surface of the substrate 1 facing the circuit board 3. In another embodiment, with reference to Figure 4 as shown, multiple pins within the first pin structure 11 can be electrically connected to each other on the top surface of the substrate 1 facing the chip 2, and no specific limitation is made thereto. In this embodiment, the inductance structure 4 is generally a wound metal wire. In other embodiments, the inductance structure 4 can also adopt other structures with higher impedance values, such as inductors, and no specific limitation is made thereto.

[0079] As Figure 5 shown, in a specific implementation manner, the first pin structure 11 includes a first electrical pin 111 and a first ground pin 112 arranged at intervals. The first electrical pin 111 is connected to the electrical output point 211 of the digital power supply terminal 21, and the first ground pin 112 is connected to the ground output point 212 of the digital power supply terminal 21.

[0080] The second pin structure 12 includes a second electrical pin 121 and a second ground pin 122 arranged at intervals. The second electrical pin 121 is connected to the electrical output point 221 of the analog power supply terminal 22, and the second ground pin 122 is connected to the ground output point 222 of the analog power supply terminal 22.

[0081] The inductance structure 4 has a first inductor 41 and a second inductor 42. The first electrical pin 111 and the second electrical pin 121 are electrically connected through at least one first inductor 41, and the first ground pin 112 and the second ground pin 122 are electrically connected through at least one second inductor 42.

[0082] The substrate structure provided by the present utility model divides the multiple pins of the first pin structure 11 into first electrical pins 111 and first ground pins 112, and divides the multiple pins of the second pin structure 12 into second electrical pins 121 and second ground pins 122, which can more precisely improve the signal shielding ability between signals of the substrate 1, and also enables the electrical signals of the digital power supply and the electrical signals of the analog power supply, and the ground signals of the digital power supply and the ground signals of the analog power supply to be isolated respectively, avoiding the problem that it is easier to generate signal interference between adjacent signals. At the same time, it can also ensure that the signal loop of the high-frequency IO trace where the reference plane of the circuit board 3 crosses the dividing line can find a relatively short return path, achieving the effect of reducing the interference electric field intensity of the high-frequency IO working loop.

[0083] With reference to Figure 3 and Figure 4 As shown, in this embodiment, the first electrical pins 111 of the first pin structure 11 are connected to the electrical output point 211 of the digital power supply terminal 21 through the traces 15 inside the substrate 1 and the wire bonds 25 outside the substrate 1, and the first ground pins 112 of the first pin structure 11 are connected to the ground output point 212 of the digital power supply terminal 21 through the traces 15 inside the substrate 1 and the wire bonds 25 outside the substrate 1; in this embodiment, the second electrical pins 121 of the second pin structure 12 are connected to the electrical output point 221 of the analog power supply terminal 22 through the traces 15 inside the substrate 1 and the wire bonds 25 outside the substrate 1, and the second ground pins 122 of the second pin structure 12 are connected to the ground output point 222 of the analog power supply terminal 22 through the traces 15 inside the substrate 1 and the wire bonds 25 outside the substrate 1; in this embodiment, the inductance structure 4 has a first inductor 41 and a second inductor 42, and both the first inductor 41 and the second inductor 42 are inductor-type components, and no specific limitations are imposed on the parameters of the first inductor 41 and the parameters of the second inductor 42.

[0084] In this embodiment, with reference to Figure 6 As shown, the two ends of the first inductor 41 are respectively connected to the first electrical pin 111 and the second electrical pin 121, realizing the electrical connection between the first electrical pin 111 and the second electrical pin 121; in this embodiment, the two ends of the second inductor 42 are respectively connected to the first ground pin 112 and the second ground pin 122, realizing the electrical connection between the first ground pin 112 and the second ground pin 122.

[0085] As Figure 7 to and Figure 10 As shown, in a specific embodiment, among the first electrical pin 111, the first ground pin 112, the second electrical pin 121, and the second ground pin 122, at least one of the pins has a plurality of numbers.

[0086] In the substrate structure provided by this embodiment, in a specific embodiment, there is an embodiment in which the number of the first electrical pins 111 is multiple and the number of the second electrical pins 121 is one. In this embodiment, the multiple first electrical pins 111 are electrically connected to each other to form a first pin group A1, and the first pin group A1 is electrically connected to the second electrical pin 121 through a first inductor 41 disposed at a position adjacent to the two; in another specific embodiment, there is an embodiment in which the number of the first electrical pins 111 is one and the number of the second electrical pins 121 is multiple. In this embodiment, the multiple second electrical pins 121 are electrically connected to each other to form a second pin group B1, and the second pin group B1 is electrically connected to the first electrical pin 111 through a first inductor 41 disposed at a position adjacent to the two; in other embodiments, there are also embodiments in which the number of the first electrical pins 111 is multiple and the number of the second electrical pins 121 is multiple.

[0087] In the substrate structure provided by this embodiment, in yet another specific embodiment, there is an embodiment in which the number of the first ground pins 112 is one and the number of the second ground pins 122 is multiple. In this embodiment, the multiple second ground pins 122 are electrically connected to each other to form a fourth pin group D1, and the fourth pin group D1 is electrically connected to the first ground pin 112 through a second inductor 42 disposed at a position adjacent to the two; in still another specific embodiment, there is an embodiment in which the number of the first ground pins 112 is multiple and the number of the second ground pins 122 is one. In this embodiment, the multiple first ground pins 112 are electrically connected to each other to form a third pin group C1, and the third pin group C1 is electrically connected to the second ground pin 122 through a second inductor 42 disposed at a position adjacent to the two. In other embodiments, there are also embodiments in which the number of the first ground pins 112 is multiple and the number of the second ground pins 122 is multiple.

[0088] As Figure 7 to and Figure 10 shown, in a specific embodiment, the number of the first electrical pins 111, the first ground pins 112, the second electrical pins 121, and the second ground pins is multiple, and the multiple pins are electrically connected to each other to form a pin group.

[0089] In the substrate structure provided by this embodiment, when the first electrical pins 111, the first ground pins 112, the second electrical pins 121, and the second ground pins 122 are all multiple, the multiple first electrical pins 111 are electrically connected to each other to form a pin group, the multiple first ground pins 112 are electrically connected to each other to form a pin group, the multiple second electrical pins 121 are electrically connected to each other to form a pin group, and the multiple second ground pins 122 are electrically connected to each other to form a pin group; it is convenient for electrical connection between each pin group through a conductor or electromagnetic isolation through an inductor, and avoids the problem of complex substrate wiring caused by the need for electrical connection between all pins.

[0090] As Figure 7 Zhihuo Figure 10 shown, in a specific embodiment, a plurality of first electrical pins 111 are electrically connected to each other to form a first pin group A1, and a plurality of second electrical pins 121 are electrically connected to each other to form a second pin group B1. The first pin group A1 and the second pin group B1 are electrically connected by at least one first inductor 41 disposed at a position adjacent to each other;

[0091] And / or, a plurality of first ground pins 112 are electrically connected to each other to form a third pin group C1, and a plurality of second ground pins 122 are electrically connected to each other to form a fourth pin group D1. The third pin group C1 and the fourth pin group D1 are electrically connected by at least one second inductor 42 disposed at a position adjacent to each other.

[0092] The substrate structure provided by this embodiment provides a preferred arrangement and connection method for a plurality of pins when the first electrical pins 111, the first ground pins 112, the second electrical pins 121, and the second ground pins 122 are all in plurality; wherein, by disposing at least one first inductor 41 at a position adjacent to the first pin group A1 and the second pin group B1, and disposing at least one second inductor 42 at a position adjacent to the third pin group C1 and the fourth pin group D1, the number of the first inductor 41 and the second inductor 42 can be reduced, the wiring complexity of the substrate structure can be reduced, and the structure can be simplified; at the same time, the first inductor 41 is connected at a position adjacent to the first pin group A1 and the second pin group B1, and the second inductor 42 is connected at a position adjacent to the third pin group C1 and the fourth pin group D1, which can also ensure that the signal loop of the high-frequency IO trace across the dividing line of the circuit board 3 reference plane can find a relatively close return path, achieving the effect of reducing the interference electric field intensity of the high-frequency IO working loop.

[0093] In this embodiment, the plurality of first electrical pins 111, the plurality of second electrical pins 121, the plurality of first ground pins 112, and the plurality of second ground pins 122 are spaced apart and disposed on one side surface of the substrate 1.

[0094] Among them, in a specific embodiment, the plurality of first electrical pins 111 are sequentially disposed adjacent to each other in a column, the plurality of second electrical pins 121 are sequentially disposed adjacent to each other in a column, the plurality of first ground pins 112 are sequentially disposed adjacent to each other in a column, or the plurality of second ground pins 122 are sequentially disposed adjacent to each other in a column. In one embodiment, with reference to Figure 7 shown, the first pin group A1 and the second pin group B1 are arranged in parallel, and the first inductor 41 is connected between any one of the first electrical pins 111 of the first pin group A1 and the second electrical pin 121 adjacent thereto in the second pin group B1. In another embodiment, with reference to Figure 8As shown, the first pin group A1 and the second pin group B1 are arranged collinearly. The first inductor 41 is connected between the first electrical pin 111 at one end of the first pin group A1 close to the second pin group B1 and the second electrical pin 121 at one end of the second pin group B1 close to the first pin group A1. In other embodiments, there is no specific limitation on the connection manner between the first pin group A1 and the second pin group B1; with reference to Figure 9 As shown, in one embodiment, the third pin group C1 and the fourth pin group D1 are arranged in parallel. The second inductor 42 is connected between any one of the first ground pins 112 of the third pin group C1 and the adjacent second ground pin 122 in the fourth pin group D1. In another embodiment, with reference to Figure 10 As shown, the third pin group C1 and the fourth pin group D1 are arranged collinearly. The second inductor 42 is connected between the first ground pin 112 at one end of the third pin group C1 close to the fourth pin group D1 and the second ground pin 122 at one end of the fourth pin group D1 close to the third pin group C1. In other embodiments, there is no specific limitation on the connection manner between the third pin group C1 and the fourth pin group D1.

[0095] In another specific embodiment, with reference to Figure 11 As shown, there is no specific limitation on the shape formed by the adjacent arrangement of multiple first electrical pins 111, multiple second electrical pins 121, multiple first ground pins 112, or multiple second ground pins 122, that is, they may not be arranged in columns. In this embodiment, the first inductor 41 is connected between the first electrical pin 111 of the first pin group A1 close to the second pin group B1 and the second electrical pin 121 of the second pin group B1 close to the first pin group A1. The second inductor 42 is connected between the first ground pin 112 at one end of the third pin group C1 close to the fourth pin group D1 and the second ground pin 122 at one end of the fourth pin group D1 close to the third pin group C1.

[0096] As Figure 12 and Figure 13 shown, in a specific embodiment, the substrate 1 further has a third inductor 13 and a fourth inductor 14;

[0097] The multiple first electrical pins 111 for accessing different voltages are electrically connected through the third inductor 13, and the multiple first ground pins 112 for accessing different voltage differences are electrically connected through the fourth inductor 14;

[0098] The multiple second electrical pins 121 for accessing different voltages are electrically connected through the third inductor 13, and the multiple second ground pins 122 for accessing different voltage differences are electrically connected through the fourth inductor 14.

[0099] The substrate structure provided by the present utility model electrically connects multiple first electrical pins 111 for accessing different voltages or multiple second electrical pins 121 for accessing different voltages to each other by arranging a third inductor 13, and electrically connects multiple first ground pins 112 for accessing different voltage differences or multiple second ground pins 122 for accessing different voltage differences to each other by arranging a fourth inductor 14, which can improve the signal shielding ability between power signals of the same type and avoid noise interference of power signals of the same type on the signals of adjacent power circuits. Among them, it is also convenient to set cross-sectional traces 16 on the reference plane of the circuit board 3 for the same type of power pins for accessing different voltages during the design of the circuit board 3. With the third inductor 13 and the fourth inductor 14, there is no need to worry about the interference electric field generated by the signal loop of high-frequency IO signals affecting the normal opening and closing of the chip 2 power switch.

[0100] In a specific embodiment of the present invention, the substrate 1 has multiple first electrical pins 111 for accessing various voltages. Among them, the number of first electrical pins 111 for accessing each voltage magnitude is multiple. In other embodiments, the number of first electrical pins 111 for accessing each voltage magnitude can also be only one, and no specific limitation is made thereto; in this embodiment, the substrate 1 also has multiple second electrical pins 121 for accessing various voltages. Among them, the number of second electrical pins 121 for accessing each voltage magnitude is multiple. In other embodiments, the number of second electrical pins 121 for accessing each voltage magnitude can also be only one, and no specific limitation is made thereto; in a specific embodiment, with reference to Figure 12 As shown, multiple first electrical pins 111 for accessing the same voltage are electrically connected to each other and form a first pin group A1 for accessing the same voltage. There are multiple first pin groups A1 for accessing different voltages on the substrate 1. Among them, multiple first pin groups A1 for accessing different voltages are electrically connected by arranging at least one third inductor 13 at the adjacent positions of any two adjacent first pin groups A1. In another specific embodiment, multiple second electrical pins 121 for accessing the same voltage are electrically connected to each other and form a second pin group B1 for accessing the same voltage. There are multiple second pin groups B1 for accessing different voltages on the substrate 1. Among them, multiple second pin groups B1 for accessing different voltages are electrically connected by arranging at least one third inductor 13 at the adjacent positions of any two adjacent second pin groups B1.

[0101] In another specific embodiment of the present invention, the substrate 1 has a plurality of first ground pins 112 for accessing various pressure differences. Among them, the number of first ground pins 112 for accessing each pressure difference magnitude is multiple. In other embodiments, the number of first ground pins 112 for accessing each pressure difference magnitude may also be only one, and no specific limitation is made thereto. In this embodiment, the substrate 1 also has a plurality of second ground pins 122 for accessing various pressure differences. Among them, the number of second ground pins 122 for accessing each pressure difference magnitude is multiple. In other embodiments, the number of second ground pins 122 for accessing each pressure difference magnitude may also be only one, and no specific limitation is made thereto. In a specific embodiment, with reference to Figure 13 As shown, a plurality of first ground pins 112 for accessing the same pressure difference are electrically connected to each other and form a third pin group C1 for accessing the same pressure difference. The substrate 1 is provided with a plurality of third pin groups C1 for accessing different pressure differences. Among them, a plurality of third pin groups C1 for accessing different pressure differences are electrically connected by providing at least one fourth inductor 14 at adjacent positions of any two adjacent third pin groups C1. In another specific embodiment, a plurality of second ground pins 122 for accessing the same pressure difference are electrically connected to each other and form a fourth pin group D1 for accessing the same pressure difference. The substrate 1 is provided with a plurality of fourth pin groups D1 for accessing different pressure differences. Among them, a plurality of fourth pin groups D1 for accessing different pressure differences are electrically connected by providing at least one fourth inductor 14 at adjacent positions of any two adjacent fourth pin groups D1.

[0102] As Figure 14 and Figure 15 shown, in a specific embodiment, a plurality of first electrical pins 111 for accessing different voltages are electrically connected through a third inductor 13 to the first electrical pins 111 connected to a first inductor 41. A plurality of second electrical pins 121 for accessing different voltages are electrically connected through a third inductor 13 to the second electrical pins 121 connected to a first inductor 41.

[0103] A plurality of first ground pins 112 for accessing different pressure differences are electrically connected through a fourth inductor 14 to the first ground pins 112 connected to a second inductor 42. A plurality of second ground pins 122 for accessing different pressure differences are electrically connected through a fourth inductor 14 to the second ground pins 122 connected to a second inductor 42.

[0104] In a specific embodiment, with reference to Figure 14As shown, the number of first electrical pins 111 for accessing various voltage magnitudes is multiple, and the number of second electrical pins 121 for accessing various voltage magnitudes is multiple. Multiple first electrical pins 111 for accessing the same voltage are electrically connected to each other and form a first pin group A1 for accessing the same voltage. Multiple second electrical pins 121 for accessing the same voltage are electrically connected to each other and form a second pin group B1 for accessing the same voltage. On the substrate 1, multiple second pin groups B1 for accessing different voltages and multiple first pin groups A1 are provided. Among them, on the substrate 1, between two adjacent second pin groups B1 and first pin groups A1 among the multiple second pin groups B1 and the multiple first pin groups A1, they are electrically connected to each other through a first inductor 41. Among the multiple second pin groups B1, the other multiple second pin groups B1 not connected to the first inductor 41 are respectively electrically connected to the second pin group B1 connected to the first inductor 41 through a third inductor 13. Among the multiple first pin groups A1, the other multiple first pin groups A1 not connected to the first inductor 41 are respectively electrically connected to the first pin group A1 connected to the first inductor 41 through a third inductor 13, so as to avoid that there are multiple first inductors 41 with different positions connected between the first pin structure 11 and the second pin structure 12, resulting in the parallel flow paths of the signal loops of the high-frequency IO signals, interfering with the superposition of the electric field intensities, and further interfering with the electric field with a relatively large intensity, which affects the normal opening and closing of the power switch of the chip 2. At the same time, it can also avoid that any first pin group A1 is respectively connected to multiple other first pin groups A1 through multiple third inductors 13, or avoid that any second pin group B1 is respectively connected to multiple other second pin groups B1 through multiple third inductors 13, resulting in the parallel flow paths of the signal loops of the high-frequency IO signals, interfering with the superposition of the electric field intensities, and affecting the normal opening and closing of the power switch of the chip 2. In other embodiments, the number of first electrical pins 111 for accessing various voltage magnitudes can also be one, and the number of second electrical pins 121 for accessing various voltage magnitudes can also be one, and no specific limitation is made thereto.

[0105] In another specific embodiment, with reference to Figure 15As shown, the number of first ground pins 112 for accessing different differential pressure magnitudes is multiple, and the number of second ground pins 122 for accessing different differential pressure magnitudes is multiple. Multiple first ground pins 112 for accessing the same differential pressure are electrically connected to each other and form a third pin group C1 for accessing the same differential pressure. Multiple second ground pins 122 for accessing the same differential pressure are electrically connected to each other and form a fourth pin group D1 for accessing the same differential pressure. On the substrate 1, multiple fourth pin groups D1 and multiple third pin groups C1 for accessing different differential pressures are provided. Among them, on the substrate 1, two adjacent fourth pin groups D1 and third pin groups C1 among the multiple fourth pin groups D1 and multiple third pin groups C1 are electrically connected to each other through a second inductor 42. Multiple other fourth pin groups D1 among the multiple fourth pin groups D1 that are not connected to the second inductor 42 are electrically connected to the fourth pin group D1 connected to the second inductor 42 through a fourth inductor 14 respectively. Multiple other third pin groups C1 among the multiple third pin groups C1 that are not connected to the second inductor 42 are electrically connected to the third pin group C1 connected to the second inductor 42 through a fourth inductor 14 respectively, so as to avoid that there are multiple second inductors 42 with different positions connected between the first pin structure 11 and the second pin structure 12, resulting in the parallel connection of the signal loop flow paths of the high-frequency IO signal, interfering with the superposition of the electric field intensities, and further interfering with the electric field to a large extent, affecting the normal opening and closing of the chip 2's power switch. At the same time, it can also avoid that any third pin group C1 is respectively connected to multiple other third pin groups C1 through multiple fourth inductors 14, or avoid that any fourth pin group D1 is respectively connected to multiple other fourth pin groups D1 through multiple fourth inductors 14, resulting in the parallel connection of the signal loop flow paths of the high-frequency IO signal, interfering with the superposition of the electric field intensities, and affecting the normal opening and closing of the chip 2's power switch. In other embodiments, the number of first ground pins 112 for accessing different differential pressure magnitudes can also be one, and the number of second ground pins 122 for accessing different differential pressure magnitudes can also be one, and no specific limitation is made thereto.

[0106] As Figures 7 to 15 shown, in a specific embodiment, the substrate 1 further has a conductor plate 51 and a ground conductor plate 52;

[0107] Multiple first electrical pins 111 for accessing the same voltage or multiple second electrical pins 121 for accessing the same voltage are electrically connected to each other through the conductor plate 51;

[0108] Multiple first ground pins 112 for accessing the same differential pressure or multiple second ground pins 122 for accessing the same differential pressure are electrically connected to each other through the ground conductor plate 52.

[0109] The substrate structure provided by the present utility model can simplify the wiring of the substrate 1 by connecting multiple pins with the same voltage or the same voltage difference in the form of a conductor plate; in this embodiment, both the electrical conductor plate 51 and the ground conductor plate 52 are metal conductor parts, and in other embodiments, the specific materials and structures of the electrical conductor plate 51 and the ground conductor plate 52 are not limited.

[0110] In this embodiment, multiple first electrical pins 111 for accessing the same voltage are electrically connected through the electrical conductor plate 51, and multiple second electrical pins 121 for accessing the same voltage are electrically connected through the electrical conductor plate 51; multiple first ground pins 112 for accessing the same voltage difference are electrically connected through the ground conductor plate 52, and multiple second ground pins 122 for accessing the same voltage difference are electrically connected through the ground conductor plate 52.

[0111] As Figure 5 and Figure 7 shown, in a specific embodiment, the impedance value of the electrical conductor plate 51 is respectively less than the impedance values of the first inductor 41 and the third inductor 13;

[0112] the impedance value of the ground conductor plate 52 is respectively less than the impedance values of the second inductor 42 and the fourth inductor 14.

[0113] The substrate structure provided by the present utility model can avoid the problem that in a high-frequency environment, the loop signal only passes through the electrical conductor plate 51 and the ground conductor plate 52 and does not pass through the first inductor 41, the second inductor 42, the third inductor 13, and the fourth inductor 14 by defining the magnitude relationship between the impedance value of the electrical conductor plate 51 and the impedance values of the first inductor 41 and the third inductor 13, and defining the magnitude relationship between the impedance value of the ground conductor plate 52 and the impedance values of the second inductor 42 and the fourth inductor 14.

[0114] As Figure 7 shown, in a specific embodiment, the first pin structure 11 and the second pin structure 12 are arranged on opposite sides of the surface of the substrate 1 facing the circuit board 3.

[0115] The substrate structure provided by the present utility model, by arranging the first pin structure 11 and the second pin structure 12 on the opposite sides of one side surface of the substrate 1, is beneficial to avoiding the staggered arrangement between the multiple pins of the first pin structure 11 and the multiple pins of the second pin structure 12, and can improve the signal anti-interference ability of the pins of the substrate 1. In this embodiment, the first pin structure 11 has multiple first electrical pins 111 and multiple first ground pins 112, and the second pin structure 12 has multiple second electrical pins 121 and multiple second ground pins 122. Among them, the multiple first electrical pins 111 and the multiple first ground pins 112 are arranged at intervals on one side of the surface of the substrate 1 facing the circuit board 3, and the multiple second electrical pins 121 and the multiple second ground pins 122 are arranged at intervals on the opposite side of the surface of the substrate 1 facing the circuit board 3, so as to avoid the pins connected to the analog power supply terminal 22 and the pins connected to the digital power supply terminal 21 from conflicting and connecting.

[0116] As Figure 16 and Figure 17 shown, in a specific embodiment, multiple first ground pins 112 for accessing the same pressure difference are arranged adjacent to each other to form a first pin group A2 with the same pressure, and multiple first electrical pins 111 for accessing the corresponding voltage are arranged adjacent to each other to form a second pin group B2 with the same pressure. The second pin group B2 with the same pressure is arranged outside the first pin group A2 with the same pressure;

[0117] Multiple second ground pins 122 for accessing the same pressure difference are arranged adjacent to each other to form a third pin group C2 with the same pressure, and multiple second electrical pins 121 for accessing the corresponding voltage are arranged adjacent to each other to form a fourth pin group D2 with the same pressure. The fourth pin group D2 with the same pressure is arranged outside the third pin group C2 with the same pressure.

[0118] In a specific embodiment, with reference to Figure 16 shown, multiple first ground pins 112 for accessing the same pressure difference are arranged adjacent to each other on one side surface of the substrate 1 to form a first pin group A2 with the same pressure where there are no other pins between the multiple first ground pins 112, and multiple first electrical pins 111 for accessing the corresponding voltage are arranged adjacent to each other at intervals on the same side surface to form a second pin group B2 with the same pressure in a columnar shape. Among them, the second pin group B2 with the same pressure is arranged outside the first pin group A2 with the same pressure, which is beneficial to the adjacent arrangement of the first pin group A2 with the same pressure and the second pin group B2 with the same pressure, facilitating the corresponding opening of connection through holes on the circuit board 3. At the same time, the combination of the first pin group A2 with the same pressure and the second pin group B2 with the same pressure can also reduce the signal interference to the pins for accessing different voltages or the pins for accessing the analog power supply.

[0119] In another specific embodiment, with reference to Figure 16As shown, a plurality of second ground pins 122 for accessing the same pressure difference are arranged adjacent to each other on one side surface of the substrate 1 to form a third pin group C2 with the same pressure where there are no other pins between the plurality of second ground pins 122. A plurality of second electrical pins 121 for accessing corresponding voltages are arranged adjacent to each other on the same side surface to form a fourth pin group D2 with the same pressure in a column shape. Among them, the fourth pin group D2 with the same pressure is arranged outside the third pin group C2 with the same pressure, which is beneficial for the third pin group C2 with the same pressure and the fourth pin group D2 with the same pressure to be adjacent to each other, facilitating the corresponding connection through holes to be opened on the circuit board 3. At the same time, the combination of the third pin group C2 with the same pressure and the fourth pin group D2 with the same pressure can also reduce the signal interference to the pins for accessing different voltages or the pins for accessing the digital power supply.

[0120] As Figure 5 and Figure 7 shown, in a specific embodiment, the distance between adjacent electrical conductor plates 51 is greater than or equal to twice the designed line width of the circuit board 3, and / or the distance between adjacent ground conductor plates 52 is greater than or equal to twice the designed line width of the circuit board 3.

[0121] For the substrate structure provided by the present utility model, by limiting the distance between adjacent electrical conductor plates 51 or limiting the distance between adjacent ground conductor plates 52, it is possible to avoid the problem that the distance between adjacent electrical conductor plates 51 is too close, which easily causes signal interference between adjacent electrical conductor plates 51 during the transmission of electrical signals. It can also avoid the problem that the distance between adjacent ground conductor plates 52 is too close, which easily causes signal interference between adjacent ground conductor plates 52 during the transmission of ground signals. It can also avoid the problem that the distance between the electrical conductor plate 51 connecting a plurality of first electrical pins 111 and the electrical conductor plate 51 connecting a plurality of second electrical pins 121 is too close, which easily causes signal interference between the two during the separate transmission of digital electrical signals and analog electrical signals; it also avoids the problem that the distance between the ground conductor plate 52 connecting a plurality of first ground pins 112 and the ground conductor plate 52 connecting a plurality of second ground pins 122 is too close, which easily causes signal interference between the two during the separate transmission of digital ground signals and analog ground signals.

[0122] As Figure 17 shown, in a specific embodiment, the projection line of the edge line where the chip 2 is connected to the substrate 1 forms a projection line 24 on the surface of the substrate 1 on the side connected to the circuit board 3, and the first electrical pin 111 and the second electrical pin 121 are both arranged close to the projection line 24.

[0123] The substrate structure provided by the present utility model, in conjunction with reference to Figure 17As shown, by arranging the first electrical pin 111 and the second electrical pin 121 close to the projection line 24, the power supply path of the chip 2 can be made as short as possible, that is, the length of the power supply path of the chip 2 on the reference plane of the circuit board 3 is reduced, and excessive electric field interference with other signal paths is avoided. In this embodiment, the projection line 24 is the projection of the edge line connecting the chip 2 and the substrate 1 on the surface of the side where the substrate 1 is connected to the circuit board 3. In the state where both the first electrical pin 111 and the second electrical pin 121 are arranged close to the projection line 24, the first electrical pin 111 and the second electrical pin 121 can run through the trace 15 inside the substrate 1 at an almost perpendicular angle, reducing the length of the trace 15 on the reference plane of the circuit board 3 and achieving the effect of reducing electric field interference.

[0124] In the specific embodiments described above, the purpose, technical solutions, and beneficial effects of the present invention have been further described in detail. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A substrate structure, characterized in that: include: A substrate is connected between the chip and the circuit board, wherein one side of the substrate is provided with a first pin structure and a second pin structure connected to the circuit board, wherein the first pin structure is connected to the digital power supply terminal of the chip, and the second pin structure is connected to the analog power supply terminal of the chip; An inductor structure is electrically connected between the first pin structure and the second pin structure.

2. The substrate structure according to claim 1, characterized in that: The first pin structure comprises a first electrical pin and a first ground pin which are arranged at intervals, the first electrical pin is connected to the electrical output point of the digital power supply terminal, and the first ground pin is connected to the ground output point of the digital power supply terminal; The second pin structure comprises a second electrical pin and a second ground pin arranged at intervals, the second electrical pin is connected to the electrical output point of the analog power supply terminal, and the second ground pin is connected to the ground output point of the analog power supply terminal; The inductor structure comprises a first inductor and a second inductor, the first electrical pin and the second electrical pin are electrically connected via at least one of the first inductors, and the first ground pin and the second ground pin are electrically connected via at least one of the second inductors.

3. The substrate structure according to claim 2, characterized in that: At least one of the first electrical pin, the first ground pin, the second electrical pin and the second ground pin has a plurality of pins.

4. The substrate structure according to claim 3, characterized in that: There are multiple pins of the first electrical pin, the first ground pin, the second electrical pin and the second ground pin, and the multiple pins are electrically connected to each other to form a pin group.

5. The substrate structure according to claim 4, characterized in that: A plurality of the first electrical pins are electrically connected to each other and form a first pin group, a plurality of the second electrical pins are electrically connected to each other and form a second pin group, and the first pin group and the second pin group are electrically connected through at least one of the first inductors disposed adjacent to each other; And / or, a plurality of the first ground pins are electrically connected to each other to form a third pin group, a plurality of the second ground pins are electrically connected to each other to form a fourth pin group, and the third pin group and the fourth pin group are electrically connected through at least one of the second inductors arranged at adjacent positions therebetween.

6. The substrate structure according to claim 3 or 5, characterized in that: The substrate also has a third inductor and a fourth inductor; The first plurality of electrical pins for receiving different voltages are electrically connected through the third inductor; the first plurality of ground pins for receiving different voltage differences are electrically connected through the fourth inductor; The plurality of second electrical pins for accessing different voltages are electrically connected through the third inductor; the plurality of second ground pins for accessing different voltage differences are electrically connected through the fourth inductor.

7. The substrate structure according to claim 6, characterized in that: The first electrical pins for connecting to different voltages are electrically connected to the first electrical pin connected to the first inductor through the third inductor, and the second electrical pins for connecting to different voltages are electrically connected to the second electrical pin connected to the first inductor through the third inductor; The first ground pins for connecting to multiple voltage differences are electrically connected to the first ground pin connected to the second inductor through the fourth inductor, and the second ground pins for connecting to multiple voltage differences are electrically connected to the second ground pin connected to the second inductor through the fourth inductor.

8. The substrate structure according to claim 6, characterized in that: The substrate also has an electrical conductor plate and a ground conductor plate; A plurality of the first electrical pins for accessing the same voltage or a plurality of the second electrical pins for accessing the same voltage are electrically connected via the electrical conductor plate; A plurality of the first ground pins for accessing the same voltage difference or a plurality of the second ground pins for accessing the same voltage difference are electrically connected through the ground conductor plate.

9. The substrate structure according to claim 8, characterized in that: The impedance value of the electric conductor plate is respectively smaller than the impedance value of the first inductor and the impedance value of the third inductor; The impedance value of the ground conductor plate is respectively smaller than the impedance value of the second inductor and the impedance value of the fourth inductor.

10. The substrate structure according to claim 1 or 2, characterized in that: The first pin structure and the second pin structure are arranged on opposite sides of a surface of the substrate facing the circuit board.

11. The substrate structure according to claim 8, characterized in that: A plurality of the first ground pins for accessing the same voltage difference are arranged adjacent to each other and form a first pin group with the same voltage, and a plurality of the first electrical pins for accessing the corresponding voltage are arranged adjacent to each other and form a second pin group with the same voltage, and the second pin group with the same voltage is arranged outside the first pin group with the same voltage; The plurality of second ground pins for accessing the same voltage difference are arranged adjacent to each other and form a third pin group with the same voltage, and the plurality of second electrical pins for accessing the corresponding voltage are arranged adjacent to each other and form a fourth pin group with the same voltage, and the fourth pin group with the same voltage is arranged around the outside of the third pin group with the same voltage.

12. The substrate structure according to claim 8, characterized in that: The distance between adjacent electrical conductor plates is greater than or equal to twice the design line width of the circuit board, and / or the distance between adjacent ground conductor plates is greater than or equal to twice the design line width of the circuit board.

13. The substrate structure according to claim 2, characterized in that: The edge line connecting the chip and the substrate is projected onto the surface of the substrate connected to the circuit board to form a projection line, and the first electrical pin and the second electrical pin are both arranged close to the projection line.

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