Clock signal driving circuit and electronic equipment

Abstract

The utility model relates to the technical field of driving circuits, in particular to a clock signal driving circuit and electronic equipment. The circuit comprises a clock signal generation module and a PCB connecting line. The clock signal generation module comprises a driving chip, a filtering module and a signal attenuation module; the driving chip is connected with the clock signal receiving module through the filtering module, the signal attenuation module and the PCB connecting line in sequence; the driving chip is used for sending a clock signal generated by the driving chip to the filtering module for filtering and obtaining a filtered clock signal, and the filtered clock signal carries a reflection interference signal; the filtering module is used for transmitting the filtered clock signal to the signal attenuation module; the signal attenuation module is used for attenuating the reflected interference signal to obtain an interference-free clock signal and transmitting the interference-free clock signal to the clock signal receiving module, and the interference-free clock signal is used for indicating the clock signal receiving module to execute a service, so that the performance index of electromagnetic compatibility can be improved, and the signal integrity can also be considered.

Description

Technical Field

[0001] This application relates to the technical field of driving circuits, and particularly to a clock signal driving circuit and an electronic device. Background Art

[0002] With the continuous enhancement of the driving ability of the CLK signal, the rising edge becomes more and more jittery, the high-frequency components carried by the CLK signal are increasing, and the radiated high-frequency energy to the outside is also getting stronger. For some low-speed signals, the steep rising edge not only fails to bring important benefits to SI (Signal Integrity), but instead causes difficult-to-suppress problems for EMC (Electromagnetic Compatibility). In order to meet the performance indicators of EMC, it is necessary to filter out the high-frequency components of the signal, and improper filtering may be accompanied by SI problems.

[0003] Among them, electromagnetic compatibility refers to the ability of a device or system to meet the requirements of normal operation in its electromagnetic environment and not generate intolerable electromagnetic interference signals to any other device or system in its environment. Utility Model Content

[0004] In view of this, the embodiments of this application provide a clock signal driving circuit and an electronic device, which can effectively improve the performance indicators of electromagnetic compatibility and can also take into account signal integrity, etc.

[0005] In a first aspect, the embodiments of this application provide a clock signal driving circuit, including: a clock signal generation module and a PCB connection line; the clock signal generation module includes a driving chip, a filtering module, and a signal attenuation module;

[0006] The driving chip is connected to the PCB connection line through the filtering module and the signal attenuation module in sequence; the PCB connection line is used to connect a clock signal receiving module;

[0007] The driving chip is used to send the generated clock signal to the filtering module for filtering and obtain a filtered clock signal, wherein the filtered clock signal carries a reflection interference signal; the filtering module is used to transmit the filtered clock signal to the signal attenuation module; the signal attenuation module is used to attenuate the reflection interference signal to obtain an interference-free clock signal and transmit it to the clock signal receiving module, and the interference-free clock signal is used to instruct the clock signal receiving module to execute operations.

[0008] In some embodiments, the filtering module includes a first resistor and a first capacitor;

[0009] One end of the first resistor is connected to the driving chip, and the other end is grounded through the first capacitor; the other end of the first resistor is also connected to the signal attenuation module.

[0010] In some embodiments, the signal attenuation module includes an attenuation resistor;

[0011] One end of the attenuation resistor is connected to the series node of the first resistor and the first capacitor, and the other end is connected to the PCB connection line.

[0012] In some embodiments, the value range of the attenuation resistor is 22Ω - 33Ω.

[0013] In some embodiments, the value range of the first resistor is 22Ω - 33Ω.

[0014] In some embodiments, the value of the first capacitor is determined according to a preset filtering frequency band and the first resistor.

[0015] In some embodiments, the value of the first capacitor is obtained through the following formula:

[0016] C = 1 / (2×PI×R×f)

[0017] Where C is the capacitance value of the first capacitor, R is the resistance value of the first resistor, f is the preset filtering frequency band, and PI is the pi.

[0018] In a second aspect, an embodiment of the present application provides an electronic device, including: a clock signal generation module, a PCB connection line, and a clock signal reception module; the clock signal generation module includes a driving chip, a filtering module, and a signal attenuation module;

[0019] The driving chip is sequentially connected to the clock signal reception module through the filtering module, the signal attenuation module, and the PCB connection line;

[0020] The driving chip is configured to send the generated clock signal to the filtering module for filtering, and obtain a filtered clock signal, where the filtered clock signal carries a reflection interference signal; the filtering module is configured to transmit the filtered clock signal to the signal attenuation module; the signal attenuation module is configured to attenuate the reflection interference signal to obtain an interference-free clock signal and transmit it to the clock signal reception module, and the interference-free clock signal is used to instruct the clock signal reception module to execute a service.

[0021] In some embodiments, the filtering module in the electronic device includes a first resistor and a first capacitor;

[0022] One end of the first resistor is connected to the driving chip, and the other end is grounded through the first capacitor; the other end of the first resistor is also connected to the signal attenuation module.

[0023] In some embodiments, the signal attenuation module in the electronic device includes an attenuation resistor;

[0024] One end of the attenuation resistor is connected to the series node of the first resistor and the first capacitor, and the other end is connected to the PCB connection line.

[0025] The embodiments of the present application have the following beneficial effects:

[0026] The present application includes a clock signal generation module and a PCB connection line; the clock signal generation module includes a driving chip, a filtering module, and a signal attenuation module;

[0027] The driving chip is configured to send the clock signal generated by it to the filtering module for filtering, and obtain a filtered clock signal, wherein the filtered clock signal carries a reflection interference signal; the filtering module is configured to transmit the filtered clock signal to the signal attenuation module; the signal attenuation module is configured to attenuate the reflection interference signal to obtain an interference-free clock signal and transmit it to the clock signal receiving module, and the interference-free clock signal is used to instruct the clock signal receiving module to execute a service.

[0028] In the present application, the EMC performance index is qualified through the filtering module, and on this basis, a signal attenuation module is added at the back end to ensure that the SI performance index meets the requirements. Therefore, the present application can effectively improve the performance index of electromagnetic compatibility and also take into account signal integrity, etc. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 Shows a structural block diagram of a clock signal driving circuit according to an embodiment of the present application;

[0031] Figure 2 Shows a waveform diagram of the clock signal output by the clock signal driving circuit according to an embodiment of the present application;

[0032] Figure 3 Shows a structural block diagram of a first signal driving circuit mentioned in an embodiment of the present application;

[0033] Figure 4 Shows the waveform schematic diagram of the clock signal output by the first signal driving circuit mentioned in the embodiments of the present application;

[0034] Figure 5 Shows the spectrogram of the clock signal output by the first signal driving circuit mentioned in the embodiments of the present application;

[0035] Figure 6 Shows a structural block diagram of the second signal driving circuit mentioned in the embodiments of the present application;

[0036] Figure 7 Shows the spectrogram of the clock signal output by the second signal driving circuit mentioned in the embodiments of the present application;

[0037] Figure 8 Shows the waveform schematic diagram of the clock signal output by the second signal driving circuit mentioned in the embodiments of the present application;

[0038] Figure 9 Shows another structural block diagram of the clock signal driving circuit mentioned in the embodiments of the present application;

[0039] Figure 10 Shows the waveform schematic diagram of the clock signal output by the clock signal driving circuit mentioned in the embodiments of the present application;

[0040] Figure 11 Shows the spectrogram of the clock signal output by the clock signal driving circuit mentioned in the embodiments of the present application;

[0041] Figure 12 Shows a structural schematic diagram of the electronic device mentioned in the embodiments of the present application.

[0042] Main element symbol description:

[0043] 100 - Clock signal generation module; 200 - PCB connection line; 110 - Driving chip; 120 - Filter module; 130 - Signal attenuation module; 300 - Clock signal receiving module. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0045] The components of the embodiments of the present application that are typically depicted and shown in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0046] Hereinafter, the terms "comprising", "having" and their cognates that can be used in various embodiments of the present application are only intended to denote specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as precluding the existence or adding the possibility of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in a commonly used dictionary) will be construed to have the same meaning as the contextual meaning in the relevant technical field and will not be construed to have an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0048] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0049] Sometimes, due to the overly strong driving ability of the chip, the high-frequency energy radiation of the low-speed CLK signal exceeds the standard, and the software cannot reduce the driving ability. Therefore, the present application provides a clock signal driving circuit and an electronic device, which can not only improve the EMC performance index but also take into account the SI problem.

[0050] The following will describe this clock signal driving circuit with reference to some specific embodiments. Figure 1 A structural block diagram of the clock signal driving circuit according to an embodiment of the present application is shown. Exemplarily, the clock signal driving circuit includes: a clock signal generation module 100 and a PCB connection line 200; the clock signal generation module 100 includes a driving chip 110, a filtering module 120, and a signal attenuation module 130.

[0051] The driving chip 110 is used to generate a clock signal.

[0052] The filtering module 120 is not limited to an RC filtering circuit, and the filtering module 120 is used to filter out high-frequency components in the clock signal.

[0053] The signal attenuation module 130 is used to attenuate the reflected signal carried in the filtered clock signal, where the reflected signal is caused by the capacitor in the RC filtering circuit.

[0054] The driving chip 110 is sequentially connected to the PCB connection line 200 through the filtering module 120 and the signal attenuation module 130; the PCB connection line 200 is used to connect the clock signal receiving module 300; among them, the clock signal receiving module is a chip for receiving clock signals.

[0055] The PCB connection line 200 is a connection line or a printed line on the PCB board. The filtering module 120 and the signal attenuation module 130 are arranged close to the driving chip 110. The filtering module 120, the signal attenuation module 130 and the driving chip 110 are at the front end of the PCB board. The filtering module 120 and the signal attenuation module 130 are as close as possible to the driving chip 110, and then are connected to the clock signal receiving module 300 through the PCB connection line 200.

[0056] In this embodiment, the driving chip 110 is used to send the clock signal generated by it to the filtering module 120 for filtering, and obtain the filtered clock signal, where the filtered clock signal carries a reflected interference signal; the filtering module 120 is used to transmit the filtered clock signal to the signal attenuation module 130; the signal attenuation module 130 is used to attenuate the reflected interference signal to obtain an interference-free clock signal and transmit it to the clock signal receiving module 300, and the interference-free clock signal is used to instruct the clock signal receiving module 300 to execute services.

[0057] Further, the filtering module 120 includes a first resistor and a first capacitor;

[0058] One end of the first resistor is connected to the driving chip 110, and the other end is used to be grounded through the first capacitor; the other end of the first resistor is also connected to the signal attenuation module 130.

[0059] Among them, the value range of the first resistor is 22Ω - 33Ω. The value of the first capacitor is determined according to the preset filtering frequency band and the first resistor. That is, the value of the first capacitor is determined according to the EMC exceeding point to determine the filtering frequency band to be filtered and the resistance value of the first resistor. That is, the value of the first capacitor can be obtained through the formula f = 1 / (2×PI×R×C).

[0060] Demonstratively, the value C of the first capacitor is obtained through the following formula:

[0061] C = 1 / (2×PI×R×f)

[0062] Wherein, C is the capacitance value of the first capacitor, R is the resistance value of the first resistor, f is the preset filtering frequency band, and PI is the pi.

[0063] Further, the signal attenuation module 130 includes an attenuation resistor;

[0064] One end of the attenuation resistor is connected to the series node of the first resistor and the first capacitor, and the other end is connected to the PCB connection line 200. Wherein, the value range of the attenuation resistor is 22Ω - 33Ω.

[0065] Specifically, when the value of the attenuation resistor R2 is increased to 1kΩ, the waveform of the clock signal output by the clock signal driving circuit in the embodiment of the present application is as Figure 2 shown (in each waveform diagram in the embodiment of the present application, the horizontal axis represents time, and the vertical axis represents the voltage value of the clock signal). Among them, the waveform is severely attenuated and does not meet the requirements; when the value of the attenuation resistor R2 is decreased to 5Ω, there are still glitches on the waveform of the clock signal output by the clock signal driving circuit in the embodiment of the present application. Therefore, it is not good if the value of the attenuation resistor R2 is too large or too small. Thus, the embodiment of the present application recommends that the value range of the attenuation resistor R2 is 22 - 33 ohms. R1 is used as a matching resistor, and its resistance value needs to be determined according to simulation, generally in the range of 22 - 33 ohms.

[0066] Exemplarily, the clock signal receiving module 300 is a Bluetooth chip. The clock signal generated by the driving chip 110 passes through the RC filtering circuit and the attenuation resistor in sequence to obtain a clock signal without interference; the clock signal without interference is transmitted to the Bluetooth chip, and the clock signal without interference is used to indicate the Bluetooth chip to synchronize and coordinate the communication between the Bluetooth devices connected thereto. The present application is unrestrictedly applicable to the field of automotive electronics. The principle of the present application is introduced below:

[0067] As Figure 3 shown in the first signal driving circuit, it includes a driving circuit (corresponding to the driving chip 110), a resistor R1, a PCB connection line 200, and a clock signal receiving chip connected in series in sequence. The driving circuit generates a clock signal, and this clock signal is output after passing through the resistor R1 and the PCB connection line 200. The output signal waveform is as Figure 4 shown. There is no ringing in this signal waveform, no back-hooking at the rising edge, and the rate of the rising edge is very fast, which is undoubtedly very good for SI. However, a fast rising edge indicates that it contains rich high-frequency components, as Figure 5 shown (in each spectrogram in the embodiment of the present application, the horizontal axis represents the frequency of the clock signal, and the vertical axis represents the amplitude of the clock signal).

[0068] To eliminate high-frequency components, such as Figure 6 As shown, an RC low-pass filter circuit (including resistor R1 and capacitor C1, corresponding to filter module 120) is added to the first signal driving circuit to obtain the second signal driving circuit. Exemplarily, the driving circuit is sequentially connected to resistor R1 and capacitor C1, and the other end of capacitor C1 is grounded; PCB connection line 200 is connected to the series node of resistor R1 and capacitor C1. The clock signal generated by the driving circuit is filtered by the RC low-pass filter circuit and then output through PCB connection line 200. The spectrogram of the filtered clock signal is as Figure 7 shown, where, according to Figure 7 the spectrogram, it can be seen that the high-frequency components have been significantly attenuated; the waveform of the filtered clock signal is as Figure 8 shown, but there is a very serious ringing phenomenon, and there is also a back-hook phenomenon at the rising edge, which is a very serious problem for the clock signal. This application finds that this back-hook phenomenon is because when the clock signal passes through the capacitor in the RC low-pass filter circuit, the capacitor (10 pF) is equivalent to a point of impedance discontinuity, causing reflection of the clock signal, thus forming ringing.

[0069] To take into account the impact of SI, this application finds that a resistor R2 is connected in series behind the RC filter circuit to obtain the clock signal driving circuit of this application, as Figure 9 shown, aiming to attenuate the reflected signal flowing to the backend caused by the capacitor through the resistor. The waveform diagram of the clock signal output by the clock signal driving circuit of the embodiment of this application is as Figure 10 shown, and there is no ringing anymore; the spectrogram of the clock signal output by the clock signal driving circuit of the embodiment of this application is as Figure 11 shown, and the high-frequency components have been further attenuated.

[0070] In this application, the EMC performance index is ensured to be qualified through the RC filter circuit, and on this basis, a series-connected resistor is added at the backend to ensure that the SI performance index meets the requirements, so as to achieve the simultaneous satisfaction of EMC and SI requirements.

[0071] Figure 12 Shows a schematic structural diagram of an electronic device according to an embodiment of this application. Exemplarily, the electronic device includes:

[0072] a clock signal generation module 100, a PCB connection line 200, and a clock signal reception module 300; the clock signal generation module 100 includes a driving chip 110, a filter module 120, and a signal attenuation module 130;

[0073] the driving chip 110 is sequentially connected to the clock signal reception module 300 through the filter module 120, the signal attenuation module 130, and the PCB connection line 200;

[0074] The driving chip 110 is used to send the clock signal generated by it to the filtering module 120 for filtering, and obtain a filtered clock signal, wherein the filtered clock signal carries a reflection interference signal; the filtering module 120 is used to transmit the filtered clock signal to the signal attenuation module 130; the signal attenuation module 130 is used to attenuate the reflection interference signal to obtain an interference-free clock signal and transmit it to the clock signal receiving module 300, and the interference-free clock signal is used to instruct the clock signal receiving module 300 to execute operations.

[0075] Further, the filtering module 120 in the electronic device includes a first resistor and a first capacitor;

[0076] One end of the first resistor is connected to the driving chip 110, and the other end is used to be grounded through the first capacitor; the other end of the first resistor is also connected to the signal attenuation module 130.

[0077] Further, the signal attenuation module 130 in the electronic device includes an attenuation resistor;

[0078] One end of the attenuation resistor is connected to the series node of the first resistor and the first capacitor, and the other end is connected to the PCB connection line 200.

[0079] It can be understood that the optional items in the above embodiments are equally applicable to this embodiment, so they will not be described again here.

[0080] As described above, the above are only the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered within the protection scope of the present application.

Claims

1. A clock signal driving circuit, characterized in that: include: Clock signal generation module and PCB connection line; The clock signal generating module includes a driving chip, a filtering module and a signal attenuation module; The driving chip is connected to the PCB connection line through the filtering module and the signal attenuation module in sequence; the PCB connection line is used to connect the clock signal receiving module; The driving chip is used to send the clock signal generated by it to the filtering module for filtering, and obtain a filtered clock signal, wherein the filtered clock signal carries a reflected interference signal; the filtering module is used to transmit the filtered clock signal to the signal attenuation module; The signal attenuation module is used to attenuate the reflected interference signal to obtain an interference-free clock signal and transmit it to the clock signal receiving module. The interference-free clock signal is used to instruct the clock signal receiving module to execute a service.

2. The clock signal driving circuit according to claim 1, characterized in that: The filtering module includes a first resistor and a first capacitor; One end of the first resistor is connected to the driving chip, and the other end is used to be grounded through the first capacitor; the other end of the first resistor is also connected to the signal attenuation module.

3. The clock signal driving circuit according to claim 2, characterized in that: The signal attenuation module includes an attenuation resistor; One end of the attenuation resistor is connected to a series node of the first resistor and the first capacitor, and the other end is connected to the PCB connection line.

4. The clock signal driving circuit according to claim 3, characterized in that: The value range of the attenuation resistance is 22Ω-33Ω.

5. The clock signal driving circuit according to claim 2, characterized in that: The value range of the first resistor is 22Ω-33Ω.

6. The clock signal driving circuit according to claim 2, characterized in that: The value of the first capacitor is determined according to a preset filtering frequency band and a first resistor.

7. The clock signal driving circuit according to claim 6, characterized in that: The value of the first capacitor is obtained by the following formula: C = 1 / (2×PI×R×f) Among them, C is the capacitance value of the first capacitor, R is the resistance value of the first resistor, f is the preset filtering frequency band, and PI is pi.

8. An electronic device, characterized in that: include: A clock signal generating module, a PCB connecting line and a clock signal receiving module; the clock signal generating module includes a driving chip, a filtering module and a signal attenuation module; The driving chip is connected to the clock signal receiving module through the filtering module, the signal attenuation module and the PCB connecting line in sequence; The driving chip is used to send the clock signal generated by it to the filtering module for filtering, and obtain a filtered clock signal, wherein the filtered clock signal carries a reflected interference signal; the filtering module is used to transmit the filtered clock signal to the signal attenuation module; The signal attenuation module is used to attenuate the reflected interference signal to obtain an interference-free clock signal and transmit it to the clock signal receiving module. The interference-free clock signal is used to instruct the clock signal receiving module to execute a service.

9. The electronic device according to claim 8, characterized in that: The filtering module includes a first resistor and a first capacitor; One end of the first resistor is connected to the driving chip, and the other end is used to be grounded through the first capacitor; the other end of the first resistor is also connected to the signal attenuation module.

10. The electronic device according to claim 9, characterized in that: The signal attenuation module includes an attenuation resistor; One end of the attenuation resistor is connected to a series node of the first resistor and the first capacitor, and the other end is connected to the PCB connection line.

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