SiC VDMOSFET structure with thermal stability

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with thermal stability, which comprises a SiC VDMOSFET structure consisting of a plurality of VDMOS cells, each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; wherein the diffusion layer comprises a first diffusion layer, a second diffusion layer and a third diffusion layer by injecting phosphorus impurities with different concentrations; the N-well layer comprises a first lightly doped N-well layer, a second lightly doped N-well layer, a third lightly doped N-well layer, a heavily doped N-well layer and a fourth lightly doped N-well layer. According to the utility model, the stability of the conduction current of the MOS device can be improved by using the P and N well layer materials with larger volumes, and the design that part of the P and N layer materials protrude and submerge the grid electrode can reduce the interference of the grid electrode electric field on charges in the P and N layers, and improve the thermal stability of the MOS device at the same time.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a SiC VDMOSFET structure with thermal stability. Background Art

[0002] The "floating error" of semiconductor devices generally refers to the error caused by factors such as environmental changes, internal device structure, temperature, voltage, etc. during device operation or testing. These errors may cause the measurement results to deviate from the true value, affecting device performance evaluation and applications. To reduce the floating error, usually some measures need to be taken, such as using a stable power supply, controlling environmental conditions, calibrating measurement equipment, etc.

[0003] The existing patent discloses a method for manufacturing a VDMOS device to reduce floating error (publication number CN110176395A), which includes the following steps: A. Providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, forming a gate oxide layer on the N-type epitaxial layer, and forming a polycrystalline gate on the gate oxide layer; B. Etching the polycrystalline gate and etching part of the gate oxide layer; C. Doping ions for body region implantation at a set implantation angle, and dividing it into 4 times, each time implanting 1 / 4 of the body region dose, and after each implantation, rotating the silicon wafer 90 degrees clockwise on the horizontal plane and then performing the next implantation; D. Performing source region self-aligned implantation; E. Performing one-time drive-in diffusion of the body region and the source region; F. Depositing a dielectric layer and completing hole etching. In the technology disclosed in this patent, the prepared VDMOS device will have its own heat accumulation and cannot be released during use, resulting in current fluctuations in the MOS device. And the P-well layer of the prepared VDMOS device will also have parasitic charges due to the intervention of the gate electric field, thus resulting in the phenomenon that the accumulated parasitic charges interfere with the free movement of charges in the diffusion layer. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a SiC VDMOSFET structure with thermal stability, solving the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a SiC VDMOSFET structure with thermal stability includes a SiC VDMOSFET structure composed of several VDMOS cells, and the VDMOS cell includes a drain, a metal source, a gate, and a semiconductor epitaxial layer;

[0006] The semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer, and an N-well layer;

[0007] Among them, the diffusion layer is formed by injecting phosphorus element impurities with different concentrations to form a first diffusion layer, a second diffusion layer, and a third diffusion layer;

[0008] The P-well layer includes a first heavily doped P-well layer, a second heavily doped P-well layer, a third heavily doped P-well layer, and a first lightly doped P-well layer;

[0009] The N-well layer includes a first lightly doped N-well layer, a second lightly doped N-well layer, a third lightly doped N-well layer, a heavily doped N-well layer, and a fourth lightly doped N-well layer;

[0010] When a positive gate voltage is applied to the gate, a reverse depletion layer is formed in the JFET region between the gate and the substrate layer to prevent the transmission of free carriers.

[0011] Furthermore, when the gate is connected to the gate voltage, the charges inside the second lightly doped P-well layer move closer to the gate under the intervention of the gate electric field to form a charge channel, and the diffusion layer and the N-well layer are conducted through the charge channel.

[0012] Furthermore, the N-well layer and the diffusion layer are separated by the P-well layer, and only the first lightly doped N-well layer, the second lightly doped N-well layer, and the third lightly doped N-well layer in the N-well layer are ohmically shorted to the metal source.

[0013] Furthermore, the first heavily doped P-well layer and the second heavily doped P-well layer between adjacent VDMOS cells are integrated, and only the first heavily doped P-well layer in the P-well layer is ohmically shorted to the metal source.

[0014] Furthermore, the N-well layers between adjacent VDMOS cells are separated by the first heavily doped P-well layer and the second heavily doped P-well layer.

[0015] Furthermore, the third heavily doped P-well layer and the first lightly doped P-well layer are both in an 'L' shape, and the third heavily doped P-well layer and the first lightly doped P-well layer are superimposed inside and outside to suppress the gate electric field from passing through the P-well layer.

[0016] Furthermore, the third heavily doped P-well layer is doped with high-concentration boron ions by ion implantation.

[0017] Furthermore, the first lightly doped N-well layer (13), the second lightly doped N-well layer (14), and the third lightly doped N-well layer (15) are doped with low-concentration phosphorus ions by ion implantation.

[0018] Furthermore, the first diffusion layer (6), the third diffusion layer (8), and the second diffusion layer (7) are doped with low-concentration phosphorus ions by ion implantation.

[0019] Furthermore, a gate oxide layer is deposited between the surface of the gate, the metal source, and the semiconductor epitaxial layer.

[0020] The beneficial effects of the SiC VDMOSFET structure with thermal stability of the present utility model are as follows:

[0021] 1. By using P and N well layer materials with larger volumes, the present utility model can improve the stability of the on-current of MOS devices. Moreover, the design of protruding part of the P and N layer materials and covering the gate can reduce the interference of the gate electric field on the charges in the P and N layers, and at the same time improve the thermal stability of the MOS device.

[0022] 2. By injecting phosphorus elements with different concentrations into the diffusion layer to form a multi-level design, and the doping concentration increases gradually from the drain to the gate, this can improve the pressure-bearing capacity between the drain and the gate, and at the same time reduce the on-resistance after the formation of the charge channel. Description of the Drawings

[0023] The following further elaborates on the present utility model in detail in conjunction with the drawings and specific implementation methods.

[0024] Figure 1 It is the structural schematic diagram of the VDMOS device in the present utility model;

[0025] Figure 2 It is the structural schematic diagram of a single VDMOS cell in the present utility model.

[0026] In the figure: 1. Drain; 2. Metal source; 3. Gate oxide layer; 4. Gate; 5. Substrate layer; 6. First diffusion layer; 7. Second diffusion layer; 8. Third diffusion layer; 9. First heavily doped P well layer; 10. Second heavily doped P well layer; 11. Third heavily doped P well layer; 12. First lightly doped P well layer; 13. First lightly doped N well layer; 14. Second lightly doped N well layer; 15. Third lightly doped N well layer; 16. Heavily doped N well layer; 17. Fourth lightly doped N well layer; 18. Second lightly doped P well layer. Specific Embodiments

[0027] The present utility model will be described in detail below with reference to the drawings and in conjunction with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0028] Such as Figure 1-2As shown, according to one aspect of the present utility model, a SiCVDMOSFET structure with thermal stability is provided, including a SiC VDMOSFET structure composed of a plurality of VDMOS cells. The VDMOS cell includes a drain 1, a metal source 2, a gate 4, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes a substrate layer 5, a diffusion layer, a P-well layer, and an N-well layer. A gate oxide layer 3 is deposited between the surface of the gate 4, the metal source 2, and the semiconductor epitaxial layer. When a gate voltage is applied to the gate 4, a charge channel will be formed inside the P-well layer, and the charge channel will connect the diffusion layer and the N-well layer. Among them, the diffusion layer is ohmically connected to the drain 1, and the N-well layer is ohmically connected to the metal source 2 (as Figure 1 shown), so that a loop is formed between the drain 1 and the metal source 2.

[0029] Among them, the diffusion layer is formed by injecting phosphorus element impurities with different concentrations to form a diffusion layer one 6, a diffusion layer two 7, and a diffusion layer three 8. The P-well layer includes a heavily doped P-well layer one 9, a heavily doped P-well layer two 10, a heavily doped P-well layer three 11, and a lightly doped P-well layer one 1. The N-well layer includes a lightly doped N-well layer one 13, a lightly doped N-well layer two 14, a lightly doped N-well layer three 15, a heavily doped N-well layer 16, and a lightly doped N-well layer four 17 (as Figure 2 shown). By using a larger volume of P and N well layer materials, the stability of the on-current of the VDMOS device can be improved, and the design of protruding and covering part of the P and N layer materials over the gate 4 can reduce the interference of the gate electric field on the charges in the P and N layers.

[0030] In this embodiment, the P-well layer is formed into different levels by injecting phosphorus elements with different concentrations, and the N-well layer and the diffusion layer are both formed into different levels by injecting boron elements with different concentrations.

[0031] The doping concentration of the heavily doped P-well layer three 11 is 2 - 3.7×10 18 mol / cm 3 ;

[0032] The doping concentration of the lightly doped N-well layer one 13 is 2 - 4×10 16 mol / cm 3 ;

[0033] The doping concentration of the lightly doped N-well layer two 14 is 3 - 7×10 17 mol / cm 3 ;

[0034] The doping concentration of the lightly doped N-well layer three 15 is 5 - 8×10 17 mol / cm 3 ;

[0035] The doping concentrations of the diffusion layer one 6 and the diffusion layer three 8 are both 3 - 5×10 17 mol / cm3 ;

[0036] The doping concentration of the second diffusion layer 7 is 6.4 - 9×10 16 mol / cm 3 .

[0037] In this embodiment, when a positive gate voltage is applied to the gate 4, a reverse depletion layer is formed in the JFET region between the gate 4 and the substrate layer 5 to prevent the transmission of free carriers. When the gate 4 is connected to the gate voltage, the charges inside the lightly doped P-well layer two 18 approach the gate 4 under the intervention of the gate electric field and form a charge channel. The diffusion layer and the N-well layer are conducted through the charge channel (as shown in Figure 2 ). When a positive gate voltage is applied, a reverse depletion layer is formed between the gate 4 and the substrate layer 5, thereby reducing the charge density in the channel. And when the reverse depletion layer expands to a certain extent, the channel region is truncated and the current cannot pass, thus reaching the cut-off state. By adjusting the gate voltage in this way, the expansion degree of the reverse depletion layer can be controlled, and further the charge density and the magnitude of the current in the channel can be controlled, realizing the current control of the MOSFET device.

[0038] In this embodiment, the N-well layer is blocked by the P-well layer between the N-well layer and the diffusion layer, and only the lightly doped N-well layer one 13, the lightly doped N-well layer two 14, and the lightly doped N-well layer three 15 in the N-well layer are ohmically short-circuited to the metal source 2. The heavily doped P-well layer one 9 and the heavily doped P-well layer two 10 between adjacent VDMOS cells are of the same body, and only the heavily doped P-well layer one 9 in the P-well layer is ohmically short-circuited to the metal source 2. By injecting different concentrations of phosphorus atoms into the diffusion layer, a multi-level design is formed, and the doping concentration increases gradually from the drain 1 to the gate 4. In this way, the pressure-bearing capacity between the drain and the gate can be improved, and at the same time, the on-resistance after the formation of the charge channel can be reduced.

[0039] In this embodiment, the N-well layer between adjacent VDMOS cells is blocked by the heavily doped P-well layer one 9 and the heavily doped P-well layer two 10. The heavily doped P-well layer three 11 and the lightly doped P-well layer one 12 are both in an 'L' shape. The heavily doped P-well layer three 11 and the lightly doped P-well layer one 12 are stacked inside and outside to inhibit the gate electric field from passing through the P-well layer. Dividing the P-well layer into a multi-level design can reduce the random movement of charges inside the P-well layer, thereby avoiding the phenomenon of parasitic capacitance in this VDMOS device.

[0040] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.

Claims

1. A thermally stable SiC VDMOSFET structure, characterized in that: A SiC VDMOSFET structure is provided which is composed of a plurality of VDMOS cells, wherein the VDMOS cells include a drain (1), a metal source (2), a gate (4) and a semiconductor epitaxial layer; The semiconductor epitaxial layer comprises a substrate layer (5), a diffusion layer, a P-well layer and an N-well layer; The diffusion layer is formed by injecting phosphorus impurities of different concentrations to include a diffusion layer 1 (6), a diffusion layer 2 (7) and a diffusion layer 3 (8); The P-well layer includes a heavily doped P-well layer 1 (9), a heavily doped P-well layer 2 (10), a heavily doped P-well layer 3 (11) and a lightly doped P-well layer 1 (12); The N-well layer includes a lightly doped N-well layer 1 (13), a lightly doped N-well layer 2 (14), a lightly doped N-well layer 3 (15), a heavily doped N-well layer (16) and a lightly doped N-well layer 4 (17); When a forward gate voltage is applied to the gate (4), a reverse depletion layer is formed in the JFET region between the gate (4) and the substrate layer (5) to prevent the transmission of free carriers.

2. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: When the gate (4) is connected to a gate voltage state, the internal charges of the lightly doped P-well layer 2 (18) move toward the gate (4) under the intervention of the gate electric field and form a charge channel, and the diffusion layer and the N-well layer are connected through the charge channel.

3. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: The N-well layer and the diffusion layer are blocked by a P-well layer, and only the lightly doped N-well layer 1 (13), the lightly doped N-well layer 2 (14) and the lightly doped N-well layer 3 (15) in the N-well layer are ohmically short-circuited with the metal source electrode (2).

4. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: The heavily doped P-well layer 1 (9) and the heavily doped P-well layer 2 (10) between adjacent VDMOS cells are integrated as a whole, wherein only the heavily doped P-well layer 1 (9) in the P-well layer is ohmically short-circuited with the metal source electrode (2).

5. The SiC VDMOSFET structure with thermal stability according to claim 4, characterized in that: The N-well layer between adjacent VDMOS cells is blocked by a heavily doped P-well layer 1 (9) and a heavily doped P-well layer 2 (10).

6. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: The heavily doped P well layer three (11) and the lightly doped P well layer one (12) are both formed in an 'L' shape, wherein the heavily doped P well layer three (11) and the lightly doped P well layer one (12) are overlapped inside and outside to suppress the gate electric field from passing through the P well layer.

7. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: The heavily doped P-well layer three (11) is doped with high concentration of boron ions by ion implantation.

8. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: The lightly doped N-well layer 1 (13), the lightly doped N-well layer 2 (14) and the lightly doped N-well layer 3 (15) are doped with low concentration of phosphorus ions by ion implantation.

9. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: The diffusion layer 1 (6), the diffusion layer 3 (8) and the diffusion layer 2 (7) are doped with low concentration phosphorus ions by ion implantation.

10. The SiC VDMOSFET structure with thermal stability according to claim 1, characterized in that: A gate oxide layer (3) is deposited between the surface of the gate electrode (4), the metal source electrode (2) and the semiconductor epitaxial layer.

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