Pin-free multi-core-group ceramic dielectric capacitor

Abstract

The utility model discloses a pin-free multi-core-group ceramic dielectric capacitor, which belongs to the field of capacitor structures, and comprises a support assembly, the support assembly comprises a first support and a second support which are symmetrically arranged, and a capacitor chip assembly is arranged between the first support and the second support; the capacitor chip assembly comprises a first end electrode part and a second end electrode part which are arranged at the end part of the capacitor chip assembly; the first end electrode part is connected with the first bracket, and the second end electrode part is connected with the second bracket; the first end electrode part and the second end electrode part are respectively provided with a solder mask. According to the utility model, the capacitor chip assembly is arranged on the support assembly, and the solder mask layer is arranged on the terminal electrode part, so that the capacitor is suitable for the condition of no pin or lower pin, and the purposes of increasing the space surplus of the height of the capacitor and avoiding cracks beside the terminal electrode caused by tin accumulation at the SMT welding part are achieved.

Description

Technical Field

[0001] The utility model relates to the field of capacitor structures, and particularly relates to a leadless multi-core ceramic capacitor. Background Art

[0002] With the rapid development of electronic technologies in aerospace, aviation, military, automotive, etc., integration has become the main development direction. As one of the three major components in a circuit, the miniaturization and flexibility of capacitors have become one of the main considerations when users select products.

[0003] Multi-core ceramic capacitors are mainly used in circuits for output / input filtering of medium-high frequency high-current switching power supplies, power bus filtering, DC-DC converters, etc. The main feature of multi-core products is that multiple individual chip ceramic capacitors (MLCCs) are connected in parallel. In addition to the characteristics of the original chip ceramic capacitors themselves, they can obtain a larger capacitance, smaller ESR and ESL, and effectively utilize the height space.

[0004] During the SMT assembly process of multi-core ceramic capacitors, a special outward-extending pin structure is generally designed on the lead frame body, so that in SMT soldering, it can be used as a dedicated soldering connection area with the circuit board (as Figure 1 shown, the connection relationship refers to components a, b, c, d in the figure).

[0005] However, the existing multi-core ceramic capacitors are limited by the characteristics of the raw materials of the chip ceramic capacitors, and it is very difficult to further reduce their thickness dimensions. Therefore, the final height of the multi-core ceramic capacitors is relatively high, which further leads to a relatively high center of gravity, making the capacitors have weak points in terms of anti-board-level vibration stress. During the production process, the positions of the pins on both sides of the lead frame need to be ensured to be flat. However, due to the accuracy of the tooling fixture, the processing accuracy of the lead frame, and the shrinkage error of the chip ceramic capacitor, it is very difficult to ensure the coplanarity of the pins on both sides, which further reduces the production qualification rate, increases the production cost, and reduces the market competitiveness. The DC-DC power module needs to work in an inert gas environment to ensure insulation, anti-oxidation, surface discharge, etc., so it is basically installed in a stainless steel shell. To ensure the product weight, the height of the shell is generally as low as possible. The height of the capacitors within the existing standards has been determined and cannot meet the requirements of users, and they cannot be used in DC-DC power modules with a specific height.

[0006] The soldering part of the lead frame pins is the SMT soldering part for users. If the pin height is relatively low, it may cause the solder of the user to climb up, resulting in the phenomenon of tin accumulation inside the pins (as Figure 2 shown by component f), resulting in a typical 45° crack risk at the position of the end electrode protection sheet of the chip ceramic capacitor (as Figure 2 shown by component e), further reducing the quality reliability.

[0007] In view of this, the present application is hereby proposed. Content of the Utility Model

[0008] The purpose of the present utility model is to provide a leadless multi-core ceramic capacitor. The capacitor chip assembly is arranged on the bracket assembly, and a solder mask layer is arranged on the end electrode part to solve the problem of solder accumulation at the SMT welding part and cracks appearing beside the end electrode in the prior art.

[0009] The embodiments of the present utility model are realized through the following technical solutions: The embodiments of the present utility model provide a leadless multi-core ceramic capacitor, including a bracket assembly. The bracket assembly includes a first bracket and a second bracket which are symmetrically arranged, and a capacitor chip assembly is arranged between the first bracket and the second bracket;

[0010] The capacitor chip assembly includes a first end electrode part and a second end electrode part arranged at its end;

[0011] The first end electrode part is connected to the first bracket, and the second end electrode part is connected to the second bracket;

[0012] Solder mask layers are arranged on both the first end electrode part and the second end electrode part.

[0013] Preferably, both the first bracket and the second bracket are sheet-shaped or hollow-shaped.

[0014] Preferably, the first end electrode part is soldered to the first bracket through solder, and the second end electrode part is soldered to the second bracket through solder.

[0015] Preferably, the capacitor chip assembly includes a plurality of chip ceramic dielectric capacitor chips. Each chip ceramic dielectric capacitor chip includes an end electrode unit. Adjacent two chip ceramic dielectric capacitor chips are stacked staggeredly, and the end electrode units on the same side are combined into the first end electrode part or the second end electrode part.

[0016] Preferably, the stacking method is horizontal up-and-down stacking.

[0017] Preferably, the stacking method is vertical side-by-side stacking.

[0018] Preferably, the capacitor chip assembly is flush with the end face of the bracket assembly, and the solder mask layer protrudes outward from the bracket assembly.

[0019] Preferably, except for the connection surfaces of the first end electrode part and the second end electrode part with the bracket assembly, solder mask layers are arranged on the side surfaces of the first end electrode part and the second end electrode part.

[0020] Preferably, the solder mask layer is disposed on the side end portions of the first end electrode portion and the second end electrode portion.

[0021] Preferably, the solder mask layer is made of solder mask ink.

[0022] Compared with the prior art, the embodiment of the present invention has the following advantages and beneficial effects:

[0023] 1. A leadless multi-core ceramic capacitor provided by the embodiment of the present invention sets the bracket assembly as a symmetric first bracket and a second bracket, and then sets the capacitor chip assembly between the first bracket and the second bracket. Since both ends of the capacitor chip assembly have a first electrode portion and a second electrode portion respectively, the first electrode portion can be connected to the first bracket, and the second electrode portion can be connected to the second bracket to form a stable bracket support structure. The connections between the end electrode portions and the bracket assembly are all electrical connections, which is convenient for the subsequent connection and operation of the capacitor with the external circuit.

[0024] In the embodiment of the present invention, a solder mask layer is provided on the first electrode portion and the second electrode portion, which can prevent the solder from extending and accumulating towards the porcelain body during the subsequent soldering process of the capacitor to the circuit board. A solder mask layer is provided on its exposed surface to achieve the purpose of isolating the solder, thereby avoiding cracks in the porcelain body and affecting the quality of the capacitor.

[0025] 2. Connecting the first end electrode portion and the first bracket, and the second end electrode portion and the second bracket by soldering can not only ensure the stability of the connection, but also ensure good electrical conductivity.

[0026] Generally speaking, a leadless multi-core ceramic capacitor provided by the embodiment of the present invention sets the capacitor chip assembly on the bracket assembly and provides a solder mask layer on the end electrode portion, which is applicable to the situation of leadless or low pins, achieving the purpose of increasing the height space margin of the capacitor and avoiding cracks beside the end electrodes caused by solder accumulation at the SMT soldering part. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 is a schematic diagram of the installation structure of a capacitor in the prior art;

[0029] Figure 2 is a schematic diagram of cracks occurring during the installation process of a capacitor in the prior art;

[0030] Figure 3 Schematic diagram of the capacitor structure provided by the embodiment of the present utility model;

[0031] Figure 4 Side view of the leadless multi-core ceramic capacitor provided by the embodiment of the present utility model;

[0032] Figure 5 Structural diagram of horizontal up-and-down stacking of multiple chip ceramic dielectric capacitor chips in the capacitor chip assembly;

[0033] Figure 6 Structural diagram of vertical side-by-side stacking of multiple chip ceramic dielectric capacitor chips in the capacitor chip assembly.

[0034] Labels in the drawings and corresponding component names:

[0035] a - lead, b - circuit board, c - lead support, d - chip ceramic dielectric capacitor;

[0036] e - crack, f - solder stacking position;

[0037] 1 - first support, 2 - second support, 4 - second end electrode part, 5 - inner electrode part, 6 - solder mask layer, 7 - chip ceramic dielectric capacitor chip, 8 - solder layer. Detailed implementation manners

[0038] To make the objectives, technical solutions and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are some but not all of the embodiments of the present utility model. Usually, the components of the embodiments of the present utility model described and shown in the accompanying drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present utility model provided in the accompanying drawings is not intended to limit the scope of the claimed present utility model, but merely represents the selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the scope of protection of the present utility model.

[0040] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0041] In the description of the present utility model, it should be noted that the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0042] Embodiment

[0043] As Figure 3-4 As shown, the embodiment of the present utility model provides a leadless multi-core ceramic capacitor, which includes a bracket assembly as a mechanical support. The bracket assembly includes a first bracket 1 and a second bracket 2 symmetrically arranged. A capacitor chip assembly is arranged between the first bracket 1 and the second bracket 2. That is, the first bracket 1 and the second bracket 2 are isolated from each other, and a capacitor chip assembly is arranged in the isolation space. The capacitor chip assembly includes an inner electrode portion 5 arranged inside and a first end electrode portion and a second end electrode portion 4 arranged at both ends. That is, the first end electrode portion and the second end electrode portion 4 are arranged at both ends of the capacitor chip assembly to form two external connection points of the capacitor. This structure allows current to flow into and out of the capacitor to realize its charging and discharging function.

[0044] Both the first end electrode portion and the second end electrode portion 4 include an exposed surface and a connection surface. The connection surface of the first end electrode portion is connected to the first bracket 1, and the connection surface of the second end electrode portion 4 is connected to the second bracket 2 to form a stable mechanical connection and electrical connection. Solder mask layers are arranged on the exposed surfaces of the first end electrode portion and the second end electrode portion 4. The setting of the solder mask layer can block the solder accumulation components formed during the installation process and avoid cracks in the capacitor chip assembly. With the structure provided by the embodiment of the present utility model, during the SMT soldering process, there will be no phenomenon of low pins or no pins causing solder to overflow and tin piling up inside the bracket assembly, thus avoiding the risk of typical 45° cracks at the position of the end electrode protection sheet of the chip ceramic capacitor, improving the quality of the capacitor. Since the capacitor provided by the embodiment of the present utility model is applicable to the situation of leadless or low pin structure, during the actual operation, the pins can be appropriately reduced or removed to lower the center of gravity of the entire capacitor structure, increasing the height space allowance of the capacitor and improving the anti-vibration ability of the product after soldering on the board.

[0045] To save the material of the solder mask layer, the solder mask layer can be only provided at the ends of the first end electrode portion and the second end electrode portion 4, so that the area to be protected can be accurately covered, effectively preventing unnecessary accumulation of solder paste in these areas, and at the same time avoiding excessive waste of raw materials. It should be noted that the specific structures of the first bracket 1 and the second bracket 2 are not limited here, and they can both be in the shape of a sheet or a hollow shape, etc. The sheet-shaped or hollow-shaped bracket helps to reduce the volume of the capacitor, making the capacitor more compact. In other embodiments, as long as the purpose of sufficient mechanical support stability can be achieved. The embodiment of the present invention preferably adopts a hollow structure. The hollow structure can reduce the weight of the capacitor by reducing the use of materials, and at the same time can provide a better heat dissipation path, which helps to transfer the heat generated during the operation of the capacitor to the surrounding environment.

[0046] As a preferred embodiment of the present invention, the first end electrode portion is welded to the first bracket 1, and the second end electrode portion 4 is welded to the second bracket 2, and solder layers 8 are formed on the welding end faces, forming stable electrical and mechanical connection points. The solder layer 8 is usually formed on the end electrode and the bracket by melting and wetting during the welding process, ensuring that the electrical connection between the end electrode and the bracket is both stable and reliable. Of course, in other embodiments, connection methods such as conductive adhesive bonding can also be used, as long as the purpose of sufficient mechanical connection stability and electrical connection stability can be achieved.

[0047] To ensure the flat installation of the capacitor on the circuit board, the capacitor chip assembly can be arranged flush with the end face of the bracket assembly, and the solder mask layer protrudes outward from the bracket assembly, improving the accuracy and reliability of the connection. The solder mask layer is set to protrude outward from the bracket assembly, which can more effectively cover and protect the edge of the capacitor chip assembly, preventing unnecessary accumulation of solder paste. The design of the flush end face and the protruding solder mask layer is suitable for the automated SMT mounting process, improving production efficiency and reducing labor costs.

[0048] In the embodiment of the present invention, the solder mask layer is made of solder mask ink, and the solder mask ink is composed of resin, pigment, filler and additive. The resin is the matrix of the ink, the pigment provides color and certain special functions, the filler is used to improve the physical properties of the ink, and the additive is used to adjust the properties such as the viscosity and drying speed of the ink. It has good viscosity and thixotropy, which enables the ink to adhere well to the circuit board during the printing process and at the same time maintain an appropriate viscosity when stationary, facilitating operation. Of course, in other embodiments, it is not limited to solder mask ink, as long as the purpose of sufficient isolation stability can be achieved.

[0049] Exemplarily, the capacitor chip assembly includes a plurality of stacked chip ceramic dielectric capacitor chips 7. A first end electrode portion and a second end electrode portion 4 are respectively provided at both ends of the capacitor chip assembly. A plurality of interleaved inner electrodes are provided between the first end electrode portion and the second end electrode portion 4 to form an inner electrode portion 5. The end electrodes of the multi-layer chip ceramic dielectric capacitor chips 7 on the same side form the end electrode portion of the capacitor chip group. Side soldermasks are coated on both sides of the edges around the capacitor chip group. A solder layer 8 is provided between the first end electrode portion and the first bracket 1 and between the second end electrode portion 4 and the second bracket 2. The solder layer 8 welds and connects the end electrode portion to the bracket assembly; the soldermask uses soldermask ink. In the capacitor of the embodiment of the present invention, the chip ceramic dielectric capacitor chips 7 are connected together by the bracket assembly to form a chip group, and then the soldermask is coated around the end electrode portion. The bracket assembly has no fixed pins, increasing the height space margin, reducing the product center of gravity at the same time, and improving the anti-vibration test ability of the product after soldering on the board. And the side soldermask ink (or other soldermask layer) on the end electrode side will block the solder paste accumulation caused by surface mount installation, improving the product application reliability and application range.

[0050] As Figure 5-6 shown, the stacking method of the plurality of chip ceramic dielectric capacitor chips 7 can be horizontal up-and-down stacking or vertical side-by-side stacking, which is not limited here. Similarly, the stacking number of the chip ceramic dielectric capacitor chips 7 is not limited here either, and can be specifically set according to actual needs. Since each chip ceramic dielectric capacitor chip 7 is in series, the more the stacking number, the larger the capacitance of the capacitor. The embodiment of the present invention is preferably two or more. Since the edge size of the bracket assembly is basically the same as that of the capacitor chip assembly, surface mount soldering can be performed on the other four surfaces except for the two connection end faces of the bracket assembly. During the assembly process, the soldermask can be coated after the capacitor chip assembly and the bracket assembly are welded together, or the soldermask can be coated on the side surfaces around the capacitor chip assembly and then assembled and welded with the bracket assembly.

[0051] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. It should be noted that the structures or components illustrated in the drawings are not necessarily drawn to scale, and the present invention omits the description of well-known components and processing technologies and processes to avoid unnecessarily limiting the present invention.

Claims

1. A leadless multi-core ceramic capacitor, comprising a bracket assembly, wherein the bracket assembly comprises a first bracket (1) and a second bracket (2) arranged symmetrically, characterized in that: A capacitor chip assembly is arranged between the first bracket (1) and the second bracket (2); The capacitor chip assembly comprises a first end electrode portion and a second end electrode portion (4) arranged at the end thereof; The first end electrode portion is connected to the first bracket (1), and the second end electrode portion (4) is connected to the second bracket (2); A solder resist layer (6) is provided on both the first end electrode portion and the second end electrode portion (4).

2. The leadless multi-core ceramic capacitor according to claim 1, characterized in that: The first bracket (1) and the second bracket (2) are both in sheet or hollow shape.

3. The leadless multi-core ceramic capacitor according to claim 2, characterized in that: The first end electrode portion and the first bracket (1) are welded by tin material, and the second end electrode portion (4) and the second bracket (2) are welded by tin material.

4. The leadless multi-core ceramic capacitor according to claim 1, characterized in that: The capacitor chip assembly comprises a plurality of chip-type ceramic dielectric capacitor chips (7), each of which comprises an end electrode unit, two adjacent chip-type ceramic dielectric capacitor chips (7) are stacked in an alternating manner, and the end electrode units on the same side are combined into a first end electrode portion or a second end electrode portion (4).

5. The leadless multi-core ceramic capacitor according to claim 4, characterized in that: The stacking method is horizontal up and down stacking.

6. The leadless multi-core ceramic capacitor according to claim 4, characterized in that: The stacking method is vertical side-by-side stacking.

7. The leadless multi-core ceramic capacitor according to claim 1, characterized in that: The capacitor chip component is flush with the end surface of the bracket component, and the solder resist layer (6) protrudes outward from the bracket component.

8. The leadless multi-core ceramic capacitor according to claim 1, characterized in that: Except for the connection surfaces of the first end electrode portion and the second end electrode portion (4) and the bracket assembly, solder resist layers (6) are provided on the side surfaces of the first end electrode portion and the second end electrode portion (4).

9. The leadless multi-core ceramic capacitor according to claim 8, characterized in that: The solder resist layer (6) is arranged at the side end portions of the first end electrode portion and the second end electrode portion (4).

10. The leadless multi-core ceramic capacitor according to claim 9, characterized in that: The solder resist layer (6) is made of solder resist ink.

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