VDMOSFET device with stable charge conduction

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device with stable charge conduction, which comprises a plurality of mutually parallel MOS cells, each MOS cell comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; the P well layer comprises a lightly doped P well I, a heavily doped P well I, a heavily doped P well II and a lightly doped P well II; the N-well layer comprises a lightly doped N-well layer I, a lightly doped N-well layer II and a heavily doped N-well layer I; a heavily doped N well layer II is formed in the diffusion layer through ion implantation; and the lower layer surface of the MOS cell is in ohmic connection with a drain electrode. According to the VDMOSFET device provided by the utility model, the highly doped P well and the lowly doped P well are arranged between the adjacent MOS cells, and the P well layer can inhibit charges from diffusing into the adjacent MOS cells, so that the charge stability of the VDMOSFET device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a VDMOSFET device with stable charge conduction. Background Art

[0002] The VDMOSFET is a power device with relatively fast development at present. It has unique characteristics such as high input impedance, low drive power, high switching speed, superior frequency characteristics, low noise, good thermal stability, radiation resistance, and simple manufacturing process; it is widely used in various fields such as AC drives, frequency conversion power supplies, and switched-mode power supplies, and has achieved good results.

[0003] A prior patent discloses a VDMOSFET device with stable charge conduction (publication number CN111755511A). This VDMOSFET includes a first-conductivity-type heavily doped substrate, a first-conductivity-type lightly doped drift layer, a second-conductivity-type lightly doped well region, a second-conductivity-type heavily doped contact region, a first-conductivity-type heavily doped source region, a second-conductivity-type lightly doped region, a first-conductivity-type lightly doped region, a gate oxide layer, a gate, a source, and a drain. In the technology disclosed in this patent, the hole density of the charge channel formed by the VDMOSFET device is only affected by the gate voltage. In this way, almost no charge channel is formed when a very small voltage is applied to the gate, which makes this VDMOSFET device not suitable for weak voltage circuits. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a VDMOSFET device with stable charge conduction, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a VDMOSFET device with stable charge conduction includes a plurality of MOS cells arranged in parallel;

[0006] The MOS cell includes a substrate layer, a diffusion layer, a P-well layer, and an N-well layer;

[0007] The P-well layer includes a lightly doped P-well 1, a heavily doped P-well 1, a heavily doped P-well 2, and a lightly doped P-well 2;

[0008] The N-well layer includes a lightly doped N-well layer 1, a lightly doped N-well layer 2, and a heavily doped N-well layer 1;

[0009] A heavily doped N-well layer 2 is formed by ion implantation inside the diffusion layer;

[0010] The lower surface of the MOS cell is ohm-connected to the drain, and the upper surface of the MOS cell is ohm-connected to the metal source;

[0011] The upper surface of a single MOS cell is etched with grooves, and a gate is deposited inside the grooves.

[0012] When a voltage is applied to the gate, a JFET region is formed in the diffusion layer, and the conductivity of the JFET region is adjusted by controlling the voltage on the gate.

[0013] Furthermore, the cross-sections of the lightly doped P-well 1 and the lightly doped P-well 2 are both in an 'L' shape, and the lightly doped P-well 1 and the lightly doped P-well 2 are in an interlocking state.

[0014] Furthermore, the heavily doped P-well 2 and the heavily doped P-well 1 are respectively located on the upper and lower sides of the lightly doped P-well 2, and the heavily doped P-well 1 and the heavily doped P-well 2 are integrated between adjacent MOS cells.

[0015] Furthermore, the heavily doped P-well 1 is in a downward convex state, and the heavily doped P-well 1 inhibits the diffusion of charges in the diffusion layer into adjacent MOS cells.

[0016] Furthermore, the cross-section of the heavily doped N-well layer 1 is in an 'L' shape, and the lightly doped N-well layer 1 and the lightly doped N-well layer 2 are respectively located on both sides of the heavily doped N-well layer 1.

[0017] Furthermore, the lightly doped N-well layer 1 and the lightly doped N-well layer 2 are ion-implanted with low-concentration phosphorus ions; the heavily doped N-well layer 1 and the heavily doped N-well layer 2 are ion-implanted with high-concentration phosphorus ions; the lightly doped P-well 1 and the heavily doped P-well 1 are ion-implanted with low-concentration boron ions; the heavily doped P-well 2 and the lightly doped P-well 2 are ion-implanted with high-concentration boron ions.

[0018] Furthermore, when an electric field is applied between the gate and the drain, a charge channel is formed inside the lightly doped P-well 1.

[0019] The beneficial effects of the VDMOSFET device with stable charge conduction of the present utility model are as follows:

[0020] 1. By implanting a highly doped N-well layer at the bottom of the U-groove in the present utility model, the resistance of the JFET region is reduced, and the path resistance between the source and the drain is smaller.

[0021] 2. By commonly providing a highly doped P-well and a lightly doped P-well between adjacent MOS cells in the present utility model, this commonly provided P-well layer can inhibit the diffusion of charges into adjacent MOS cells, thereby improving the charge stability of the VDMOSFET device.

[0022] 3. By providing a second lightly doped N-well layer near the gate in the source N-well layer, the present utility model can suppress the influence of the gate electric field on the flowing charges in the first heavily doped N-well layer, reduce the retention of charges in the N-well layer, and form a parasitic charge effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present utility model will be further described in detail below with reference to the drawings and specific implementation methods.

[0024] Figure 1 is a schematic structural diagram of a VDMOSFET device;

[0025] Figure 2 is Figure 1 a partial enlarged detail schematic diagram;

[0026] Figure 3 is a schematic diagram of the cells of the present utility model arranged side by side.

[0027] In the figure: 1, drain; 2, substrate layer; 3, diffusion layer; 4, metal source; 5, gate; 6, first lightly doped N-well layer; 7, second lightly doped N-well layer; 8, first heavily doped N-well layer; 9, JFET region; 10, first lightly doped P-well; 11, first heavily doped P-well; 12, second heavily doped P-well; 13, second lightly doped P-well; 14, charge channel; 15, second heavily doped N-well layer; 16, oxidation insulation layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0029] As Figures 1-3 shown, a VDMOSFET device with stable charge conduction includes a plurality of MOS cells arranged side by side. The MOS cell includes a substrate layer 2, a diffusion layer 3, a P-well layer, and an N-well layer. By arranging a plurality of MOS cells side by side and finally forming a VDMOSFET device with stable charge conduction, the use in different voltage environments can be realized by increasing the number of MOS cells.

[0030] The P-well layer includes a first lightly doped P-well 10, a first heavily doped P-well 11, a second heavily doped P-well 12, and a second lightly doped P-well 13. The N-well layer includes a first lightly doped N-well layer 6, a second lightly doped N-well layer 7, and a first heavily doped N-well layer 8. And a first heavily doped P-well 11, a second heavily doped P-well 12, and a second lightly doped P-well 13 are commonly provided between adjacent MOS cells. This common provision of the P-well layer can suppress the diffusion of charges into adjacent MOS cells.

[0031] Inside the diffusion layer 3, ion implantation molding forms a heavily doped N-well layer II 15. The heavily doped N-well layer II 15 has better charge conductivity and a larger contact surface with the diffusion layer 3. After the charge channel 14 connects the heavily doped N-well layer I 8 and the heavily doped N-well layer II 15, the efficiency of charge flow from the diffusion layer 3 into the N-well layer is higher.

[0032] In this embodiment, the lower surface of the MOS cell is ohmically connected to the drain 1, and the upper surface of the MOS cell is ohmically connected to the metal source 4. A trench is etched on the upper surface of a single MOS cell, and a gate 5 is deposited inside the trench. When a voltage is applied to the gate 5, a JFET region 9 is formed in the diffusion layer 3. By controlling the voltage on the gate 5, the conductivity of the JFET region 9 can be adjusted (as Figure 3 shown). The characteristics of the JFET region 9 depend on the action of the gate electric field. By controlling the gate voltage, the conductivity of the JFET region 9 can be adjusted to implement various types of field-effect transistors.

[0033] In this embodiment, the cross-sections of the lightly doped P-well I 10 and the lightly doped P-well II 13 are both in an 'L' shape, and the lightly doped P-well I 10 and the lightly doped P-well II 13 are in an interlocking state. This design can effectively increase the hole density in the lightly doped P-well I 10, so that a charge channel can be formed even when a very small voltage is applied to the gate 5. The heavily doped P-well II 12 and the heavily doped P-well I 11 are respectively located on the upper and lower sides of the lightly doped P-well II 13, and the heavily doped P-well I 11 and the heavily doped P-well II 12 are integrated as a whole between adjacent MOS cells. The heavily doped P-well I 11 is in a downward convex state, and the heavily doped P-well I 11 inhibits the diffusion of charges in the diffusion layer 3 into adjacent MOS cells.

[0034] In this embodiment, the cross-section of the heavily doped N-well layer I 8 is in an 'L' shape, and the lightly doped N-well layer I 6 and the lightly doped N-well layer II 7 are respectively located on both sides of the heavily doped N-well layer I 8. When an electric field is applied between the gate 5 and the drain 1, a charge channel 14 is formed inside the lightly doped P-well I 10.

[0035] In this embodiment, the lightly doped N-well layer I 6 is doped with 5.2 - 8.2×10 15 mol / cm 3 phosphorus;

[0036] The lightly doped N-well layer II 7 is doped with 3.2 - 8.4×10 15 mol / cm 3 phosphorus;

[0037] The heavily doped N-well layer I 8 is doped with 7.2 - 9.5×10 18 mol / cm 3 phosphorus;

[0038] The heavily doped N-well layer 15 is doped with 2.1 - 3.4×10 18 mol / cm 3 of phosphorus element;

[0039] The lightly doped P-well 10 is doped with 2.3 - 3.2×10 16 mol / cm 3 of boron element;

[0040] The heavily doped P-well 11 is doped with 6.4 - 7.8×10 18 mol / cm 3 of boron element;

[0041] The heavily doped P-well 2 12 is doped with 7.3 - 9.4×10 18 mol / cm 3 of boron element;

[0042] The lightly doped P-well 2 13 is doped with 5.3 - 7.2×10 15 mol / cm 3 of boron element.

[0043] Of course, the above description is not a limitation of the present utility model, and the present utility model is not limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of the present utility model also belong to the protection scope of the present utility model.

Claims

1. A charge-conduction stable VDMOSFET device, characterized in that: It includes several MOS cells that are parallel to each other; The MOS cell comprises a substrate layer (2), a diffusion layer (3), a P-well layer and an N-well layer; The P-well layer includes a lightly doped P-well 1 (10), a heavily doped P-well 1 (11), a heavily doped P-well 2 (12) and a lightly doped P-well 2 (13); The N-well layer includes a lightly doped N-well layer 1 (6), a lightly doped N-well layer 2 (7) and a heavily doped N-well layer 1 (8); The diffusion layer (3) is internally ion-implanted to form a heavily doped N-well layer 2 (15); The lower surface of the MOS cell is ohmically connected to a drain electrode (1), and the upper surface of the MOS cell is ohmically connected to a metal source electrode (4); A groove is etched on the upper surface of a single MOS cell, and a gate (5) is deposited inside the groove; When a voltage is applied to the gate (5), a JFET region (9) is formed in the diffusion layer (3), and the conductivity of the JFET region (9) is adjusted by controlling the voltage on the gate (5).

2. The charge-conduction-stable VDMOSFET device according to claim 1, characterized in that: The cross sections of the lightly doped P well 1 (10) and the lightly doped P well 2 (13) are both in the shape of an "L" and the lightly doped P well 1 (10) and the lightly doped P well 2 (13) are in a mutually interlocking shape.

3. The charge-conduction stable VDMOSFET device according to claim 2, characterized in that: The heavily doped P well 2 (12) and the heavily doped P well 1 (11) are respectively located on the upper and lower sides of the lightly doped P well 2 (13), and the heavily doped P well 1 (11) and the heavily doped P well 2 (12) are integrated between adjacent MOS cells.

4. The charge-conduction stable VDMOSFET device according to claim 3, characterized in that: The heavily doped P well one (11) is in a downward convex state, and the heavily doped P well one (11) inhibits the charges in the diffusion layer (3) from diffusing into the adjacent MOS cells.

5. The charge-conduction-stable VDMOSFET device according to claim 1, characterized in that: The cross section of the heavily doped N well layer 1 (8) is formed in the shape of an 'L', and the lightly doped N well layer 1 (6) and the lightly doped N well layer 2 (7) are respectively located on both sides of the heavily doped N well layer 1 (8).

6. The charge-conduction-stable VDMOSFET device according to claim 1, characterized in that: When an electric field is connected between the gate (5) and the drain (1), a charge channel (14) is formed inside the lightly doped P well (10).

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