Planar gate SiC MOS with gate oxide protection junction
By forming a boss region at the gate of the SiC MOSFET device and injecting the P-shield region, the breakdown failure problem caused by high defect density of the gate oxide layer is solved, and the long-term reliability of the device is improved and good performance is maintained.
Patent Information
- Application Number
- CN202422072715.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-08-26
AI Technical Summary
Due to the high defect density of the gate oxide layer in SiC MOSFET devices, it is easy to break down and fail early in long-term use, affecting the reliability of the device.
The boss region is formed at the gate of the SiC MOSFET device and a P-shield region is injected at the bottom to shield the electric field from concentrating on the gate oxide layer.
It effectively protects the gate oxide layer, improves its reliability for long-term use, and reduces the increase in internal resistance caused by the P-shield region, avoiding negative impacts on device performance.
Smart Images
Figure CN223040478U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a planar gate SiC MOS with a gate oxide protection junction. Background Art
[0002] In voltage-controlled power switch devices, Si MOSFET and Si IGBT devices have always been the main ones. Among them, Si MOSFET is often used in medium and low voltage environments, generally below 600V, which is limited by the physical properties of Si material itself and the unipolar structure characteristics of MOSFET. And Si IGBT devices are usually used in high voltage environments, mostly above 600V, but their switching frequency is only 30kHz - 50kHz, which is limited by the bipolar structure characteristics of IGBT. Thus, it can be seen that while Si MOSFET and Si IGBT devices have obvious advantages, their disadvantages are also very significant.
[0003] As a typical third-generation wide bandgap material, SiC has excellent physical properties. Therefore, MOSFET devices prepared with SiC material can have many advantages such as high breakdown voltage, low on-state loss, high switching frequency, and low thermal resistance. Especially in the current booming new energy vehicle field, SiC MOSFET is considered to be its core product in the future. However, the long-term stable use of SiC MOSFET also faces many problems, and the most significant one is the gate oxide layer in SiC MOSFET. The gate oxide layer in SiC MOSFET is directly formed by thermal oxidation. However, affected by the C element in SiC, there will be many defects in the gate oxide layer, resulting in a large interface state density and poor quality at the SiC / SiO2 interface of the gate oxide. If the design is improper, the gate oxide layer will break down and fail prematurely during long-term use, causing the device to be unusable and even affecting the entire system. Therefore, how to better protect the gate oxide layer and improve the long-term use reliability of the gate oxide layer is very important for SiC MOSFET devices. Summary of the Utility Model
[0004] The utility model realizes the protection of the device gate oxide layer and at the same time reduces the problem of the increase in device internal resistance brought by the P-shield region; during the device blocking process, the P-shield region at the bottom of the convex region well shields the electric field and avoids the concentration of the electric field in the gate oxide layer.
[0005] The technical solution of the utility model is as follows:
[0006] A planar gate SiC MOS with a gate oxide protection junction includes an SiC Sub layer, an SiC Drift layer, and a CSL region arranged in sequence from bottom to top; on the CSL region, there are provided:
[0007] The P-body region extends downward from the top surface of the CSL region;
[0008] The NP region extends downward from the top surface of the P-body region;
[0009] The PP region extends downward from the top surface of the P-body region and is connected to the side of the NP region;
[0010] The P-shield region extends downward from the middle of the top surface of the CSL region;
[0011] The gate oxide layer covers the P-shield region, and its bottom surface is connected to the NP region, P-body region, CSL region, and P-shield region respectively;
[0012] The Poly layer covers the gate oxide layer;
[0013] The isolation dielectric layer wraps around the gate oxide layer and the Poly layer, and its bottom surface is connected to the NP region; the inner side of the isolation dielectric layer is connected to the gate oxide layer and the Poly layer respectively;
[0014] The source ohmic contact alloy layer is arranged on the side of the isolation dielectric layer, and its bottom surface is connected to the NP region and the PP region respectively;
[0015] The front electrode metal layer is arranged on the top of the device, and its bottom surface is connected to the source ohmic contact alloy layer and the isolation dielectric layer respectively.
[0016] Specifically, the thickness of the SiC Sub layer is 150um - 400um, and the thickness of the SiC Drift layer is 5um - 20um.
[0017] Specifically, the bottom surface depth of the CSL region is 1um - 2um, and the doping concentration is 5E16 - 1E18 cm -2 .
[0018] Specifically, the bottom surface depth of the P-body region is 0.8um - 1.2um, and the doping concentration is 1E17 - 3E18 cm -2 .
[0019] Specifically, the bottom surface depth of the NP region is 0.3um - 0.6um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0020] Specifically, the bottom surface depth of the PP region is 0.4um - 0.8um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0021] Specifically, the bottom depth of the P-shield region is 0.3 um - 0.6 um, the width is 0.4 um - 0.8 um, and the doping concentration is 1E17 - 5E18 cm -2 .
[0022] Specifically, the thickness of the gate oxide layer is between 40 nm and 70 nm.
[0023] In the SiC MOSFET device of the present utility model, a convex region is formed by micro-groove etching at the gate of the device, and a P-shield region is formed by implantation at the bottom of the convex region, realizing the protection of the gate oxide layer of the device and simultaneously reducing the increase in the internal resistance of the device caused by the P-shield region. During the blocking process of the device, the P-shield region at the bottom of the convex region can well shield the electric field and prevent the electric field from concentrating in the gate oxide layer. And because the bottom surface of the P-shield region is at a higher position compared to the P-body region, the increase in internal resistance caused by the P-shield region is relatively small and will not overly affect the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a schematic structural diagram of the SiC MOSFET of the present utility model;
[0025] Figure 2 is a schematic structural diagram of step S100 of the present utility model;
[0026] Figure 3 is a schematic structural diagram of step S200 of the present utility model;
[0027] Figure 4 is a schematic structural diagram of step S300 of the present utility model;
[0028] Figure 5 is a schematic structural diagram of step S400 of the present utility model;
[0029] Figure 6 is a schematic structural diagram of step S500 of the present utility model;
[0030] Figure 7 is a schematic structural diagram of step S600 of the present utility model;
[0031] Figure 8 is a schematic structural diagram of step S700 of the present utility model;
[0032] Figure 9 is a schematic structural diagram of step S900 of the present utility model;
[0033] Figure 10 is a schematic structural diagram of step S1000 of the present utility model;
[0034] Figure 11It is a schematic structural diagram of step S1100 of the present utility model;
[0035] Figure 12 It is a schematic structural diagram of step S1200 of the present utility model;
[0036] In the figure, 1 is the SiC Sub layer, 2 is the SiC Drift layer, 3 is the CSL region, 4 is the P-body region, 5 is the NP region, 6 is the PP region, 7 is the P-shield region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the source ohmic contact alloy layer, and 12 is the front electrode metal layer. Detailed implementation manners
[0037] The present utility model will be described in detail below in combination with specific actual cases. The examples of the embodiments are shown in the drawings. The schematic embodiments and descriptions thereof of the present utility model are only used to explain the present utility model and shall not be construed as a limitation to the present utility model.
[0038] A method for preparing a planar gate SiC MOS with a gate oxide protection junction includes the following steps:
[0039] S100, homoepitaxially grow a layer of SiC Drift layer 2 on the SiC Sub layer 1; as Figure 2 shown;
[0040] The thickness of the SiC Sub layer 1 in step S100 is 150 um - 400 um, and the thickness of the SiC Drift layer 2 is 5 um - 20 um.
[0041] S200, preliminarily form a CSL region 3 on the top surface of the SiC Drift layer 2 by oblique N ion implantation; as Figure 3 shown;
[0042] The bottom depth of the CSL region 3 in step S200 is 1 um - 2 um, and the doping concentration is 5E16 - 1E18 cm -2 .
[0043] S300, micro-etch the upper surface of the CSL region 3 to form a convex platform region in the middle of the top surface of the CSL region 3, as Figure 4 shown;
[0044] The depth of the micro-etching in step S300 is 0.2 um - 0.5 um.
[0045] S400, preliminarily form a P-body region 4 on the top surface of the CSL region 3 by oblique Al ion implantation, as Figure 5 shown;
[0046] The bottom depth of the P-body region 4 in step S400 is 0.8um - 1.2um, and the doping concentration is 1E17 - 3E18 cm -2 .
[0047] S500, initially form an NP region 5 on the top surface of the P-body region 4 by oblique N ion implantation, as Figure 6 shown;;
[0048] The bottom depth of the NP region 5 in step S500 is 0.3um - 0.6um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0049] S600, initially form a PP region 6 on the top surface of the P-body region 4 by oblique Al ion implantation, as Figure 7 shown;;
[0050] The bottom depth of the PP region 6 in step S600 is 0.4um - 0.8um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0051] S700, initially form a P-shield region 7 on the top surface of the convex region in the CSL region 3 by oblique Al ion implantation, as Figure 8 shown;;
[0052] The bottom depth of the P-shield region 7 in step S700 is 0.3um - 0.6um, the width is 0.4um - 0.8um, and the doping concentration is 1E17 - 5E18 cm -2 .
[0053] S800, completely form the implanted regions of the CSL region 3, P-body region 4, NP region 5, PP region 6 and P-shield region 7 by high-temperature ion activation;
[0054] The high-temperature activation annealing temperature in step S800 is 1600℃ - 1900℃.
[0055] S900, grow a gate oxide layer 8 on the top surfaces of the CSL region 3, P-body region 4, NP region 5 and P-shield region 7 by dry oxidation; as Figure 9 shown;
[0056] The thickness of the gate oxide layer 8 in step S900 is 40nm - 70nm.
[0057] S1000, form a Poly layer 9 on the top surface of the gate oxide layer 8 by polysilicon Poly deposition for use as the gate electrode of the device, as Figure 10 shown;
[0058] The thickness of the Poly layer 9 in step S1000 is between 0.5 μm and 1.2 μm.
[0059] S1100, a layer of isolation dielectric layer 10 is formed on the top surface of the NP region 5 and the Poly layer 9 by means of oxide layer deposition, which is used as a dielectric to prevent the short circuit between the device gate electrode and the source electrode, as Figure 11 shown;
[0060] S1200, a source ohmic contact alloy layer 11 is formed on the top surface of the NP region 5 and the PP region 6 by sputtering Ni metal followed by thermal annealing, as Figure 12 shown;
[0061] The thickness of the Ni metal in step S1200 is between 0.1 μm and 0.3 μm.
[0062] S1300, a front electrode metal layer 12 is formed on the top of the device by sputtering Ti and AlCu metals, as Figure 1 shown.
[0063] The thickness of the Ti metal in step S1300 is 0.1 μm - 0.5 μm, and the thickness of the AlCu metal is 2 μm - 5 μm.
[0064] A planar gate SiC MOS with a gate oxide protection junction includes an SiC Sub layer 1, an SiC Drift layer 2, and a CSL region 3 arranged in sequence from bottom to top; on the CSL region 3 are provided:
[0065] A P-body region 4 extends downward from the top surface of the CSL region 3, and its bottom surface is higher than the bottom surface of the CSL region 3;
[0066] An NP region 5 extends downward from the top surface of the P-body region 4, and its bottom surface is higher than the bottom surface of the P-body region 4;
[0067] A PP region 6 extends downward from the top surface of the P-body region 4 and is connected to the side of the NP region 5; the PP region 6 is located outside the NP region 5;
[0068] A P-shield region 7 extends downward from the middle of the top surface of the CSL region 3;
[0069] A gate oxide layer 8 covers the P-shield region 7, and its bottom surface is connected to the NP region 5, the P-body region 4, the CSL region 3, and the P-shield region 7 respectively;
[0070] A Poly layer 9 covers the gate oxide layer 8;
[0071] The isolation dielectric layer 10 is wrapped on the gate oxide layer 8 and the Poly layer 9, and its bottom surface is connected to the NP region 5; the inner sides of the isolation dielectric layer 10 are respectively connected to the gate oxide layer 8 and the Poly layer 9;
[0072] The source ohmic contact alloy layer 11 is arranged on the side of the isolation dielectric layer 10, and its bottom surface is respectively connected to the NP region 5 and the PP region 6;
[0073] The front electrode metal layer 12 is arranged on the top of the device, and its bottom surface is respectively connected to the source ohmic contact alloy layer 11 and the isolation dielectric layer 10.
[0074] The top surface of the P-shield region 7 is higher than the top surface of the P-body region 4.
[0075] Since the SiC material can directly grow the gate oxide layer SiO2 through thermal oxidation, it is a very suitable material for manufacturing MOSFET devices. However, different from Si, SiC is rich in C elements inside, which leads to many defects during the thermal oxidation growth process, such as C clusters, oxygen vacancies, dangling bonds, etc. The disadvantage of these defects is the poor quality of the gate oxide layer. If the electric field is concentrated, it is very easy to occur breakdown failure, thus damaging the device. In the SiC MOSFET device of the present invention, a convex platform region is formed by micro-groove etching at the gate of the device, and a P-shield region 7 is formed by implantation at the bottom of the convex platform region. During the blocking process of the device, the P-shield region 7 at the bottom of the convex platform region can effectively shield the electric field, avoid the concentration of the electric field in the gate oxide layer, thereby improving the long-term use reliability of the gate oxide layer. And because the bottom surface of the P-shield region 7 is at a higher position compared with the P-body region 4, the increase in internal resistance caused by the P-shield region 7 is also smaller and will not overly affect the performance of the device.
Claims
1. A planar gate SiC MOS with a gate oxide protection junction, characterized in that: The invention comprises a SiC Sub layer (1), a SiC Drift layer (2) and a CSL region (3) which are arranged in sequence from bottom to top; the CSL region (3) is provided with: A P-body region (4) extending downward from the top surface of the CSL region (3); An NP region (5) extending downward from the top surface of the P-body region (4); A PP region (6), extending downward from the top surface of the P-body region (4) and connected to the side of the NP region (5); A P-shield region (7) extending downward from the middle of the top surface of the CSL region (3); A gate oxide layer (8) is disposed on the P-shield region (7), and its bottom surface is respectively connected to the NP region (5), the P-body region (4), the CSL region (3) and the P-shield region (7); A Poly layer (9) is disposed on the gate oxide layer (8); An isolation dielectric layer (10) is wrapped on the gate oxide layer (8) and the Poly layer (9), and the bottom surface is connected to the NP region (5); the inner side of the isolation dielectric layer (10) is respectively connected to the gate oxide layer (8) and the Poly layer (9); The source ohmic contact alloy layer (11) is arranged on the side of the isolation dielectric layer (10), and the bottom surface is respectively connected to the NP region (5) and the PP region (6).
2. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The SiC Sub layer (1) has a thickness of 150um-400um, and the SiC Drift layer (2) has a thickness of 5um-20um.
3. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The bottom surface depth of the CSL region (3) is 1 um to 2 um.
4. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The bottom surface depth of the P-body region (4) is 0.8um-1.2um.
5. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The bottom surface depth of the NP region (5) is 0.3um-0.6um.
6. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The bottom surface depth of the PP region (6) is 0.4um-0.8um.
7. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The bottom surface depth of the P-shield region (7) is 0.3um-0.6um, and the width is 0.4um-0.8um.
8. The planar gate SiC MOS with gate oxide protection junction according to claim 1, characterized in that: The thickness of the gate oxide layer (8) in step S500 is between 40 nm and 70 nm.