Overlay pattern and wafer
By designing T-shaped engraving graphics, the problem of inlay patterns cannot be placed in narrow cutting channels is solved, the IBO measurement accuracy is improved, the cutting channels area is saved and the size of semiconductor devices is reduced.
Patent Information
- Application Number
- CN202421905602.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-07
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-08-07
AI Technical Summary
The overprinted graphics in the existing IBO measurement technology cannot be effectively placed in the cutting path with a width of 40um, resulting in low measurement accuracy and inability to meet customer needs.
A tying pattern is designed, including the front layer and the layer tying pattern when both are in a T-shaped shape, and the sum of the widths of the front layer and the layer tying pattern in the second direction is less than or equal to 20um, which can be placed in the 40um cutting path and two sets of tying patterns are included in the 60um cutting path content, and the tying error is detected by alternately or relative settings.
The measurement accuracy of IBO measurement technology is improved, the area of the cutting channel is saved, and the size of semiconductor devices is reduced.
Smart Images
Figure CN223051640U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of lithography technology, and particularly relates to an overlay pattern and a wafer. Background Art
[0002] Overlay error refers to the deviation of the pattern on the wafer in the current layer relative to the pattern in the previous layer in the x - direction and y - direction during IC manufacturing. Ideally, the patterns in the current layer and the previous layer are exactly aligned, that is, the overlay error is zero. To ensure reliable connection of the circuits designed in the upper and lower layers, the overlay error between the current layer and the previous layer must be less than 1 / 3 - 1 / 5 of the line width of the pattern feature. The rapid measurement and accurate evaluation of overlay error are the keys to optimizing the operation parameters of the lithography machine and managing the process yield.
[0003] From the perspective of the basic measurement principle, optical overlay error measurement techniques can be divided into: imaging - based overlay error (IBO) measurement technique and diffraction - based overlay error (DBO) measurement technique. The IBO measurement technique uses a high - resolution bright - field optical microscope with image recognition and measurement functions to measure the deviation of the pattern position in a specially designed overlay mark to achieve the measurement of overlay error; the overlay mark in the DBO measurement technique is a specially designed nano - grating structure, and by measuring the diffraction signals of the overlay mark, such as spectra or angular - resolved spectra, etc., the overlay error is extracted through a certain method. IBO uses optical technology to measure the Overlay error, while DBO uses the diffraction phenomenon for measurement. Compared with DBO, the measurement accuracy of IBO is lower, but it has the advantage of faster speed.
[0004] In particular, with the increasing requirements of customers and the trend of continuously reducing line widths, the scribe lanes are also required to be tightened, and it cannot meet the current and future needs under the limitation of the lithography overlay size. The width of the overlay pattern in the existing IBO measurement technique is 50um, which can only be applied to scribe lanes with a width of 60um. For scribe lanes with a width of 40um, the overlay patterns in the existing IBO measurement technique cannot effectively meet the customer's needs. Summary of the Utility Model
[0005] The purpose of the utility model is to provide an overlay pattern and a wafer to solve at least one of the problems that the measurement accuracy of IBO is relatively low and the overlay pattern in the existing IBO measurement technique cannot be placed in a scribe lane with a width of 40um.
[0006] To solve the above technical problems, the present utility model provides an overlay pattern, which includes a front-layer overlay pattern and a current-layer overlay pattern. The front-layer overlay pattern and the current-layer overlay pattern have the same shape and are both in a T shape. The front-layer overlay pattern includes a first part extending in a first direction and a second part extending in a second direction, and the current-layer overlay pattern includes a first part extending in the first direction and a second part extending in the second direction. The first direction and the second direction are perpendicular to each other. The second part of the front-layer overlay pattern and the second part of the current-layer overlay pattern are oppositely arranged in the second direction, and the sum of the widths of the front-layer overlay pattern and the current-layer overlay pattern in the second direction is less than or equal to 20um.
[0007] Optionally, in the first direction, the front-layer overlay pattern and the current-layer overlay pattern are alternately arranged to detect the overlay error in the second direction.
[0008] Optionally, in the second direction, the front-layer overlay pattern and the current-layer overlay pattern are oppositely arranged to detect the overlay error in the first direction.
[0009] Optionally, the first direction is the X direction and the second direction is the Y direction.
[0010] Optionally, the first direction is the Y direction and the second direction is the X direction.
[0011] Optionally, the overlay pattern is located within the scribe line of the wafer, and at least one set of the overlay patterns is accommodated in the scribe line.
[0012] Optionally, the width of the scribe line is less than or equal to 40um, and one set of the overlay patterns is accommodated in the scribe line.
[0013] Optionally, the width of the scribe line is 60um, and two sets of the overlay patterns can be accommodated in the scribe line.
[0014] Optionally, the overlay pattern is used for IBO measurement technology.
[0015] Based on the same inventive concept, the present utility model also provides a wafer, which includes a chip area and a scribe line area, and the scribe line area is used to form the overlay pattern as described in any one of the above.
[0016] In a pattern overlay and a wafer provided by the present utility model, the pattern overlay includes a front-layer pattern overlay and a current-layer pattern overlay. By setting the shapes of the front-layer pattern overlay and the current-layer pattern overlay to be the same and both in a T shape, the front-layer pattern overlay includes a first part extending in a first direction and a second part extending in a second direction, and the current-layer pattern overlay includes a first part extending in the first direction and a second part extending in the second direction, where the first direction and the second direction are perpendicular to each other; the second part of the front-layer pattern overlay and the second part of the current-layer pattern overlay are oppositely arranged in the second direction, and the sum of the widths of the front-layer pattern overlay and the current-layer pattern overlay in the second direction is less than or equal to 20 um. The present invention reduces the size in the second direction through the T-shaped designed pattern overlay. The width of the pattern overlay can meet the requirement of being placed in a dicing lane with a width of 40 um. Further, two sets of pattern overlay combinations can be accommodated in a dicing lane with a width of 60 um, improving the measurement accuracy of the IBO measurement technology, and solving the technical problem of placing the pattern overlay in a narrow dicing lane, saving the area of the dicing lane, and reducing the size of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present utility model and do not constitute any limitation to the scope of the present utility model. Among them:
[0018] Figure 1 is a schematic diagram of a pattern overlay in the prior art.
[0019] Figure 2 is a schematic diagram of a pattern overlay in a dicing lane according to an embodiment of the present utility model.
[0020] Figure 3 is a schematic diagram of another pattern overlay in a dicing lane according to an embodiment of the present utility model.
[0021] In the drawings:
[0022] 10 - pattern overlay; 11 - front-layer pattern overlay; 12 - current-layer pattern overlay;
[0023] 20 - pattern overlay; 20a - first set of pattern overlay; 20b - second set of pattern overlay; 21 - front-layer pattern overlay; 21a - first part of the front-layer pattern overlay; 21b - second part of the front-layer pattern overlay; 22 - current-layer pattern overlay; 22a - first part of the current-layer pattern overlay; 22b - second part of the current-layer pattern overlay. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] To make the objectives, advantages, and features of the present utility model clearer, the following further elaborates on the present utility model in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and not drawn to scale, only serving to conveniently and clearly assist in explaining the objectives of the embodiments of the present utility model. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphasis to be shown in each of the accompanying drawings is different, and sometimes different scales are used.
[0025] As used in the present utility model, the singular forms "a", "an", and "the" include plural objects. The term "or" is generally used in the sense of including "and / or". The term "several" is generally used in the sense of including "at least one". The term "at least two" is generally used in the sense of including "two or more". In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present utility model, when an element is provided on another element, it generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated, or transmitted through an intermediate element, rather than being construed as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below, or on one side of another element in any orientation, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0026] Figure 1 It is a schematic diagram of an overlay pattern in the prior art. The inventor has found that in the existing overlay pattern 10, it includes a front-layer overlay pattern 11 and a current-layer overlay pattern 12. In order to measure the overlay error in the X direction and the overlay error in the Y direction, four sets of overlay sub-patterns are provided. The four sets of overlay sub-patterns are arranged in an array, with two sets of overlay sub-patterns in each row and also two sets of overlay sub-patterns in each column. The overlay error in the X direction and the overlay error in the Y direction can be measured in each row and each column. However, in the prior art, the sum of the widths of the two sets of overlay sub-patterns in each row or each column is 45um, and the edge regions on both sides of the overlay sub-patterns are 2.5um. The sum of the width of the two sets of overlay sub-patterns in each row or each column of the entire overlay pattern and the widths of the edge regions on both sides is 50um, which can only be applied to a scribe lane with a width of 60um. For a scribe lane with a width of 40um, the existing overlay pattern cannot effectively meet the customer's needs.
[0027] Based on this, the core idea of the present utility model is that the present utility model provides a nested pattern and a wafer. The nested pattern includes a pre-layer nested pattern and a current-layer nested pattern. By setting the shapes of the pre-layer nested pattern and the current-layer nested pattern to be the same and both in a T shape, the pre-layer nested pattern includes a first part extending in a first direction and a second part extending in a second direction, and the current-layer nested pattern includes a first part extending in the first direction and a second part extending in the second direction, where the first direction and the second direction are perpendicular to each other; the second part of the pre-layer nested pattern and the second part of the current-layer nested pattern are oppositely arranged in the second direction, and the sum of the widths of the pre-layer nested pattern and the current-layer nested pattern in the second direction is less than or equal to 20um. The present invention reduces the size in the second direction through the T-shaped nested pattern design. The width of the nested pattern can meet the requirement of being placed in a scribe lane with a width of 40um. Further, two sets of nested pattern combinations can be accommodated in a scribe lane with a width of 60um, improving the measurement accuracy of the IBO measurement technology, and solving the technical problem of placing the nested pattern in a narrow scribe lane, saving the area of the scribe lane and reducing the size of the semiconductor device.
[0028] Figure 2 is a schematic diagram of a nested pattern in a scribe lane according to an embodiment of the present utility model. As Figure 2 shown, the present embodiment provides a nested pattern 20, which includes a pre-layer nested pattern 21 and a current-layer nested pattern 22. The shapes of the pre-layer nested pattern 21 and the current-layer nested pattern 22 are the same and both in a T shape. The pre-layer nested pattern 21 includes a first part 21a extending in the first direction and a second part 21b extending in the second direction, and the current-layer nested pattern 22 includes a first part 22a extending in the first direction and a second part 22b extending in the second direction. The first direction and the second direction are perpendicular to each other. The second part 21b of the pre-layer nested pattern and the second part 22b of the current-layer nested pattern are oppositely arranged in the second direction, and the sum of the widths of the pre-layer nested pattern 21 and the current-layer nested pattern 22 in the second direction is less than or equal to 20umm. Therefore, the present embodiment reduces the size in the second direction through the T-shaped nested pattern design. The width of the nested pattern can meet the requirement of being placed in a scribe lane with a width of 40um. Further, two sets of nested pattern combinations can be accommodated in a scribe lane with a width of 60um, improving the measurement accuracy of the IBO measurement technology, and solving the technical problem of placing the nested pattern in a narrow scribe lane, saving the area of the scribe lane and reducing the size of the semiconductor device.
[0029] Please continue to refer to Figure 2, in the first direction, the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 are arranged alternately. The previous-layer alignment pattern 21 and the current-layer alignment pattern 22 are arranged in sequence in the first direction. When there is an error between the adjacent previous-layer alignment pattern 21 and the current-layer alignment pattern 22, the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 are not in the same first direction. For example, the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 will move up and down, resulting in an alignment error in the second direction. Therefore, by arranging the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 alternately in the first direction, the alignment error in the second direction is detected. The first direction and the second direction are perpendicular to each other. In this embodiment, the first direction is, for example, the X direction, and the second direction is, for example, the Y direction. In other embodiments, the first direction can be the Y direction, and the second direction can be the X direction.
[0030] Please continue to refer to Figure 2 , in the second direction, the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 are arranged oppositely. That is, the first part 21a of the previous-layer alignment pattern and the first part 22a of the current-layer alignment pattern are far away from each other, and the second part 21b of the previous-layer alignment pattern and the second part 22b of the current-layer alignment pattern are close to each other. The previous-layer alignment pattern 21 and the current-layer alignment pattern 22 are arranged oppositely in the second direction. When there is an error between the oppositely arranged previous-layer alignment pattern 21 and the current-layer alignment pattern 22, the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 are not in the same second direction. For example, the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 will move left and right, resulting in an alignment error in the first direction. Therefore, by arranging the previous-layer alignment pattern 21 and the current-layer alignment pattern 22 oppositely in the second direction, the alignment error in the first direction is detected. The first direction and the second direction are perpendicular to each other. In this embodiment, the first direction is, for example, the X direction, and the second direction is, for example, the Y direction. In other embodiments, the first direction can be the Y direction, and the second direction can be the X direction.
[0031] This embodiment also provides a wafer, which includes a chip area and a scribe lane area. The scribe lane area is used to form the alignment pattern 20 as described in any one of the above. The alignment pattern 20 is located within the scribe lane of the wafer, and at least one group of the alignment pattern 20 is accommodated in the scribe lane.
[0032] Please continue to refer to Figure 2, in one embodiment, the width of the scribing lane is less than or equal to 40 um, and the scribing lane accommodates a set of the overlay patterns 20. The width of the overlay pattern 20 is 20 um, and the width of the two side edge regions is 2.5 um. Therefore, the sum of the width of the overlay pattern 20 and the widths of the two side edge regions is 25 um, which can meet the design requirements of the scribing lane with a width of 40 um, reduce the width of the scribing lane, and increase the area of the chips in the wafer.
[0033] Figure 3 is a schematic diagram of an overlay pattern in another scribing lane according to an embodiment of the present invention. As Figure 3 shown, the width of the scribing lane is 60 um, and two sets of the overlay patterns can be accommodated in the scribing lane, namely the first set of overlay patterns 20a and the second set of overlay patterns 20b. The widths of the first set of overlay patterns 20a and the second set of overlay patterns 20b are 20 um respectively, and the width of the two side edge regions is 2.5 um. The spacing width between the first set of overlay patterns 20a and the second set of overlay patterns 20b is not greater than 2.5 um. Therefore, the sum of the width of the first set of overlay patterns 20a, the width of the second set of overlay patterns 20b, the spacing width between the first set of overlay patterns 20a and the second set of overlay patterns 20b, and the widths of the two side edge regions is less than or equal to 47.5 um, which can meet the requirement of placing two sets of the overlay patterns in the scribing lane with a width of 60 um. Placing two sets of overlay patterns in the same scribing lane can improve the measurement accuracy of the overlay patterns.
[0034] The overlay pattern in this embodiment is used for IBO measurement technology. The IBO measurement technology uses a high-resolution bright-field optical microscope with image recognition and measurement functions to measure the deviation of the pattern position in a specially designed overlay mark to achieve the measurement of overlay error; compared with DBO, the measurement accuracy of IBO is lower, but it has the advantage of faster speed. Through the overlay pattern provided in this embodiment, both the measurement speed and the measurement accuracy can be guaranteed.
[0035] In summary, in a kind of overlay pattern and wafer provided by the embodiment of the present utility model, the overlay pattern includes a previous layer overlay pattern and a current layer overlay pattern. By setting the shapes of the previous layer overlay pattern and the current layer overlay pattern to be the same and both in a T shape, the previous layer overlay pattern includes a first part extending along a first direction and a second part extending along a second direction, and the current layer overlay pattern includes a first part extending along the first direction and a second part extending along the second direction. The first direction and the second direction are perpendicular to each other. The second part of the previous layer overlay pattern and the second part of the current layer overlay pattern are oppositely arranged in the second direction, and the sum of the widths of the previous layer overlay pattern and the current layer overlay pattern in the second direction is less than or equal to 20 nm. In this embodiment, the overlay pattern designed in a T shape reduces the size in the second direction, and the width of the overlay pattern can meet the requirement of being placed in a dicing lane with a width of 40 μm. Further, two sets of overlay pattern combinations can be accommodated in a dicing lane with a width of 60 μm, which improves the measurement accuracy of the IBO measurement technology, solves the technical problem of placing the overlay pattern in a narrow dicing lane, saves the area of the dicing lane, and reduces the size of the semiconductor device.
[0036] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. In addition, the different parts among the various embodiments can also be combined and used with each other. The present utility model does not make any limitation in this regard.
[0037] In addition, it should also be recognized that although the present utility model has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present utility model. For any person skilled in the art, without departing from the scope of the technical solution of the present utility model, many possible changes and modifications can be made to the technical solution of the present utility model by using the disclosed technical content above, or it can be modified into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present utility model without departing from the content of the technical solution of the present utility model still belong to the scope protected by the technical solution of the present utility model.
Claims
1. A pattern of overlay, characterized in that: The overlay pattern includes a front-layer overlay pattern and a current-layer overlay pattern, the front-layer overlay pattern and the current-layer overlay pattern have the same shape and are both T-shaped, the front-layer overlay pattern includes a first part extending along a first direction and a second part extending along a second direction, and the current-layer overlay pattern includes a first part extending along a first direction and a second part extending along a second direction, the first direction and the second direction are perpendicular to each other; the second part of the front-layer overlay pattern and the second part of the current-layer overlay pattern are relatively arranged in the second direction, and the sum of the widths of the front-layer overlay pattern and the current-layer overlay pattern in the second direction is less than or equal to 20um.
2. The overlay pattern according to claim 1, characterized in that: In the first direction, the previous layer overlay pattern and the current layer overlay pattern are arranged alternately to detect the overlay error in the second direction.
3. The overlay pattern according to claim 1, characterized in that: In the second direction, the previous layer overlay pattern and the current layer overlay pattern are arranged relatively to each other to detect the overlay error in the first direction.
4. The overlay pattern according to claim 1, characterized in that: The first direction is the X direction, and the second direction is the Y direction.
5. The overlay pattern according to claim 1, characterized in that: The first direction is the Y direction, and the second direction is the X direction.
6. The overlay pattern according to claim 1, characterized in that: The overlay pattern is located within a cutting path of the wafer, and the cutting path contains at least one group of the overlay patterns.
7. The overlay pattern according to claim 6, characterized in that: The width of the cutting road is less than or equal to 40um, and the cutting road accommodates a group of the overlay patterns.
8. The overlay pattern according to claim 6, characterized in that: The width of the cutting road is 60um, and the cutting road can accommodate two groups of the overlay patterns.
9. The overlay pattern according to claim 1, characterized in that: The overlay pattern is used for IBO measurement technology.
10. A wafer, characterized in that: The wafer comprises a chip area and a dicing area, and the dicing area is used to form the overlay pattern as claimed in any one of claims 1 to 9.