Semiconductor test structure and wafer

Abstract

The utility model provides a semiconductor test structure and a wafer. The semiconductor test structure comprises a plurality of pads; the top metal layer is arranged in the substrate, the bonding pads are located in the top metal layer, and the two ends of the top metal layer are first to-be-tested ends; the bottom metal layer is arranged in the substrate, and two ends of the bottom metal layer are second to-be-tested ends; and the passivation layer is arranged between the bottom metal layer and the top metal layer, and the passivation layer is arranged between the top metal layer and the plurality of bonding pads. In one embodiment of the utility model, a plurality of bonding pads are arranged in an array, and the metal wire of the top metal layer sequentially surrounds each bonding pad. According to the utility model, whether the passivation layer has cracks can be rapidly and efficiently detected, and the detection efficiency of the semiconductor test structure is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor test structure and a wafer. Background Art

[0002] In the semiconductor manufacturing process, in order to protect integrated circuits from the influence of the external environment, such as water vapor, foreign impurities and mechanical damage, a passivation layer (PV, passivation) is usually deposited above the integrated circuit. Due to excessive internal stress generated during the deposition and curing of the passivation layer, or the mismatch of the thermal expansion coefficient with the underlying metal layer, cracks are generated during temperature changes or cooling processes, which may lead to the failure of the integrated circuit. In the prior art, the surface change of the integrated circuit is observed through a microscope to determine whether cracks occur, but there is a problem of low detection efficiency. Therefore, there are areas for improvement. Summary of the Utility Model

[0003] The utility model provides a semiconductor test structure and a wafer to solve the technical problem of low detection efficiency in observing cracks on the surface of an integrated circuit through a microscope in the prior art.

[0004] A semiconductor test structure provided by the utility model is characterized by comprising:

[0005] A plurality of pads;

[0006] A top metal layer is arranged in the substrate, and a plurality of the pads are located inside the top metal layer. Both ends of the top metal layer are first test ends;

[0007] A bottom metal layer is arranged in the substrate, and both ends of the bottom metal layer are second test ends;

[0008] A passivation layer is arranged between the bottom metal layer and the top metal layer, and a passivation layer is also arranged between the top metal layer and a plurality of the pads.

[0009] In an embodiment of the utility model, a plurality of the pads are arranged in an array, and the metal wires of the top metal layer successively surround each of the pads.

[0010] In an embodiment of the utility model, after the metal wire of the top metal layer surrounds a certain pad in the clockwise direction, it surrounds the adjacent pad in the same row as this pad in the counterclockwise direction, and then surrounds the adjacent pad in the same column as this pad in the clockwise direction;

[0011] After the metal line of the top metal layer winds around a certain pad in the clockwise direction, it winds around an adjacent pad in the same column as the pad in the counterclockwise direction, and then winds around an adjacent pad in the same row as the pad in the clockwise direction.

[0012] In an embodiment of the present invention, the width of the metal line of the top metal layer is denoted as the first width, and the distance between the metal line of the top metal layer and the pad is denoted as the distance width, and the first width is the same as the distance width.

[0013] In an embodiment of the present invention, the side length of the pad is denoted as the side length width, and the ratio between the first width and the side length width is 1 / 15 to 1 / 10.

[0014] In an embodiment of the present invention, on the projection of multiple pads on the plane where the bottom metal layer is located, the metal lines of the bottom metal layer wind around each pad in turn.

[0015] In an embodiment of the present invention, the metal line trajectory of the top metal layer corresponds to the metal line trajectory of the bottom metal layer.

[0016] In an embodiment of the present invention, the metal line of the top metal layer is denoted as the top metal line, and the metal line of the bottom metal layer is denoted as the bottom metal line;

[0017] For a section of the top metal line, the bottom metal line extends along the first side of the top metal line to its second side, and then extends along the second side of the top metal line to its first side, and the bottom metal line performs periodic wiring along the top metal line.

[0018] In an embodiment of the present invention, the width of the metal line of the top metal layer is denoted as the first width, and the width of the metal line of the bottom metal layer is denoted as the second width, and the ratio between the first width and the second width is 5 to 10.

[0019] The present invention also provides a wafer, including a substrate, and the semiconductor test structure as described in any one of the above is provided in the substrate.

[0020] The beneficial effects of the present invention: A semiconductor test structure and a wafer provided by the present invention. In the semiconductor test structure, after depositing a passivation layer above the bottom metal layer, the top metal layer and the pads, a first test end is led out from the top metal layer, and a second test end is led out from the bottom metal layer. By performing an electrical test on the top metal layer outside the pads or the bottom metal layer at the bottom of the pads, it is possible to detect whether there are cracks in the passivation layer and the specific position where the cracks occur in the passivation layer. Description of the Drawings

[0021] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 The top view of the semiconductor test structure provided by an embodiment of the present utility model.

[0023] Figure 2 The top view of the top metal layer and the bottom metal layer in the semiconductor test structure provided by an embodiment of the present utility model.

[0024] Explanation of the reference numerals in the drawings: 10, pad; 20, top metal layer; 210, first end of the top layer; 220, second end of the top layer; 230, third end of the top layer; 240, fourth end of the top layer; 30, bottom metal layer; 310, first end of the bottom layer; 320, second end of the bottom layer; 330, third end of the bottom layer; 340, fourth end of the bottom layer. Specific embodiments

[0025] The following uses specific examples to illustrate the embodiments of the present utility model. Those skilled in the art can easily understand other advantages and effects of the present utility model from the content disclosed in this specification. The present utility model can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present utility model. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0026] It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present utility model in a schematic manner. Therefore, only the components related to the present utility model are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0027] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present utility model. However, it is obvious to those skilled in the art that the embodiments of the present utility model can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present utility model difficult to understand.

[0028] Please refer to Figures 1 to 2, the present utility model proposes a semiconductor test structure, which can be applied in the field of semiconductor manufacturing processes. For example, a passivation layer is deposited on top of an integrated circuit. The passivation layer generates a dense passivation film with good coverage on the surface of the integrated circuit. By electrically testing the top metal layer 20 outside the pad 10 or the bottom metal layer 30 at the bottom of the pad 10, it is possible to detect whether cracks occur in the passivation layer and the specific location where the cracks occur in the passivation layer. The following will be described in detail through specific embodiments.

[0029] Please refer to Figure 1 and Figure 2 , the present utility model proposes a semiconductor test structure, which may include pads 10, a top metal layer 20, a bottom metal layer 30, and a passivation layer. Among them, the number of pads 10 is multiple. The pads 10 are the basic components of surface mount assembly and are used to form the pad pattern of the circuit board. The top metal layer 20 and the bottom metal layer 30 can be disposed in the substrate of the wafer. The top metal layer 20 and the bottom metal layer 30 are metal layers with different heights, and the top metal layer 20 and the bottom metal layer 30 can be two adjacent metal layers up and down. The top metal layer 20 is located on top of the bottom metal layer 30, and a passivation layer (not shown in the figure) is provided between the top metal layer 20 and the bottom metal layer 30.

[0030] Specifically, as Figure 1 and Figure 2 shown, the top metal layer 20 may include multiple metal wires, and the bottom metal layer 30 may include multiple metal wires. For the convenience of description, the metal wires of the top metal layer 20 are denoted as top metal wires. Similarly, the metal wires on the bottom metal layer 30 are denoted as bottom metal wires. Multiple top metal wires are connected to form the top metal layer 20. The top metal layer 20 can be a continuously arranged metal chain, and the two ends of the top metal layer 20 are the first test ends. Multiple bottom metal wires are connected to form the bottom metal layer 30. The bottom metal layer 30 can be a continuously arranged metal chain, and the two ends of the bottom metal layer 30 are the second test ends.

[0031] Specifically, as Figure 1 and Figure 2 shown, after connecting the multiple bottom metal wires of the bottom metal layer 30 and after connecting the multiple top metal wires of the top metal layer 20, multiple pads 10 can be disposed inside the top metal layer 20, and then a passivation layer (not shown in the figure) is deposited above the top metal layer 20 and the multiple pads 10. After the passivation layer is cured, a passivation layer is provided between the bottom metal layer 30 and the top metal layer 20, and a passivation layer is provided between the top metal layer 20 and the multiple pads 10.

[0032] In addition, on the top of the passivation layer, as Figure 1As shown, an opening can be made at the position corresponding to the pad 10. A metal wire is passed through the opening and then connected to the pad 10, so that the pad 10 can be externally connected to a pin. By providing a passivation layer, and when there are no cracks in the passivation layer, the underlying metal layer 30, the top metal layer 20 and the plurality of pads 10 can be protected from foreign impurities and mechanical damage. However, if cracks occur in the passivation layer, the electrical properties of the underlying metal layer 30 and the top metal layer 20 will change, and there is a possibility of failure.

[0033] Please refer to Figure 1 and Figure 2 , in an embodiment of the present invention, before passivating the underlying metal layer 30 and the top metal layer 20, the resistance value of the first measurement end on the top metal layer 20 can be measured, and the resistance value of the second measurement end on the underlying metal layer 30 can be measured. After passivating the underlying metal layer 30 and the top metal layer 20, the resistance value of the first measurement end on the top metal layer 20 can be measured again, and the resistance value of the second measurement end on the underlying metal layer 30 can be measured again. Before and after passivating the underlying metal layer 30 and the top metal layer 20, the resistance values of the first measurement end and the second measurement end are compared to determine whether cracks occur in the passivation layer.

[0034] Specifically, after passivating the underlying metal layer 30 and the top metal layer 20, if the resistance value of the first measurement end becomes larger or cannot be detected, it indicates that cracks occur in the passivation layer at the top metal layer 20, resulting in bending of the top metal wires of the top metal layer 20 and an increase in resistance, or resulting in breakage of the top metal wires of the top metal layer 20 and the resistance cannot be detected. For the way cracks occur in the passivation layer at the top metal layer 20, it may be due to stress at the pad 10 causing cracks in the passivation layer, or stress at the corner of the top metal wire causing cracks in the passivation layer.

[0035] Specifically, after passivating the underlying metal layer 30 and the top metal layer 20, if the resistance value of the second measurement end becomes larger or cannot be detected, it indicates that cracks occur in the passivation layer at the underlying metal layer 30, resulting in bending of the bottom metal wires of the underlying metal layer 30 and an increase in resistance, or resulting in breakage of the bottom metal wires of the underlying metal layer 30 and the resistance cannot be detected. For the way cracks occur in the passivation layer at the underlying metal layer 30, it may be due to stress at the corner of the bottom metal wire causing cracks in the passivation layer.

[0036] Please refer to Figure 1 and Figure 2, in an embodiment of the present utility model, a plurality of pads 10 may be arranged in an array, for example, a rectangular array. The top metal lines of the top metal layer 20 may successively surround each pad 10.

[0037] Specifically, as Figure 1 shown, the connection direction of the two ends of the top metal layer 20 can be denoted as the horizontal direction, that is, the connection direction of the two ends corresponding to the first test end is denoted as the horizontal direction, and the direction perpendicular to the connection of the two ends corresponding to the first test end is denoted as the vertical direction. The plurality of pads 10 in the horizontal direction can be denoted as multiple rows of pads 10, and the plurality of pads 10 in the vertical direction can be denoted as multiple columns of pads 10.

[0038] Specifically, after the metal line of the top metal layer 20 surrounds a certain pad 10 in the clockwise direction, it surrounds the adjacent pad 10 in the same row as this pad 10 in the counterclockwise direction, and then surrounds the adjacent pad 10 in the same column as this pad 10 in the clockwise direction. Or, after the metal line of the top metal layer 20 surrounds a certain pad 10 in the clockwise direction, it surrounds the adjacent pad 10 in the same column as this pad 10 in the counterclockwise direction, and then surrounds the adjacent pad 10 in the same row as this pad 10 in the clockwise direction.

[0039] That is, the top metal lines of the top metal layer 20 can successively surround each pad 10. When cracks are generated in the passivation layer due to stress at the pad 10, it will affect the top metal lines around this pad 10. After the electrical detection of the first test end, the situation of cracks generated in the passivation layer can be efficiently and accurately detected.

[0040] Please refer to Figure 1 and Figure 2 , in an embodiment of the present utility model, the width of the top metal lines of the top metal layer 20 is denoted as the first width, the distance between the top metal lines of the top metal layer 20 and the pad 10 is denoted as the distance width, and the first width is the same as the distance width. The side length of the pad 10 is denoted as the side length width, and the ratio between the first width and the side length width is 1 / 15 to 1 / 10.

[0041] Specifically, the width of the top metal lines of the top metal layer 20 can be 2um to 3um, the distance between the top metal lines of the top metal layer 20 and the pad 10 can be 2um to 3um. The side length of the pad 10 can be 30um to 40um, then the ratio between the width of the top metal lines of the top metal layer 20 and the side length of the pad 10 can be 1 / 20 to 1 / 10.

[0042] Please refer to Figure 1 and Figure 2, in an embodiment of the present utility model, on the projection of multiple pads 10 on the plane where the bottom metal layer 30 is located, the bottom metal lines of the bottom metal layer 30 successively surround each pad 10. The bottom metal lines of the bottom metal layer 30 and the top metal lines of the top metal layer 20 can be correspondingly arranged. However, since the bottom metal layer 30 and the top metal layer 20 are located on different planes, the bottom metal lines of the bottom metal layer 30 do not directly surround each pad 10 successively.

[0043] Specifically, the bottom metal lines of the bottom metal layer 30 and the top metal lines of the top metal layer 20 can be correspondingly arranged, that is, the trajectory of the top metal lines of the top metal layer 20 corresponds to the trajectory of the bottom metal lines of the bottom metal layer 30. As Figure 2 shown, for example, for a section of the top metal line, the bottom metal line extends along the first side of the top metal line to the second side of the top metal line, and then extends along the second side of the top metal line to the first side of the top metal line, and the bottom metal line is periodically wired along the top metal line.

[0044] Specifically, the length of the metal chain formed by connecting the top metal lines of the top metal layer 20 is denoted as the first length, the length of the metal chain formed by connecting the bottom metal lines of the bottom metal layer 30 is denoted as the second length, and the ratio of the second length to the first length can be 2 to 4. The width of the bottom metal lines of the bottom metal layer 30 is denoted as the second width, the width of the bottom metal lines of the bottom metal layer 30 can be 0.2um to 0.4um, and the ratio of the first width to the second width is 5 to 10.

[0045] Please refer to Figure 1 , in an embodiment of the present utility model, both ends of the top metal layer 20 are the first test ends. Specifically, the top metal layer 20 can include a top first end 210, a top second end 220, a top third end 230, and a top fourth end 240. The top first end 210 and the top second end 220 can be located on one side of the top metal layer 20, and the top third end 230 and the top fourth end 240 can be located on the other side of the top metal layer 20. One of the top first end 210 and the top second end 220 can be selected, and then one of the top third end 230 and the top fourth end 240 can be selected and combined to form the first test end.

[0046] Please refer to Figure 2, in an embodiment of the present utility model, both ends of the bottom metal layer 30 are the second test ends. Specifically, the bottom metal layer 30 may include a bottom first end 310, a bottom second end 320, a bottom third end 330, and a bottom fourth end 340. The bottom first end 310 and the bottom second end 320 may be located on one side of the bottom metal layer 30, and the bottom third end 330 and the bottom fourth end 340 may be located on the other side of the bottom metal layer 30. One of the bottom first end 310 and the bottom second end 320 can be selected, and then one of the bottom third end 330 and the bottom fourth end 340 can be selected to form the second test end.

[0047] In an embodiment of the present utility model, a wafer can also be proposed. The wafer includes a substrate, and the above-mentioned semiconductor test structure is provided in the substrate. By electrically testing the top metal layer 20 outside the pad 10 or the bottom metal layer 30 at the bottom of the pad 10 in the substrate of the wafer, it can be detected whether there are cracks in the passivation layer and the specific position where the passivation layer has cracks.

[0048] In summary, the present utility model proposes a semiconductor test structure and a wafer. In the semiconductor test structure, after depositing a passivation layer above the bottom metal layer, the top metal layer, and the pad, a first test end is led out from the top metal layer, and a second test end is led out from the bottom metal layer. By electrically testing the top metal layer outside the pad or the bottom metal layer at the bottom of the pad, it can be detected whether there are cracks in the passivation layer and the specific position where the passivation layer has cracks. The present utility model electrically tests the top metal layer and the bottom metal layer corresponding to the passivation layer, can quickly and efficiently detect whether there are cracks in the passivation layer, and improves the detection efficiency of the semiconductor test structure.

[0049] The above embodiments are only illustrative of the principles and effects of the present utility model, and are not used to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present utility model should still be covered by the claims of the present utility model. As used in the description herein and throughout the claims below, unless otherwise specified, "a" and "the" include plural referents. Similarly, as used in the description herein and throughout the claims below, unless otherwise specified, "in..." means "in..." and "on...".

Claims

1. A semiconductor test structure, characterized in that: include: Multiple pads; A top metal layer is arranged in the substrate, the plurality of pads are located inside the top metal layer, and two ends of the top metal layer are first ends to be tested; A bottom metal layer is arranged in the substrate, and two ends of the bottom metal layer are second ends to be tested; A passivation layer is provided between the bottom metal layer and the top metal layer, and between the top metal layer and the plurality of pads.

2. The semiconductor test structure according to claim 1, characterized in that: The plurality of pads are arranged in an array, and the metal wire of the top metal layer surrounds each of the pads in sequence.

3. The semiconductor test structure according to claim 2, characterized in that: The metal wire of the top metal layer is wound around a certain pad in a clockwise direction, and then is wound around an adjacent pad in the same row as the pad in a counterclockwise direction, and then is wound around an adjacent pad in the same column as the pad in a clockwise direction; The metal wire of the top metal layer is wound around a certain pad in a clockwise direction, and then is wound around an adjacent pad in the same column of the pad in a counterclockwise direction, and then is wound around an adjacent pad in the same row of the pad in a clockwise direction.

4. The semiconductor test structure according to claim 2, characterized in that: The width of the metal line of the top metal layer is recorded as a first width, and the spacing between the metal line of the top metal layer and the pad is recorded as a spacing width, and the first width is the same as the spacing width.

5. The semiconductor test structure according to claim 4, characterized in that: The side length of the pad is recorded as the side length width, and the ratio of the first width to the side length width is 1 / 15 to 1 / 10.

6. The semiconductor test structure according to claim 3, characterized in that: The plurality of pads are on a projection of a plane where the bottom metal layer is located, and a metal line of the bottom metal layer surrounds each of the pads in sequence.

7. The semiconductor test structure according to claim 6, characterized in that: The metal line traces of the top metal layer correspond to the metal line traces of the bottom metal layer.

8. The semiconductor test structure according to claim 7, characterized in that: The metal line of the top metal layer is recorded as a top metal line, and the metal line of the bottom metal layer is recorded as a bottom metal line; For one section of the top metal line, the bottom metal line extends from a first side of the top metal line to a second side thereof and then extends from the second side of the top metal line to the first side thereof, and the bottom metal line is periodically wired along the top metal line.

9. The semiconductor test structure according to claim 6, characterized in that: The metal line width of the top metal layer is recorded as a first width, the metal line width of the bottom metal layer is recorded as a second width, and the ratio of the first width to the second width is 5-10.

10. A wafer, characterized in that: The invention comprises a substrate, wherein the semiconductor test structure according to any one of claims 1 to 9 is arranged in the substrate.

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