Clock switching circuit

Abstract

The utility model discloses a clock switching circuit which comprises a signal input unit, a first buffer, a second buffer and an output selection unit, and the signal input unit is used for inputting an initial clock signal, amplifying the initial clock signal into a first clock signal and outputting the first clock signal. The input end of the first buffer is connected with the signal input unit for inputting a first clock signal. The input end of the second buffer is used for inputting a second clock signal. The output selection unit is connected with the signal input unit for inputting a first clock signal, and the output selection unit is connected with an enabling end of the first buffer for controlling the first buffer to work under the condition that the first clock signal is input so as to output the first clock signal; and the output selection unit is connected with the enabling end of the second buffer and is used for controlling the second buffer to work under the condition that the first clock signal is not input so as to output a second clock signal.

Description

Technical Field

[0001] This application relates to the technical field of clock circuits, and particularly to a clock switching circuit. Background Art

[0002] In many high-speed digital electronic devices and systems, a high-precision and high-stability clock signal is required as the system clock to ensure the stable operation of the system. In the related art, a single clock source is usually used to provide the clock signal. When the electronic device and system need to change the clock signal according to requirements, it cannot be flexibly switched. Utility Model Content

[0003] This application aims to propose a clock switching circuit, which can solve the problem that the traditional clock circuit cannot flexibly switch the clock signal.

[0004] An embodiment of this application provides a clock switching circuit, including:

[0005] A signal input unit, which is used to input an initial clock signal and amplify the initial clock signal to output a first clock signal;

[0006] A first buffer, the input end of the first buffer is connected to the signal input unit to input the first clock signal;

[0007] A second buffer, the input end of the second buffer is used to input a second clock signal;

[0008] An output selection unit, the output selection unit is connected to the signal input unit to input the first clock signal, the output selection unit is connected to the enable end of the first buffer to control the first buffer to work and output the first clock signal when the first clock signal is input, and the output selection unit is connected to the enable end of the second buffer to control the second buffer to work and output the second clock signal when the first clock signal is not input.

[0009] According to some embodiments of this application, the signal input unit includes:

[0010] A first triode, the base of the first triode is used to input the initial clock signal, and the emitter of the first triode is grounded;

[0011] A second triode, the base of the second triode is connected to the collector of the first triode, the emitter of the second triode is grounded, and the collector of the second triode is used to output the first clock signal.

[0012] According to some embodiments of this application, the first triode is a high-frequency triode.

[0013] According to some embodiments of the present application, the second triode is a high-frequency triode.

[0014] According to some embodiments of the present application, it further includes:

[0015] A clock distribution unit, the input end of the clock distribution unit is connected to the signal input unit, the first output end of the clock distribution unit is connected to the input end of the first buffer, and the second output end of the clock distribution unit is connected to the output selection unit.

[0016] According to some embodiments of the present application, the clock distribution unit includes a clock distributor, the input end of the clock distributor is connected to the signal input unit, the first output end of the clock distributor is connected to the input end of the first buffer, and the second output end of the clock distributor is connected to the output selection unit.

[0017] According to some embodiments of the present application, the output selection unit includes:

[0018] A switch sub-unit, one end of the switch sub-unit is used to connect to the power supply terminal, one end of the switch sub-unit is connected to the enable end of the first buffer, the other end of the switch sub-unit is grounded, and the control end of the switch sub-unit is connected to the signal input unit;

[0019] A third triode, the base of the third triode is connected to one end of the switch sub-unit, the collector of the third triode is connected to the power supply terminal, the collector of the third triode is connected to the enable end of the second buffer, and the emitter of the third triode is grounded.

[0020] According to some embodiments of the present application, the output selection unit further includes:

[0021] A diode, the positive pole of the diode is connected to the signal input unit, and the negative pole of the diode is connected to the control end of the switch sub-unit;

[0022] A first capacitor, one end of the first capacitor is connected to the negative pole of the diode, and the other end of the first capacitor is grounded.

[0023] According to some embodiments of the present application, the output selection unit further includes:

[0024] A fourth triode, the base of the fourth triode is connected to the signal input unit, the collector of the fourth triode is connected to the control end of the switch sub-unit, and the emitter of the fourth triode is grounded.

[0025] According to some embodiments of the present application, the switch sub-unit includes a MOS transistor. The drain of the MOS transistor is used to connect to the power supply terminal. The drain of the MOS transistor is connected to the enable terminal of the first buffer. The source of the MOS transistor is grounded, and the gate of the MOS transistor is connected to the signal input unit.

[0026] In the embodiments of the present application, the output selection unit controls the working states of the first buffer and the second buffer respectively according to whether a first clock signal is input. When the first clock signal is input to the output selection unit, the output selection unit controls the first buffer to work, so as to output the first clock signal. When the first clock signal is not input to the output selection unit, the output selection unit controls the second buffer to work, so as to output the second clock signal, realizing flexible switching of the clock signal.

[0027] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0028] The following further describes the present application in conjunction with the drawings and embodiments, where:

[0029] Figure 1 is the circuit diagram of the signal input unit in the embodiment of the clock switching circuit provided by the present application;

[0030] Figure 2 is the circuit diagram of the clock distribution unit in the embodiment of the clock switching circuit provided by the present application;

[0031] Figure 3 is the circuit diagram of the output selection unit in the embodiment of the clock switching circuit provided by the present application;

[0032] Figure 4 is the circuit diagram of the first buffer and the second buffer in the embodiment of the clock switching circuit provided by the present application. Detailed Description of the Embodiments

[0033] The following details the embodiments of the present application. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0034] In the description of the present application, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, etc., it is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0035] In the description of the present application, "a plurality of" means more than two. If the first and second are described, it is only for the purpose of distinguishing technical features, and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features or implicitly specifying the sequence relationship of the indicated technical features.

[0036] In the description of the present application, unless otherwise clearly defined, terms such as "arrangement", "installation", "connection", etc. should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present application in combination with the specific content of the technical solution.

[0037] The following refers to Figures 1 to 4 Describe a clock switching circuit according to an embodiment of the present application.

[0038] An embodiment of the present application provides a clock switching circuit, including:

[0039] A signal input unit, which is used to input an initial clock signal and amplify the initial clock signal into a first clock signal for output;

[0040] A first buffer U9, the input end of the first buffer U9 is connected to the signal input unit for inputting the first clock signal;

[0041] A second buffer U10, the input end of the second buffer U10 is used to input a second clock signal;

[0042] An output selection unit, the output selection unit is connected to the signal input unit for inputting the first clock signal, the output selection unit is connected to the enable end of the first buffer U9 for controlling the first buffer U9 to work and output the first clock signal when the first clock signal is input, and the output selection unit is connected to the enable end of the second buffer U10 for controlling the second buffer U10 to work and output the second clock signal when the first clock signal is not input.

[0043] In this embodiment, the signal input unit amplifies the initial clock signal into a first clock signal and outputs the first clock signal.

[0044] The output selection unit controls the operating states of the first buffer U9 and the second buffer U10 respectively according to whether the first clock signal is input. When the first clock signal is input to the output selection unit, the output selection unit controls the first buffer U9 to operate, so as to output the first clock signal. When the first clock signal is not input to the output selection unit, the output selection unit controls the second buffer U10 to operate, so as to output the second clock signal, realizing flexible switching of the clock signal. As Figure 1 shown, Figure 1 in which OutSize_10MHz_CLKIN represents the initial clock signal. As Figure 4 shown, Figure 4 Inner_10MHz_CLKIN in it represents the second clock signal.

[0045] In some embodiments of the present application, the models of the first buffer U9 and the second buffer U10 are AiP74LVC1G125, and the enable terminals of the first buffer U9 and the second buffer U10 are active low.

[0046] In some embodiments of the present application, the signal input unit can adopt a Schmitt trigger to convert the initial clock signal into the first clock signal.

[0047] In an embodiment of the present application, as Figure 1 shown, the signal input unit includes:

[0048] The first triode Q6, the base of the first triode Q6 is used to input the initial clock signal, and the emitter of the first triode Q6 is grounded;

[0049] The second triode Q4, the base of the second triode Q4 is connected to the collector of the first triode Q6, the emitter of the second triode Q4 is grounded, and the collector of the second triode Q4 is used to output the first clock signal.

[0050] In this embodiment, the initial clock signal is amplified into the first clock signal by the first triode Q6 and the second triode Q4.

[0051] Both the first triode Q6 and the second triode Q4 are high-frequency triodes, which can input the initial clock signal with a lower voltage, expanding the voltage range of the initial clock signal.

[0052] An embodiment of the present application further includes:

[0053] A clock distribution unit, the input end of the clock distribution unit is connected to the signal input unit, the first output end of the clock distribution unit is connected to the input end of the first buffer U9, and the second output end of the clock distribution unit is connected to the output selection unit.

[0054] In this embodiment, after the first clock signal is input into the clock distribution unit, the clock distribution unit distributes the first clock signal to the first output end and the second output end, so as to provide the first clock signal for the first buffer U9 and the output selection unit respectively, enabling the first buffer U9 and the output selection unit to work in the same clock cycle.

[0055] In an embodiment of the present application, the clock distribution unit includes a clock distributor U8. The input end of the clock distributor U8 is connected to the signal input unit. The first output end of the clock distributor U8 is connected to the input end of the first buffer U9, and the second output end of the clock distributor U8 is connected to the output selection unit.

[0056] In this embodiment, as Figure 2 shown, the clock distribution unit includes a clock distributor U8, which provides multiple first clock signals through the clock distributor U8. The clock distributor U8 outputs the first clock signal to the first buffer U9 and the output selection unit respectively. The model of the clock distributor U8 is CLB2305. The clock distributor U8 can convert the waveform of the first clock signal from a sine wave to a pulse wave and perform multi-channel output.

[0057] In an embodiment of the present application, as Figures 3 to 4 shown, the output selection unit includes:

[0058] A switch sub-unit, one end of the switch sub-unit is used to connect to the power supply terminal, one end of the switch sub-unit is connected to the enable terminal of the first buffer U9, the other end of the switch sub-unit is grounded, and the control terminal of the switch sub-unit is connected to the signal input unit;

[0059] A third triode Q9, the base of the third triode Q9 is connected to one end of the switch sub-unit, the collector of the third triode Q9 is connected to the power supply terminal, the collector of the third triode Q9 is connected to the enable terminal of the second buffer U10, and the emitter of the third triode Q9 is grounded.

[0060] In this embodiment, the first clock signal is input to the control terminal of the switch sub-unit, causing the switch sub-unit to conduct. The enable terminal of the first buffer U9 is pulled to a low level, and the first buffer U9 works, outputting the first clock signal. When the switch sub-unit conducts, the base of the third triode Q9 is pulled to a low level, and the collector of the third triode Q9 correspondingly changes to a high level, causing the enable terminal of the second buffer U10 to be pulled to a high level, and the second buffer U10 does not work.

[0061] In the absence of the input of the first clock signal, the switch sub-unit is disconnected, the enable terminal of the first buffer U9 is at a high level, and the first buffer U9 does not work. When the switch sub-unit is disconnected, the base of the third triode Q9 is at a high level, and the collector of the third triode Q9 is at a low level, so that the enable terminal of the second buffer U10 is pulled to a low level, and the second buffer U10 works, and the second buffer U10 outputs the second clock signal.

[0062] In some embodiments of the present application, the switch sub-unit uses the MOS transistor Q7. The drain of the MOS transistor Q7 is used to connect to the power supply terminal. The drain of the MOS transistor Q7 is connected to the enable terminal of the first buffer U9. The source of the MOS transistor Q7 is grounded, and the gate of the MOS transistor Q7 is connected to the signal input unit.

[0063] In an embodiment of the present application, as Figure 3 shown, the output selection unit further includes:

[0064] A diode D4, the positive electrode of the diode D4 is connected to the signal input unit, and the negative electrode of the diode D4 is connected to the control terminal of the switch sub-unit;

[0065] A first capacitor C47, one end of the first capacitor C47 is connected to the negative electrode of the diode D4, and the other end of the first capacitor C47 is grounded.

[0066] In this embodiment, when the signal input unit outputs the first clock signal to the diode D4, when the first clock signal is at a high level, the diode D4 conducts, the first capacitor C47 is charged, and the switch sub-unit conducts. When the first clock signal is at a low level, the diode D4 is cut off, the first capacitor C47 discharges, and the switch sub-unit maintains the conducting state, so that a continuous level output can be performed when the first clock signal is input, and the switch sub-unit is continuously conducted.

[0067] In an embodiment of the present application, as Figure 3 shown, the output selection unit further includes:

[0068] A fourth triode Q8, the base of the fourth triode Q8 is connected to the signal input unit, the collector of the fourth triode Q8 is connected to the control terminal of the switch sub-unit, and the emitter of the fourth triode Q8 is grounded.

[0069] In this embodiment, the first clock signal is input to the base of the fourth triode Q8, and after being amplified, it is output to the control terminal of the switch sub-unit.

[0070] In some embodiments of the present application, the base of the fourth triode Q8 is connected to the second output terminal of the clock distributor U8, so as to input the second clock signal to the base of the fourth triode Q8. The collector of the fourth triode Q8 is connected to the positive electrode of the diode D4, and the second clock signal is output to the positive electrode of the diode D4 through the collector of the fourth triode Q8.

[0071] The embodiments of the present application have been described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present application within the scope of knowledge possessed by those of ordinary skill in the art.

Claims

1. A clock switching circuit, characterized in that, Comprising: A signal input unit for inputting an initial clock signal and amplifying the initial clock signal to output a first clock signal; A first buffer, the input end of the first buffer is connected to the signal input unit for inputting the first clock signal; A second buffer, the input end of the second buffer is used for inputting a second clock signal; An output selection unit, the output selection unit is connected to the signal input unit for inputting the first clock signal, the output selection unit is connected to the enable end of the first buffer for controlling the first buffer to work when the first clock signal is input, so as to output the first clock signal, and the output selection unit is connected to the enable end of the second buffer for controlling the second buffer to work when the first clock signal is not input, so as to output the second clock signal.

2. The clock switching circuit according to claim 1, wherein The signal input unit includes: A first triode, the base of the first triode is used for inputting the initial clock signal, and the emitter of the first triode is grounded; A second triode, the base of the second triode is connected to the collector of the first triode, the emitter of the second triode is grounded, and the collector of the second triode is used for outputting the first clock signal.

3. The clock switching circuit according to claim 2, wherein: The first triode is a high-frequency triode.

4. The clock switching circuit according to claim 2, wherein: The second triode is a high-frequency triode.

5. The clock switching circuit according to claim 1, wherein Further comprising: A clock distribution unit, the input end of the clock distribution unit is connected to the signal input unit, the first output end of the clock distribution unit is connected to the input end of the first buffer, and the second output end of the clock distribution unit is connected to the output selection unit.

6. The clock switching circuit according to claim 5, wherein: The clock distribution unit includes a clock distributor, the input end of the clock distributor is connected to the signal input unit, the first output end of the clock distributor is connected to the input end of the first buffer, and the second output end of the clock distributor is connected to the output selection unit.

7. The clock switching circuit according to claim 1, wherein The output selection unit includes: A switch sub-unit, one end of the switch sub-unit is used for connecting a power supply terminal, one end of the switch sub-unit is connected to the enable end of the first buffer, the other end of the switch sub-unit is grounded, and the control end of the switch sub-unit is connected to the signal input unit; A third triode, the base of the third triode is connected to one end of the switch sub-unit, the collector of the third triode is connected to the power supply terminal, the collector of the third triode is connected to the enable end of the second buffer, and the emitter of the third triode is grounded.

8. The clock switching circuit according to claim 7, wherein The output selection unit further includes: A diode, the positive pole of the diode is connected to the signal input unit, and the negative pole of the diode is connected to the control end of the switch sub-unit; A first capacitor, one end of the first capacitor is connected to the negative pole of the diode, and the other end of the first capacitor is grounded.

9. The clock switching circuit according to claim 7, wherein The output selection unit further includes: The fourth triode, the base of the fourth triode is connected to the signal input unit, the collector of the fourth triode is connected to the control end of the switch sub-unit, and the emitter of the fourth triode is grounded.

10. The clock switching circuit according to claim 7, characterized in that: The switch sub-unit includes a MOS transistor, the drain of the MOS transistor is used to connect to the power supply terminal, the drain of the MOS transistor is connected to the enable end of the first buffer, the source of the MOS transistor is grounded, and the gate of the MOS transistor is connected to the signal input unit.

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